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* ARM: dts: vfxxx: add missing reg propertiesStefan Agner2016-04-131-0/+1
| | | | | | | | | | | | | | Add missing reg properties to AIPS bus and Cortex-A5's PMU unit. This change avoids the following warnings: Warning (unit_address_vs_reg): Node /soc/aips-bus@40000000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000/pmu@40089000 has a unit name, but no reg property Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: dts: vf610: add performance monitoring unitStefan Agner2016-02-291-0/+9
| | | | | | | | | All Freescale Vybrid SoC include a Cortex-A5 core which supports ARM's standard PMU (performance monitoring unit). Include the monitoring unit into the Cortex-A5 base device tree vf500.dtsi. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: dts: vf610: relicense vf???.dtsi under GPLv2/X11Stefan Agner2016-02-291-4/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPLv2-only devicetrees make reuse difficult for software components licensed under a different license. The consensus is that a GPL/X11 dual-license should allow all necessary uses, so relicense the vfxxx.dtsi, vf500.dtsi and vf610.dtsi files to this combination. CCs were acquired using (updated some email addresses, commented out bouncing email addresses with --): git shortlog -sne --no-merges arch/arm/boot/dts/vf???.dtsi --CC: Chao Fu <B44548@freescale.com> CC: Cosmin Stoica <cosminstefan.stoica@freescale.com> CC: Frank Li <Frank.Li@freescale.com> CC: Fugang Duan <B38611@freescale.com> --CC: Huang Shijie <b32955@freescale.com> --CC: Jingchang Lu <jingchang.lu@freescale.com> --CC: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)Stefan Agner2015-03-301-137/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: vf610: add second DSPI instanceBhuvanchandra DV2015-03-301-0/+4
| | | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: vf610: use zero based naming for GPIO nodesStefan Agner2015-01-201-5/+5
| | | | | | | | | | | On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vfxxx: Add SNVS nodeSanchayan Maity2015-01-131-0/+4
| | | | | | | | | Add device tree node for the Secure Non-Volatile Storage (SNVS) on the VF610 platform. The SNVS block also has a Real Time Counter (RTC). Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: add system reset controller and syscon-rebootStefan Agner2015-01-051-0/+4
| | | | | | | | | Add the system reset controller (SRC) module and use syscon-reboot to register a restart handler which restarts the SoC using the SRC SW_RST bit. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: enable watchdog for Cortex-A5 dt'sStefan Agner2015-01-051-0/+5
| | | | | | | | | | During restructuring of the device tree files the watchdog was changed to be disabled by default. However, since the watchdog instance is dedicated to the Cortex-A5, enable the peripheral by default in the base device tree vf500.dtsi. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: vf610: create generic base device treesStefan Agner2014-11-231-0/+171
This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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