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path: root/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
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* ARM: vexpress: Fix wdt interrupt in ca15{-tc1,_a7} dtsMark Rutland2013-01-291-1/+1
| | | | | | | | | | | | As the wdt nodes have the gic as their interrupt-parent, their interrupts property should be 3 cells in format described in the gic devicetree binding document. This patch fixes the interrupts property in the wdt nodes to be in the correct format. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress: Remove motherboard dependencies in the DTS filesPawel Moll2012-11-051-3/+8
| | | | | | | | | | | The way the VE motherboard Device Trees were constructed enforced naming and structure of daughterboard files. This patch makes it possible to simply include the motherboard description anywhere in the main Device Tree and retires the "arm,v2m-timer" alias - any of the motherboard SP804 timers will be used instead. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress: Add config bus components and clocks to DTsPawel Moll2012-11-051-0/+110
| | | | | | | | Add description of all functions provided by Versatile Express motherboard and daughterboards configuration controllers and clock dependencies between devices. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addressesPawel Moll2012-07-131-18/+18
| | | | | | | ... to enable use of LPAE, which extends physical address space to 40 bits. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress: Device Tree updatesPawel Moll2012-05-211-1/+12
| | | | | | | | | | | | * Added extra regs for A15 VGIC * Added A15 architected timer node * Split A5 and A9 TWD nodes into two separate ones for timer and watchdog; interrupt definitions fixed on the way * Fixed typo in A5 GIC compatible value All the changes courtesy of Marc Zyngier. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)Pawel Moll2012-02-241-0/+157
This patch adds Device Tree file for the CoreTile Express A15x2 (V2P-CA15) with Test Chip 1. As the chip's GIC has 160 interrupt inputs and equivalent SMM (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is increased. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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