Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ARM: dts: mvebu: Correct license text | Alexandre Belloni | 2017-01-03 | 1 | -5/+5 |
| | | | | | | | | | | | | | | The license text has been mangled at some point then copy pasted across multiple files. Restore it to what it should be. Note that this is not intended as a license change. Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> | ||||
* | ARM: dts: mvebu: armada-390: add missing compatibility string and bracket | Grzegorz Jaszczyk | 2016-08-08 | 1 | -0/+3 |
| | | | | | | | | | | | | The armada-390.dtsi was broken since the first patch which adds Device Tree files for Armada 39x SoC was introduced. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: <stable@vger.kernel.org> # 4.0+ Fixes 538da83 ("ARM: mvebu: add Device Tree files for Armada 39x SoC and board") Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> | ||||
* | ARM: mvebu: add Device Tree files for Armada 39x SoC and board | Thomas Petazzoni | 2015-03-04 | 1 | -0/+57 |
This commit adds the Device Tree files for the Armada 39x family of processors, as well as one Armada 398 Development Board. Like for other Marvell EBU families, a common armada-39x.dtsi contains the description of the common features of all Armada 39x SoCs, while armada-390.dtsi and armada-398.dtsi respectively describe the specificities of those SoCs. Finally, an armada-398-db.dts file is added to describe the Armada 398 Development Board itself. So far, the following features are supported: * SMP: dual Cortex-A9 * Basic ARM IPs: SCU, timer, GIC, L2 cache * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus controller, MPIC interrupt controller, timer, CPU reset for SMP, PMSU. * I2C * SPI * SDHCI * XOR * NAND * UART * PCIe Additional features will be supported in the future. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> |