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* Merge tag 'pinctrl-v3.16-1' of ↵Linus Torvalds2014-06-038-10/+360
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
| * pinctrl: msm: Add more MSM8X74 pin definitionsAndy Gross2014-05-291-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pin definitiones for the MSM8x74 TLMM. New definitions include: BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins. Signed-off-by: Andy Gross <agross@codeaurora.org> Acked-By: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: Enable "power-source" to be extracted from DT filesIvan T. Ivanov2014-05-281-0/+1
| | | | | | | | | | | | | | | | | | Add "power-source" property to generic options used for DT parsing files. This enables drivers, which use generic pin configurations, to get the value passed to this property. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: add pinctrl driver for imx6sxAnson Huang2014-05-271-0/+36
| | | | | | | | | | | | | | | | | | Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core driver. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: adapt rockchip-pinctrl doc to changed bindingsHeiko Stübner2014-05-091-8/+20
| | | | | | | | | | | | | | | | | | Introduce the syscons for grf and pmu and deprecate the previous register areas. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: do not require 2nd register areaHeiko Stübner2014-05-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | Deprecate secondary register area for rk3188 pulls. Instead use big enough initial mapping of grf registers to catch all. The now deprecated register is still supported though. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mvebu: new driver for Orion platformsThomas Petazzoni2014-04-241-0/+91
| | | | | | | | | | | | | | | | | | | | | | This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt: Document Qualcomm IPQ8064 pinctrl bindingAndy Gross2014-04-231-0/+95
| | | | | | | | | | | | | | | | | | Define a new binding for the Qualcomm TLMMv2 based pin controller inside the IPQ8064. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: sunxi: list all pinctrl compatible stringsBoris BREZILLON2014-04-231-2/+7
| | | | | | | | | | | | | | | | List all sunxi pinctrl compatible strings in order to be able to grep for those values. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Add documentation for pinctrl-apq8064 bindingBjorn Andersson2014-04-221-0/+88
| | | | | | | | | | | | | | DT bindingdocumentation for qcom,apq8064-pinctrl driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt: Fix binding typos in clock-names and interrupt-namesGeert Uytterhoeven2014-04-231-2/+2
|/ | | | | | | | | | | | | s/interrupts-names/interrupt-names/g s/clocks-names/clock-names/g Some of the binding files and device tree files get this wrong and the kernel won't be able to pick it up. Fix them up now so that they don't get widely used. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by : Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Grant Likely <grant.likely@linaro.org>
* pinctrl: fix typo in bindings documentationSherman Yin2014-04-141-1/+1
| | | | | | | Fixed the missing comma in DT node example. Signed-off-by: Sherman Yin <syin@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v3.15-1' of ↵Linus Torvalds2014-04-0111-14/+249
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
| * devicetree: bindings: Make msm8974-pinctrl documentation match codeStephen Boyd2014-03-071-7/+7
| | | | | | | | | | | | | | | | | | | | The compatible string doesn't have an x in it. Fix it. Also remove the "qcom" prefix from pins and functions as this binding uses the generic pinctrl bindings for the pins and functions. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge branch 'pinctrl-mvebu' into develLinus Walleij2014-03-037-1/+167
| |\
| | * Merge tag 'tags/for-mvebu-pinctrl-3xx' into mvebu/pinctrlJason Cooper2014-03-012-0/+162
| | |\ | | | | | | | | | | | | Sign for-mvebu/pinctrl-3xx
| | | * pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385Thomas Petazzoni2014-02-251-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| | | * pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375Thomas Petazzoni2014-02-251-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Armada 375 is a new ARM SoC from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | devicetree: bindings: update MVEBU pinctrl binding documentationSebastian Hesselbarth2014-02-255-1/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | Dove pinctrl binding now requires three different reg properties. This updates corresponding binding and example accordingly. While at it, also document reg property as required for the other MVEBU SoC pinctrl nodes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| * | pinctrl: exynos: add exynos5260 SoC specific dataYoung-Gun Jang2014-02-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds pinctrl support for all platforms based on EXYNOS5260 SoC. Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: single: add low power mode supportChao Xie2014-02-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some silicons, the pin configuration register can control the output of the pin when the pad including the pin enter low power mode. For example, the pin can be "Drive 1", "Drive 0", "Float" when the pad including the pin enter low power mode. It is very useful when you want to control the power leakeage when the SOC enter low power mode, and can save more power for the low power mode. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: st: Add Interrupt supportSrinivas Kandagatla2014-02-101-6/+67
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add interrupt support to the pincontroller driver. ST Pincontroller GPIO bank can have one of the two possible types of interrupt-wirings. First type is via irqmux, single interrupt is used by multiple gpio banks. This reduces number of overall interrupts numbers required. All these banks belong to a single pincontroller. _________ | |----> [gpio-bank (n) ] | |----> [gpio-bank (n + 1)] [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] | |----> [gpio-bank (... )] |_________|----> [gpio-bank (n + 7)] Second type has a dedicated interrupt per gpio bank. [irqN]----> [gpio-bank (n)] Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Rename Broadcom Capri pinctrl bindingSherman Yin2014-02-241-4/+4
|/ | | | | | | | | | | The compatible string of the Broadcom Capri pinctrl driver is renamed to "brcm,bcm11351-pinctrl" to match the machine binding here: Documentation/devicetree/bindings/arm/bcm/bcm11351.txt Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Christian Daudt <bcm@fixthebug.org>
* pinctrl: Add pinctrl binding for Broadcom Capri SoCsSherman Yin2014-01-161-0/+461
| | | | | | | | | | | | | | | | | | | | | Adds pinctrl driver devicetree binding for Broadcom Capri (BCM281xx) SoCs. v4: Changed valid values for "bias-pull-up" property for I2C pins. Expanded pin configuration node example. v3: Use generic pin config properties instead of brcm-specific ones. Clarified pin types (standard, i2c, hdmi). v2: Use hyphens instead of underscore in DT property names. Device tree bindings maintainers ECG: _ _ _ _ _ __________/ \ ________/ \ _____/ \ ___/ \ ___/ \ __ \_/ \_/ \_/ \_/ \_/ Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: single: fix DT bindings documentationTomi Valkeinen2014-01-151-1/+1
| | | | | | | | Remove extra comma in pinctrl-single documentation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Adds slew-rate, input-enable/disableSherman Yin2013-12-161-0/+3
| | | | | | | | This commit adds slew-rate and input-enable/disable support for pinconf -generic. Signed-off-by: Sherman Yin <syin@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl-msm: Rename compatible to be more specificBjorn Andersson2013-12-161-2/+2
| | | | | | | | Use the more specific form 8974 for the compatible to reduce the risk of future mishaps. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add devicetree binding document for Tegra124Laxman Dewangan2013-12-121-0/+144
| | | | | | | | | | | | | | | | | This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Changes from V1: - Referred the dt-binding header file on describing the nodes. Changes from V2: - Rewording reg properties. - drop drv_type as it is not applicable. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: Support GPIO to IRQ mapping specified IRQ resourcesLaurent Pinchart2013-12-121-0/+14
| | | | | | | | | | | | | | | | | | On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Add documentation for pinctrl-msm8x74Bjorn Andersson2013-12-061-0/+92
| | | | | | | This adds initial documentation for the pinctrl-msm8x74 driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinctrl-imx: add imx25 pinctrl driverDenis Carikli2013-11-251-0/+23
| | | | | | | | | | | | | | | | | | | | | | This is mostly cut and paste from the imx35 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx25.h. Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Eric Bénard <eric@eukrea.com> Signed-off-by: Denis Carikli <denis@eukrea.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: imx1-core populate subdevicesMarkus Pargmann2013-11-251-0/+22
| | | | | | | | Support gpio devicetree subnodes to allow a more detailed DT hardware description. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-for-v3.13-1' of ↵Linus Torvalds2013-11-126-22/+244
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Main pin control pull request for the v3.13 cycle. The changes hitting arch/blackfin are ACKed by the Blackfin maintainer, and the device tree bindings are ACKed to the extent possible by someone from the device tree maintainers group. - Blackfin ADI pin control driver, we move yet another architecture under this subsystem umbrella. - Incremental updates to the Renesas Super-H PFC pin control driver. New subdriver for the r8a7791 SoC. - Non-linear GPIO ranges from the gpiolib side of things, this enabled simplified device tree bindings by referring entire groups of pins on some pin controller to act as back-end for a certain GPIO-chip driver. - Add the Abilis TB10x pin control driver used on the ARC architecture. Also the corresponding GPIO driver is merged through this tree, so the ARC has full support for pins and GPIOs after this. - Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin controller instances. The i.MX1 and i.MX27 is an entirely new family (silicon) of controllers whereas i.MX50 is a variant of the previous supported controller. - Then the usual slew of fixes, cleanups and incremental updates" The ARC DT changes are apparently still pending, that hopefully gets sorted out in a timely manner. * tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits) pinctrl: imx50: add pinctrl support code for the IMX50 SoC pinctrl: at91: copy define to driver pinctrl: remove minor dead code pinctrl: imx: fix using pin->input_val wrongly pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe() gpio: tb10x: fix return value check in tb10x_gpio_probe() gpio: tb10x: use module_platform_driver to simplify the code pinctrl: imx27: imx27 pincontrol driver pinctrl: imx1 core driver pinctrl: sh-pfc: r8a7791 PFC support sh-pfc: r8a7778: Add CAN pin groups gpio: add TB10x GPIO driver pinctrl: at91: correct a few typos pinctrl: mvebu: remove redundant of_match_ptr pinctrl: tb10x: use module_platform_driver to simplify the code pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe() pinctrl: add documentation for pinctrl_get_group_pins() pinctrl: rockchip: emulate both edge triggered interrupts pinctrl: rockchip: add rk3188 specifics pinctrl: rockchip: remove redundant check ...
| * pinctrl: imx27: imx27 pincontrol driverMarkus Pargmann2013-10-291-0/+99
| | | | | | | | | | | | | | | | | | | | imx27 pincontrol driver using the imx1 core driver. The DT bindings are similar to other imx pincontrol drivers. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: add rk3188 specificsHeiko Stübner2013-10-161-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | Besides the pull registers sitting in a separate place, the rk3188 also has the peculiarity that the pull registers of the first bank are split and the first half is sitting in the register space of the pmu. Therefore this adds a special bank-type for the first bank, to handle the two register sources. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: add TB10x pin control driverChristian Ruppert2013-10-161-0/+80
| | | | | | | | | | | | | | | | | | The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs. Used to control the pinmux and is a prerequisite for the GPIO driver. Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx: update fsl,pins description in bindings docShawn Guo2013-10-091-19/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | While commit e164153 (pinctrl: imx: move hard-coding data into device tree) moves to use DTC macro for imx pinctrl device tree setting, it changes the semantics of fsl,pins without updating the bindings doc properly. Let's update the fsl,pins description to stop confusing people. While at it, the example in the document is updated, and the stale TODO gets removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: palmas: remove pin config BIAS_PULL_PIN_DEFAULT supportLaxman Dewangan2013-10-081-1/+1
| | | | | | | | | | | | | | | | | | Palmas devices do not support the default bias configuration and hence removing this option from valid pin config parameters. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: at91/at91-pinctrl documentation: add missing sam9x5 compatible stringBoris BREZILLON2013-09-271-1/+1
| | | | | | | | | | | | | | | | | | Add missing "atmel,at91sam9x5-pinctrl" compatible string to the documentation. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'imx-dt-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Olof Johansson2013-10-281-827/+32
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/dt From Shawn Guo: The imx/mxs device tree changes for 3.13: - Use macros for mxs pinctrl settings - New board support: VF610 Cosmic/Cosmic+, imx6q-udoo, MSR M28CU3 - Support DSPI device for vf610 - Add PCIe device for imx6qdl - Add UHS pinctrl states for imx6sl and imx6qdl - Display support for APF and imx51-babbage boards - Enable SPI NOR and USB for imx6sl-evk board - Enable LVDS for imx6q-sabrelite and SPDIF for imx6qdl-wandboard - Misc updates on boards: TX28, imx6qdl-wandboard, imx53-qsb etc. - Some random updates on imx51 device tree * tag 'imx-dt-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6: (44 commits) ARM: imx: imx6sl iomuxc syscon is compatible to imx6q ARM: dts: imx6sl-evk: enable the SPI NOR ARM: dts: imx6sl: add a pinctrl for ECSPI1 ARM: imx27: add missing #pwm-cells property ARM: dts: imx6sl: add pinctrl uhs states for usdhc ARM: dts: imx6qdl-sabresd: Add backlight support for lvds ARM: dts: imx51-babbage: Make DVI and WVGA panel functional ARM: imx27-apf27dev: Add framebuffer support ARM: imx51-apf51dev: Add parallel display support ARM: dts: imx53-qsb: Do not use GPIO1_8 as wakeup source ARM: dts: imx53-qsb: SDHC1 does not have cd-gpios ARM: dts: imx53-qsb: SDHC3 is connected in 8-bit mode ARM: dts: mxs: Add MSR M28CU3 board ARM: dts: imx6qdl-wandboard: Provide phy-reset-gpios ARM: dts: imx6qdl-sabresd: Provide phy-reset-gpios ARM: dts: imx6q-sabrelite: Add ethernet phy reset pin into hog ARM: dts: imx6qdl: add pcie device node ARM: dts: imx6q-udoo: Add initial board support ARM: dts: mxs: Add muxing options for the SSP2 MMC ARM: dts: add initial VF610 Cosmic/Cosmic+ board support ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: dts: mxs: add pinctrl header filesLothar Waßmann2013-09-261-827/+32
| |/ | | | | | | | | | | | | | | | | | | | | | | Remove the list of possible pin configurations from the documentation file and create header files containing those definitions. This eliminates the need for error-prone manual lookup of those values in the documentation and guarantees consistency between the human readable representation of the pad function in the .dts file and the actual binary value used in DT. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | pinctrl: single: Add support for wake-up interruptsTony Lindgren2013-10-101-0/+11
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin control registers can have interrupts for example for device wake-up. These interrupts can be treated as a chained interrupt controller as suggested earlier by Linus Walleij <linus.walleij@linaro.org>. This patch adds support for interrupts in a way that should be pretty generic, and works for the omaps that support wake-up interrupts. On omaps, there's an interrupt enable and interrupt status bit for each pin. The two pinctrl domains on omaps share a single interrupt from the PRM chained interrupt handler. Support for other similar hardware should be easy to add. Note that this patch does not attempt to handle the wake-up interrupts automatically unlike the earlier patches. This patch allows the device drivers to do a request_irq() on the wake-up pins as needed. I'll try to do also a separate generic patch for handling the wake-up events automatically. Also note that as this patch makes the pinctrl-single an irq controller, the current bindings need some extra trickery to use interrupts from two different interrupt controllers for the same driver. So it might be worth waiting a little on the patches enabling the wake-up interrupts from drivers as there should be a generic way to handle it coming. And also there's been discussion of interrupts-extended binding for using interrupts from multiple interrupt controllers. In any case, this patch should be ready to go allowing handling the wake-up interrupts in a generic way, or separately from the device drivers. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: Roger Quadros <rogerq@ti.com> Cc: linux-kernel@vger.kernel.org Cc: Benoît Cousson <bcousson@baylibre.com> Cc: devicetree@vger.kernel.org Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge tag 'dt-for-linus' of ↵Linus Torvalds2013-09-064-3/+37
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "Device tree and bindings updates for 3.12. General additions of various on-chip and on-board peripherals on various platforms as support gets added. Some of the bigger changes are: - Addition of (new) PCI-e support on Tegra. - More Tegra4 support, including PMC configuration for Dalmore. - Addition of a new board for Exynos4 (trats2) and more bindings for 4x12 IP. - Addition of Allwinner A20 and A31 SoC and board files. - Move of the ST Ericsson device tree files to now use ste-* prefix. - More move of hardware description of shmobile platforms to DT. - Two new board dts files for Freescale MXs" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (177 commits) dts: Rename DW APB timer compatible strings dts: Deprecate ALTR as a vendor prefix of: add vendor prefix for Altera Corp. ARM: at91/dt: sam9x5ek: add sound configuration ARM: at91/dt: sam9x5ek: enable SSC ARM: at91/dt: sam9x5ek: add WM8731 codec ARM: at91/dt: sam9x5: add SSC DMA parameters ARM: at91/dt: add at91rm9200 PQFP package version ARM: at91: at91rm9200: set default mmc0 pinctrl-names ARM: at91: at91sam9n12: correct pin number of gpio-key ARM: at91: at91sam9n12: add qt1070 support ARM: at91: at91sam9n12: add pinctrl of TWI ARM: at91: Add PMU support for sama5d3 ARM: at91: at91sam9260: add missing pinctrl-names on mmc ARM: tegra: configure power off for Dalmore ARM: DT: binding fixup to align with vendor-prefixes.txt (DT) ARM: dts: add sdio blocks to bcm28155-ap board ARM: dts: align sdio numbers to HW definition ARM: sun7i: Add Olimex A20-Olinuxino-Micro support ARM: sun7i: Add Allwinner A20 DTSI ...
| * Merge tag 'tegra-for-3.12-dt' of ↵Kevin Hilman2013-08-203-0/+34
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt From: Stephen Warren: ARM: tegra: device tree changes for 3.12 This branch contains all *.dts (device tree) changes for Tegra. New features enabled are: * PMICs on Dalmore * CPU power-gating on Dalmore * HDMI output on Beaver * LP1 system suspend mode on almost all boards * PCIe support on numerous Tegra20/30 boards * USB support on Tegra30/114 boards * Audio capture on Beaver and Dalmore * Temperature sensor on Cardhu. ... along with a few DT cleanups. * tag 'tegra-for-3.12-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits) ARM: tegra: add Mic Jack to Dalmore device tree ARM: tegra: add Mic Jack to Beaver device tree ARM: tegra: add USB DT entries for Tegra114, Dalmore ARM: tegra: add USB DT entries for Tegra30 ARM: dts: tegra: Increase prefetchable PCI memory space ARM: tegra: Fix Beaver's PCIe lane configuration ARM: tegra: Enable PCIe controller on Beaver ARM: tegra: Enable PCIe controller on Cardhu ARM: tegra: Add Tegra30 PCIe support ARM: tegra: trimslice: Initialize PCIe from DT ARM: tegra: harmony: Initialize PCIe from DT ARM: tegra: tec: Add PCIe support ARM: tegra: tamonten: Add PCIe support ARM: tegra: Add Tegra20 PCIe support to DT ARM: tegra: enable LP1 suspend mode ARM: tegra: beaver: Enable HDMI output ARM: tegra: use TEGRA_GPIO() in a couple more places ARM: tegra: dalmore: fix the irq trigger type of Palmas MFD device ARM: tegra: define valid function names in DT document ARM: tegra: dalmore: add PM configurations for PMC ...
| | * ARM: tegra: define valid function names in DT documentLaxman Dewangan2013-07-303-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List valid values for the property "nvidia,function" in DT binding document of Tegra pincontrol. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren, whitespace fixes, grammar consistency fixes, section ordering fixes] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | Documentation: Update binding for Nomadik and DBx5x based platformsLee Jones2013-08-061-3/+3
| |/ | | | | | | | | | | | | Change compatible string to something more standard. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge branch 'for-linus' of ↵Linus Torvalds2013-09-061-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial Pull trivial tree from Jiri Kosina: "The usual trivial updates all over the tree -- mostly typo fixes and documentation updates" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (52 commits) doc: Documentation/cputopology.txt fix typo treewide: Convert retrun typos to return Fix comment typo for init_cma_reserved_pageblock Documentation/trace: Correcting and extending tracepoint documentation mm/hotplug: fix a typo in Documentation/memory-hotplug.txt power: Documentation: Update s2ram link doc: fix a typo in Documentation/00-INDEX Documentation/printk-formats.txt: No casts needed for u64/s64 doc: Fix typo "is is" in Documentations treewide: Fix printks with 0x%# zram: doc fixes Documentation/kmemcheck: update kmemcheck documentation doc: documentation/hwspinlock.txt fix typo PM / Hibernate: add section for resume options doc: filesystems : Fix typo in Documentations/filesystems scsi/megaraid fixed several typos in comments ppc: init_32: Fix error typo "CONFIG_START_KERNEL" treewide: Add __GFP_NOWARN to k.alloc calls with v.alloc fallbacks page_isolation: Fix a comment typo in test_pages_isolated() doc: fix a typo about irq affinity ...
| * | doc: Fix typo in doucmentationsMasanari Iida2013-07-251-1/+1
| |/ | | | | | | | | | | | | | | Correct typo (double words) in documentations. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | pinctrl: Add s5pv210 support to pinctrl-exynosMateusz Krawczuk2013-08-281-1/+2
| | | | | | | | | | | | | | | | | | This patch implements pinctrl support and adds device tree bindings for s5pv210. Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: palmas: add pincontrol driverLaxman Dewangan2013-08-141-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI Palmas series Power Management IC have multiple pins which can be configured for different functionality. This pins can be configured for different function. Also their properties like pull up/down, open drain enable/disable are configurable. Add support for pincontrol driver Palmas series device like TPS65913, TPS80036. The driver supports to be register from DT only. Changes from V1: - Add generic property for pins and functions in pinconf-generic. - Add APIs to map the DT and subnode. - Move common utils APIs to the pinctrl-utils from this file. - Update the binding document accordingly. Changes from V2: - Add ack by Lee. - Correct the binding docs. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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