| Commit message (Collapse) | Author | Age | Files | Lines |
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "i.MX SoC update for 4.6" from Shawn Guo:
- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups
* tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: Make reset_control_ops const
ARM: imx: Do L2 errata only if the L2 cache isn't enabled
ARM: imx: select ARM_CPU_SUSPEND only for imx6
ARM: mx25: Add basic suspend/resume support
ARM: imx: Add msl code support for imx6qp
ARM: imx: enable big endian mode
ARM: imx: use endian-safe readl/readw/writel/writew
ARM: imx7d: correct chip version information
ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D
ARM: imx6: fix cleanup path in imx6q_suspend_init()
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The imx_src_ops structure is never modified. Make it const.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped. The write to the L2-Cache controller from non-secure
world causes an imprecise external abort. This is needed in
scenarios where one of the cores runs an other OS, e.g. an RTOS.
For the i.MX6 specific L2 cache handling we missed this check.
Add it.
Signed-off-by: Marcel Grosshans <MarcelViktor.Grosshans@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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i.MX only needs to select ARM_CPU_SUSPEND manually for the
very specific case that CONFIG_PM_SLEEP is disabled and imx6
is used with CONFIG_PM enabled for runtime PM.
If we are building a kernel only for CPUs that are not using
the cpu_suspend() helper, we otherwise get a harmless
build warning:
warning: (ARCH_MXC && SOC_IMX23 && SOC_IMX28 && ARCH_PXA && MACH_MVEBU_V7 && ARCH_OMAP3 && ARCH_OMAP4 && SOC_OMAP5 && SOC_AM33XX && SOC_DRA7XX && ARCH_EXYNOS3 && ARCH_EXYNOS4 && EXYNOS5420_MCPM &&
EXYNOS_CPU_SUSPEND && ARCH_VEXPRESS_TC2_PM && ARM_BIG_LITTLE_CPUIDLE && ARM_HIGHBANK_CPUIDLE && QCOM_PM) selects ARM_CPU_SUSPEND which has unmet direct dependencies (ARCH_SUSPEND_POSSIBLE)
This moves the option to the SOC_IMX6 option that actually
requires it, in effect reverting commit f36b594f3754 ("ARM:
mach-imx: Select ARM_CPU_SUSPEND at ARCH_MXC level") that was
meant as a cleanup and unintentionally caused this warning.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Tested basic suspend/resume on a mx25pdk:
$ echo enabled > /sys/class/tty/ttymxc0/power/wakeup
$ echo mem > /sys/power/state
Then press any key in the serial console and the system wakes up.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q
Rev_2.0 to maximum the code reusability. The chip silicon number we
read from the ANADIG_DIGPROG is 0x630100. This patch add code to
identify it as i.MX6QP Rev_1.0 when print out the silicon version.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Enable ARM big-endian mode on mach-imx. This requires adding some
byte swapping in the debug functions (which otherwise hang forever)
and of course the secondary core bringup.
Tested (on top of 4.4) on i.MX6 HummingBoard quad-core (IMX6Q).
The patch is pretty much as suggested by Arnd Bergmann, thanks!
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Instead of __raw_*, define imx_* to *_relaxed and use those.
Using imx_* was requested by Arnd because *_relaxed tends to
indicate that the code was carefully reviewed to not require
any synchronisation and otherwise be safe, which isn't the
case here with the automatic conversion.
The conversion itself was done using the following spatch
(since that automatically adjusts the coding style unlike
a simple search&replace).
@@
expression E1, E2;
@@
-__raw_writel(E1, E2)
+imx_writel(E1, E2)
@@
expression E1, E2;
@@
-__raw_writew(E1, E2)
+imx_writew(E1, E2)
@@
expression E1;
@@
-__raw_readl(E1)
+imx_readl(E1)
@@
expression E1;
@@
-__raw_readw(E1)
+imx_readw(E1)
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The commond 'cat /sys/devices/soc0/revision' can
show correct soc version information.
"unknow revision" message in imx_print_silicon_rev()
will never work for digprog.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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i.MX7D Supported ARCH Timer.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The wrong pointer is passed to the ioumap function in the cleanup path
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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In an invalid randconfig build (fixed by another patch),
I ran across this warning:
arch/arm/include/debug/at91.S:18:0: error: "CONFIG_DEBUG_UART_VIRT" redefined [-Werror]
#define CONFIG_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS)
As Russell pointed out, we should never #define a macro starting
with CONFIG_ in a source file, as that is rather confusing.
This renames the macro to avoid the symbol clash.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Suggested-by: Russell King <linux@arm.linux.org.uk>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Merge "pxa changes for v4.6 cycle" from Robert Jarzmik:
This is a minor cycle with :
- cleanup fixes from Arnd, mainly build oriented and sparse type ones
- dma fixes for requestors above 32 (impacting mainly camera driver)
- some minor cleanup on pxa3xx device-tree side
* tag 'pxa-for-4.6' of https://github.com/rjarzmik/linux:
dmaengine: pxa_dma: fix the maximum requestor line
ARM: pxa: add the number of DMA requestor lines
dmaengine: mmp-pdma: add number of requestors
dma: mmp_pdma: Add the #dma-requests DT property documentation
ARM: pxa: pxa3xx device-tree support cleanup
ARM: pxa: don't select RFKILL if CONFIG_NET is disabled
ARM: pxa: fix building without IWMMXT
ARM: pxa: move extern declarations to pm.h
ARM: pxa: always select one of the two CPU types
ARM: pxa: don't select GPIO_SYSFS for MIOA701
ARM: pxa: mark unused eseries code as __maybe_unused
ARM: pxa: mark spitz_card_pwr_ctrl as __maybe_unused
ARM: pxa: define clock registers as __iomem
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The current number of requestor lines is limited to 31. This was an
error of a previous commit, as this number is platform dependent, and is
actually :
- for pxa25x: 40 requestor lines
- for pxa27x: 75 requestor lines
- for pxa3xx: 100 requestor lines
The previous testing did not reveal the faulty constant as on pxa[23]xx
platforms, only camera, MSL and USB are above requestor 32, and in these
only the camera has a driver using dma.
Fixes: e87ffbdf0697 ("dmaengine: pxa_dma: fix the no-requestor case")
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Vinod Koul <vinod.koul@intel.com>
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Declare the number of DMA requestor lines per platform :
- for pxa25x: 40 requestor lines
- for pxa27x: 75 requestor lines
- for pxa3xx: 100 requestor lines
This information will be used to activate the DMA flow control or not.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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The DMA chip has a fixed number of requestor lines used for flow
control. This number is platform dependent. The pxa_dma dma driver will
use this value to activate or not the flow control.
There won't be any impact on mmp_pdma driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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For pxa based platforms, the number of requestor lines should be
specified, so that the driver can check if the flow control should be
activated (when a requestor line is asked for) or not.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Rob Herring <robh@kernel.org>
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Clocks, timer and several other drivers have well defined and working
device-tree bindings. Clean-up the code to leave only the strict
minimum. The final goal will be to remove the lookup array.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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Bluetooth is only supported when network support is part of the kernel,
so it is a bit pointless to build the tosa-bt support without networking.
If we try anyway, we get a Kconfig warning:
warning: (TOSA_BT && H1940BT) selects RFKILL which has unmet direct dependencies (NET)
This adds a dependency on CONFIG_NET to avoid that case.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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When CONFIG_IWMMXT, the pxa3xx and pxa27x suspend/resume code
emits some xscale specific instructions, which are rejected
by the assembler, because gcc is built with -march=armv5
-mtune=xscale and passes that option to the assembler:
/tmp/cciHumzr.s:553: Error: selected processor does not support ARM mode `mra r2,r3,acc0'
/tmp/cciHumzr.s:605: Error: selected processor does not support ARM mode `mar acc0,r2,r3'
make[3]: *** [arch/arm/mach-pxa/pxa3xx.o] Error 1
/tmp/cci5MUNu.s:326: Error: selected processor does not support ARM mode `mra r2,r3,acc0'
/tmp/cci5MUNu.s:367: Error: selected processor does not support ARM mode `mar acc0,r2,r3'
make[3]: *** [arch/arm/mach-pxa/pxa27x.o] Error 1
Overriding with -Wa,-march=xscale no longer works, so instead
I'm adding an explict ".arch_extension" directive in all four inline
assembly statements, which should work even if they end up in a different
order in the assembly output.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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When CONFIG_IWMMXT is disabled, we get a warning in pxa3xx.c:
arch/arm/mach-pxa/pxa3xx.c: In function 'pxa3xx_cpu_pm_suspend':
arch/arm/mach-pxa/pxa3xx.c:109:2: error: ISO C90 forbids mixed declarations and code [-Werror=declaration-after-statement]
It turns out that there is an 'extern' declaration in the
middle of a function.
For consistency, this moves the declaration and two others from
the same file into pm.h.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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When all boards are disabled on PXA, we cannot build a kernel
because no CPU gets selected:
arch/arm/include/uapi/asm/swab.h:26:29: error: "__LINUX_ARM_ARCH__" is not defined [-Werror=undef]
This is a bit annoying for compile-testing, so I'm adding a line
that ensures that at all times, at least one of CPU_XSCALE or
CPU_XSC3 is set and we can at least continue building.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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GPIO_SYSFS is a common kernel functionality, not something
that a board specific Kconfig should have to worry about.
In MIOA701, we get a warning about the select when CONFIG_SYSFS
is disabled:
warning: (MACH_MIOA701) selects GPIO_SYSFS which has unmet direct dependencies (GPIOLIB && SYSFS)
This just removes the select and instead enables the symbol in
the defconfig file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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Two variables in eseries.c are used on multiple platforms,
but are not referenced when those are all disabled:
eseries.c:60:31: warning: 'e7xx_gpio_vbus' defined but not used [-Wunused-variable]
eseries.c:129:20: warning: 'eseries_register_clks' defined but not used [-Wunused-function]
Marking them __maybe_unused is the nicest way to ensure
that we never get the warning or end up with missing symbols
if we get it wrong.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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This function is only used when CONFIG_PCMCIA is enabled, otherwise
we get a harmless warning:
arch/arm/mach-pxa/spitz.c:204:13: warning: 'spitz_card_pwr_ctrl' defined but not used [-Wunused-function]
Marking it as __maybe_unused keeps the logic simple and avoids the
warning on randconfig builds.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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We should not dereference registers as pointers, so use readl/writel
instead for these registers.
The clock registers are accessed in multiple files, so we have to
change them all at once.
I stumbled over these registers while looking at something unrelated.
There are in fact other registers with the same problem, but I did
not try to address those at this point.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc
Merge "Allwinner core changes for 4.6" from Maxime Ripard:
Just introduce the A83T support.
* tag 'sunxi-core-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: Introduce Allwinner for A83T support
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Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
[maxime: Removed the clock protection code]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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http://github.com/Broadcom/stblinux into next/soc
Merge "Broadcom maintainers changes for 4.6" from Florian Fainelli:
This pull request contains MAINTAINERS file updates for Broadcom ARM-based SoCs:
- Florian updates the Broadcom BCM63xx ARM-based DSL SoCs to use the same mailing-list
and development tree as all the other Broadcom SoCS
* tag 'arm-soc/for-4.6/maintainers' of http://github.com/Broadcom/stblinux:
MAINTAINERS: ARM: BCM63xx: Update git and mailing-lists
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arm-bcm63xx.git has not been used for development, instead, all patches
have been added to stblinux.git, so reflect that. While at it, add
bcm-kernel-feedback-list@broadcom.com as a secondary list to include
submissions, and finally update LAKML to reflect that it is moderated.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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next/soc
Merge "Broadcom soc changes for 4.6" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoC/platform changes:
- Masahiro updates the Broadcom Northstar Plus SMP operations to be annotated
with const and __initconst
- Florian removes an unused variable in the Broadcom BCM63XX SMP code
* tag 'arm-soc/for-4.6/soc' of http://github.com/Broadcom/stblinux:
ARM: BCM63xx: Remove unused pmb_dn variable
ARM: bcm: use const and __initconst for smp_operations
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Introduced in commit 3f2a43c98d72b ("ARM: BCM63xx: Add secondary CPU PMB
initialization sequence"), but not used by the code.
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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This newly added code missed the global fixup by commit 75305275a721
("ARM: use const and __initconst for smp_operations"). So fix it now.
Also, add missing "static" qualifier.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Select the Alpine MSI controller driver when using an Alpine platform.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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next/soc
Merge "ARM: Xilinx Zynq patches for v4.6" from Michal Simek:
- SLCR early init
- Fix L2 cache data corruption
- Fix early printk uart setting
* tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: Move early printk virtual address to vmalloc area
ARM: zynq: address L2 cache data corruption
ARM: zynq: initialize slcr mapping earlier
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The patch
"ARM: 8432/1: move VMALLOC_END from 0xff000000 to 0xff800000"
(sha1: 6ff0966052c46efb53980b8a1add2e7b49c9f560)
has moved also start of VMALLOC area because size didn't change.
That's why origin location of vmalloc was
vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
and now is
vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
That's why uart virtual addresses need to be changed to reflect this new
memory setup. Starting address should be vmalloc start address.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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The Zynq has a bug where the L2 cache will return invalid data in some
circumstances unless the L2C_RAM register is set to 0x00020202 before the first
enabling of the L2 cache.
The Xilinx-recommended solution to this problem is to ensure that early one of
the earlier bootstages correctly initialize L2C_RAM, however, this issue wasn't
discovered and fixed until after their EDK/SDK 14.4 release. For systems built
prior to that, and which lack field-upgradable bootloaders, this issue still
exists and silent data corruption can be seen in the wild.
Fix these systems by ensuring L2C_RAM is properly initialized at the
earliest convenient moment prior to the L2 being brought up, which is
when the SLCR is first mapped.
The Zynq bug is described in more detail by Xilinx AR# 54190 as quoted
below.
Xilinx AR# 54190
http://www.xilinx.com/support/answers/54190.htm
Captured on 2014-09-24 14:43 -0500
= Description =
For proper L2 cache operation, the user code must program the
slcr.L2C_RAM register (address 0xF800_0A1C) to the value of
0x0002_0202 before enabling the L2 cache. The reset value
(0x0001_0101) might cause, very infrequently, the L2 cache to return
invalid data.
= Solution =
It is up to the user code (FSBL or other user code) to set the
slcr.L2C_RAM register to the value 0x0002_0202 before enabling the L2
cache.
Note: The L2 cache is disabled after reset and is not enabled by the
BootROM.
Note: The slcr.l2C_RAM register was previously reserved. It is added
in the Zynq-7000 AP SoC Technical Reference Manual (TRM) v1.5 as
"Reserved".
Thanks to Jaeden Amero for initial debugging and triage efforts.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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In preparation for performing additional configuration prior to bringing
up L2, move the slcr initialization earlier in the boot process.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
Merge "DaVinci EDMA enhancements for v4.6" from Sekhar Nori:
Pass dma_slave_map data to EDMA driver. This will help
migration to new DMA engine API for requesting
slave channels dma_request_chan().
* tag 'davinci-for-v4.6/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: dm646x: Add dma_slave_map to edma
ARM: davinci: dm644x: Add dma_slave_map to edma
ARM: davinci: dm365: Add dma_slave_map to edma
ARM: davinci: dm355: Add dma_slave_map to edma
ARM: davinci: devices-da8xx: Add dma_slave_map to edma
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: fix typos in code]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: typo fixes in code]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: typo fixes in code]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: fix map for edma1]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Updates for v4.6" from Simon Horman:
* Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains
* Move emev2_smp_ops to emev2
* Remove legacy map_io callbacks on r8a7740 and emev2 SoCs
* Migrate to generic l2c OF initialization on r8a7740
* tag 'renesas-soc-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains
ARM: shmobile: emev2: Move declaration of emev2_smp_ops to emev2.h
ARM: shmobile: emev2: Remove legacy machine_desc.map_io() callback
ARM: shmobile: r8a7740: Remove legacy machine_desc.map_io() callback
ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers
ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
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All supported Renesas ARM SoCs (except for Emma Mobile EV2) have clock
domains. Some SoCs also have power domains. To ensure proper operation
of on-SoC modules, module clocks must be ungated, and power domains must
be powered up when needed.
Currently the user can choose to build a kernel with power management
enabled or disabled:
- If CONFIG_PM=y, power domains and/or module clocks are handled
dynamically by Runtime PM and the generic power domain.
- If CONFIG_PM=n, power domains are assumed to be powered up by reset
state or by the boot loader, and module clocks are handled by the
legacy clock domain on driver (un)bind.
The latter is implemented using a platform bus notifier, which
applies not only to all on-SoC devices, but to all platform devices
present in the system.
To remove the dependency on implicit assumptions, and to get rid of the
peculiarities of the legacy clock domain, enable CONFIG_PM and
CONFIG_PM_GENERIC_DOMAINS unconditionally, for all Renesas ARM SoCs with
clock and/or power domains.
This does cause an increase in kernel size. Given bloat-o-meter reports
a modest increase of 26 KiB for an RZ/A1H kernel, this should not be a
problem, even when used on RZ/A1H with XIP and internal RAM only.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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make C=1:
arch/arm/mach-shmobile/smp-emev2.c:51:29: warning: symbol 'emev2_smp_ops' was not declared. Should it be static?
To fix this, move the forward declaration of emev2_smp_ops to a header
file, and include it where appropriate.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Commit FIXME ("ARM: shmobile: Consolidate SCU mapping code") removed the
last user of the static mapping on emev2-based systems. Remove the
mapping and the legacy machine_desc.map_io() callback.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Commit 37201ba5c99d0be8 ("ARM: shmobile: r8a7740: Migrate to generic l2c
OF initialization") removed the last user of the legacy "IOMEM()" macro
on r8a7740-based systems. Hence there's no longer a need to set up a
transparent mapping of system I/O registers. Remove the mapping and the
legacy machine_desc.map_io() callback.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Now all r8a7740-based platforms have been migrated to the generic l2c OF
initialization, it's no longer needed to map the L2 cache controller
registers from .map_io().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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