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* Lower clock frequency of FPGA I2C bus to mitigate read / write errorsdev-4.13Raptor Engineering Development Team2018-05-191-0/+1
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* Update MAX31785 setings on Talos systemsRaptor Engineering Development Team2018-05-191-6/+12
| | | | | Enable faster fan ramp up/down to avoid overshoot / fan speed oscillations Disable unnecessary temperature sensor watchdog
* Remove explicit chassis reset binding on Talos systemsRaptor Engineering Development Team2018-05-191-6/+0
| | | | This allows the reset button service to bind to the GPIO
* Remove DD1 VCS workaround GPIO hogRaptor Engineering Development Team2018-05-191-6/+0
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* Move the system speaker from PWM7 to GPION7 for software-mode beep ↵Raptor Engineering Development Team2018-05-191-7/+5
| | | | development The ASpeed device doesn't really support variable PWM frequencies, at least not enough for proper beep support
* Port commit e3fac12aa8172222281420bf2eb1b25b756e82c8 to TalosRaptor Engineering Development Team2018-05-191-1/+4
| | | | ARM: dts: aspeed: talos: Add w83773g temp sensor
* Port commit 052add4e0fd8d827b85382f584e53582ce621951 to TalosRaptor Engineering Development Team2018-05-191-0/+6
| | | | ARM: dts: aspeed: talos: hog GPIOS7
* Add chassis reset request input to BMC DTS for TalosRaptor Engineering Development Team2018-05-191-0/+6
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* Add BMC ready LED output to Talos BMC device treeRaptor Engineering Development Team2018-05-191-0/+4
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* Put Talos system fans into PWM mode by defaultRaptor Engineering Development Team2018-05-191-6/+6
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* Update Talos device tree to match production hardwareRaptor Engineering Development Team2018-05-191-28/+5
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* Put fans in RPM mode at startup on Talos systemsRaptor Engineering Development Team2018-05-191-0/+6
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* Enable PWM7 for use with on-board piezo speakerRaptor Engineering Development Team2018-05-191-1/+1
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* Enable MAX31785 fan controllerRaptor Engineering Development Team2018-05-191-2/+87
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* Add Raptor Computing Systems Talos BMC setup and device tree filesRaptor Engineering Development Team2018-05-192-0/+302
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* ipmi: NPCM7xx KCS BMC: enable interrupt to the hostAvi Fishman2018-05-181-4/+16
| | | | | | | | | | | Original kcs_bmc_npcm7xx.c was missing enabling to send interrupt to the host on writes to output buffer. This patch fixes it by setting the bits that enables the generation of IRQn events by hardware control based on the status of the OBF flag. OpenBMC-Staging-Count: 1 Signed-off-by: Avi Fishman <AviFishman70@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ipmi: kcs_bmc: coding-style fixesHaiyue Wang2018-05-184-36/+43
| | | | | | | | | | | OpenBMC-Staging-Count: 1 Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> [This is is not the same commit as upstream, as the changes to use new type '__poll_t' from linux-4.16-rc1 are not included. This was done because the feature is not a small self contained backport. There is no impact on functionality for dev-4.13] Signed-off-by: Joel Stanley <joel@jms.id.au>
* ipmi: add an NPCM7xx KCS BMC driverHaiyue Wang2018-05-184-0/+259
| | | | | | | | | | | | | | This driver exposes the Keyboard Controller Style (KCS) interface on Novoton NPCM7xx SoCs as a character device. Such SOCs are commonly used as a BaseBoard Management Controller (BMC) on a server board, and KCS interface is commonly used to perform the in-band IPMI communication between the server and its BMC. OpenBMC-Staging-Count: 1 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ipmi: add an Aspeed KCS IPMI BMC driverHaiyue Wang2018-05-184-0/+357
| | | | | | | | | | | | | | | The KCS (Keyboard Controller Style) interface is used to perform in-band IPMI communication between a server host and its BMC (BaseBoard Management Controllers). This driver exposes the KCS interface on ASpeed SOCs (AST2400 and AST2500) as a character device. Such SOCs are commonly used as BMCs and this driver implements the BMC side of the KCS interface. OpenBMC-Staging-Count: 1 Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ipmi: add a KCS IPMI BMC driverHaiyue Wang2018-05-185-0/+588
| | | | | | | | | | | | | Provides a device driver for the KCS (Keyboard Controller Style) IPMI interface which meets the requirement of the BMC (Baseboard Management Controllers) side for handling the IPMI request from host system software. Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> [Removed the selectability of IPMI_KCS_BMC, as it doesn't do much good to have it by itself.] Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* clk: npcm7xx: fix return value check in npcm7xx_clk_init()Wei Yongjun2018-05-181-1/+1
| | | | | | | | | | | | In case of error, the function ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. OpenBMC-Staging-Count: 1 Fixes: fcfd14369856 ("clk: npcm7xx: add clock controller") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
* pinctrl: npcm: add NPCM7xx pin control driverTomer Maimon2018-05-185-0/+2149
| | | | | | | | | | | | | | | | | Add Nuvoton BMC NPCM7xx pin controller driver. The NPCM7XX Pin Controller multi-function routed through the multiplexing block, Each pin supports GPIO functionality (GPIOx) and multiple functions that directly connect the pin to different hardware blocks. OpenBMC-Staging-Count: 1 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [Joel: - changed depend to select for MFD_SYSCON to fix kconfig warn - Fixed unintialised variable warning in npcm_set_drive_strength] Signed-off-by: Joel Stanley <joel@jms.id.au>
* dt-binding: pinctrl: document NPCM7xx pin controller DT bindingsTomer Maimon2018-05-181-0/+70
| | | | | | | | | Added device tree binding documentation for Nuvoton NPCM7xx pin controller OpenBMC-Staging-Count: 1 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Use 24MHz fixed clock for pwmLei YU2018-05-182-2/+2
| | | | | | | | | | The aspeed pwm driver always sets the clock source to 24MHz, specify the fixed clock in device tree to make sure the driver is using the correct clock frequency to calculate the fan speed. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* clk: aspeed: Add 24MHz fixed clockLei YU2018-05-182-1/+8
| | | | | | | | | Add a 24MHz fixed clock that is provided by the input oscillator. This clock will be used for certain devices, e.g. pwm. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* hwmon: (pmbus) Use 64bit math for DIRECT format valuesRobert Lippert2018-05-171-9/+12
| | | | | | | | | | | | | | Power values in the 100s of watt range can easily blow past 32bit math limits when processing everything in microwatts. Use 64bit math instead to avoid these issues on common 32bit ARM BMC platforms. Fixes: 442aba78728e ("hwmon: PMBus device driver") Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit bd467e4eababe4c04272c1e646f066db02734c79) Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi/fsi-master-gpio: Delay sampling of FSI data inputBenjamin Herrenschmidt2018-05-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Most SoC GPIO implementations, including the Aspeed one, have synchronizers on the GPIO inputs. This means that the value read from a GPIO is a couple of clocks old, from whatever clock source feeds those synchronizers. In practice, this means that in no-delay mode, we are using a value that can potentially be a bit too old and too close to the clock edge establishing the data on the other side of the link. The voltage converters we use on some systems make this worse and sensitive to things like voltage fluctuations etc... This is, we believe, the cause of occasional CRC errors encountered during heavy activity on the LPC bus. This is fixed by introducing a dummy GPIO read before the actual data read. It slows down SBEFIFO by about 15% (less than any delay primitive) and the end result is so far solid. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi/fsi-master-gpio: Reduce dpoll clocksBenjamin Herrenschmidt2018-05-111-2/+3
| | | | | | | | | | | | | | | | | FSI_GPIO_DPOLL_CLOCKS is the number of clocks before sending a DPOLL command after receiving a BUSY status. It should be at least tSendDelay (16 clocks). According to comments in the code, it needs to also be at least 21 clocks due to HW issues. It's currently 100 clocks which impacts performances negatively in some cases. Reduces it in half to 50 clocks which seems to still be solid. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi/fsi-master-gpio: Reduce turnaround clocksBenjamin Herrenschmidt2018-05-111-1/+1
| | | | | | | | | | | | | | | | | FSI_GPIO_PRIME_SLAVE_CLOCKS is the number of clocks if the "idle" phase between the end of a response and the beginning of the next one. It corresponds to tSendDelay in the FSI specification. The default value in the slave is 16 clocks. 100 is way overkill and significantly reduces the driver performance. This changes it to 20 (which gives the HW a bit of margin still just in case). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi/fsi-master-gpio: Add "no-gpio-delays" optionBenjamin Herrenschmidt2018-05-114-4/+19
| | | | | | | | | | | | | | | | | This adds support for an optional device-tree property that makes the driver skip all the delays around clocking the GPIOs and set it in the device-tree of common POWER9 based OpenPower platforms. This useful on chips like the AST2500 where the GPIO block is running at a fairly low clock frequency (25Mhz typically). In this case, the delays are unnecessary and due to the low precision of the timers, actually quite harmful in terms of performance. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi/fsi-master-gpio: Sample input data on different clock phaseBenjamin Herrenschmidt2018-05-111-3/+5
| | | | | | | | | | | | | | We currently sample the input data right after we toggle the clock low, then high. The slave establishes the data on the rising edge, so this is not ideal. We should sample it on the low phase instead. This currently works because we have an extra delay, but subsequent patches will remove it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* gpio/aspeed: Use a cache of output data registersBenjamin Herrenschmidt2018-05-111-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | The current driver does a read/modify/write of the output registers when changing a bit in __aspeed_gpio_set(). This is sub-optimal for a couple of reasons: - If any of the neighbouring GPIOs (sharing the shared register) isn't (yet) configured as an output, it will read the current input value, and then apply it to the output latch, which may not be what the user expects. There should be no bug in practice as aspeed_gpio_dir_out() will establish a new value but it's not great either. - The GPIO block in the aspeed chip is clocked rather slowly (typically 25Mhz). That extra MMIO read halves the maximum speed at which we can toggle the GPIO. This provides a significant performance improvement to the GPIO based FSI master. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* gpio/aspeed: Set output latch before changing directionBenjamin Herrenschmidt2018-05-111-2/+1
| | | | | | | | | | | | In aspeed_gpio_dir_out(), we need to establish the new output value in the output latch *before* we change the direction to output in order to avoid a glitch on the output line if the previous value of the latch was different. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Clean up sio registersJoel Stanley2018-05-111-19/+18
| | | | | | | | Remove the unnecessary reg property. Drop the 'rx' in the name, as this refers to a quirk in the datasheet and is not useful. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: configs: aspeed: Add watchdog sysfsEddie James2018-05-072-0/+2
| | | | | | | | | | | This kernel config adds sysfs entries for watchdog devices. This is needed in order to access the bootstatus sysfs file that will indicate whether or not the BMC has tripped the watchdog and subsequently switched sides. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi: occ: Add check for OCC response checksumEddie James2018-05-071-2/+24
| | | | | | | | | | | | The OCC specification indicates that it is an error scenario if the response checksum doesn't match the sum of the bytes of the response. The driver needs to perform this calculation and check, and return an error if it's a mismatch. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Move random number deviceJoel Stanley2018-05-072-12/+12
| | | | | | | | | | Move the node out from under the syscon/simple-mfd. Being a child of this node causes the driver to fail to probe, as platform_get_resource returns NULL due to dev->num_resources being zero. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi: occ: Use PutOCCSRAM in circular mode for OCC attentionAndrew Jeffery2018-05-011-13/+9
| | | | | | | | | | | | | | | | | | | | | We can't do SCOMs from the BMC when the host is booted in secure mode, and without triggering the attention of the OCC our commands won't be processed. Further, the SCOM operation fails, which causes the OCC driver's probe to fail, which leads the BMC to think that the OCC has failed. We have an alternative to the SCOM though: We can trigger the OCC by writing the correct attention magic in circular buffer mode. The PutOCCSRAM operation returns the written data length in the response payload before the 0xCODE word, so the condition testing the success of the operation is rearranged. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Matt Spinler mspinler@linux.vnet.ibm.com Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: romulus: Enable the GFX IPJoel Stanley2018-05-011-0/+12
| | | | | | | | | | | The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and enables the GFX node. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add Inventec Lanyang BMCBrian Yang2018-04-262-0/+332
| | | | | | | | | The Inventec Lanyang is Power 9 platform with ast2500 BMC. Tested-by: Brian Yang <yang.brianc.w@inventec.com> Signed-off-by: Brian Yang <yang.brianc.w@inventec.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add Portwell Neptune machineAmithash Prasad2018-04-263-1/+162
| | | | | | | | | | | | Initial introduction of Portwell Neptune family equipped with Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a ASPEED ast2500 BMC manufactured by Portwell. Specifically, This adds the neptune platform device tree file including the flash layout used by the neptune machines. Signed-off-by: Amithash Prasad <amithash@fb.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* clk: aspeed: Fix reset assert logicJae Hyun Yoo2018-04-261-1/+1
| | | | | | | | | | This commit fixes a bug in aspeed_reset_assert() which determines the second reset register using condition. OpenBMC-Staging-Count: 1 Fixes: 9e3efb97c78f ("clk: aspeed: Support second reset register") Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Add DAC MUX userspace controlJoel Stanley2018-04-201-2/+6
| | | | | | | | | | | | | | | | | This exposes SCU2C "Misc. Control Register" bits 16 and 17 which control the input to the VGA DAC. They are used to select which graphics device drives the analog output: 00: VGA mode (default) 01: Graphics CRT mode 10: Pass-through mode from Video input port-A 11: Pass-through mode from Video input port-B We don't need the reg property, so remove it and the unit name. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: witherspoon: Enable the GFX IPJoel Stanley2018-04-201-0/+8
| | | | | | | | | | | | The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: ast2500-evb: Enable the GFX IPJoel Stanley2018-04-201-1/+20
| | | | | | | | | | | | The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Add resets and clocks to GFX nodeJoel Stanley2018-04-201-0/+4
| | | | | | | | | | The ast2500 has a reset for the CRT device that must be deasserted before it can be used. Similarly it has a clock gate for a clock called D1CLK that must be set to running. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* drm: aspeed: Debugfs interface for GFX registersJoel Stanley2018-04-204-0/+83
| | | | | | | | This exposes the GFX registers in debugfs for debugging. The idea is borrowed from the Broadcom driver. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
* drm: Add ASPEED GFX driverJoel Stanley2018-04-208-0/+681
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is for the ASPEED BMC SoC's GFX display hardware. This driver runs on the ARM based BMC systems, unlike the ast driver which runs on a host CPU and is is for a PCI graphics device. The AST2500 supports a total of 3 output paths: 1. VGA output, the output target can choose either or both to the DAC or DVO interface. 2. Graphics CRT output, the output target can choose either or both to the DAC or DVO interface. 3. Video input from DVO, the video input can be used for video engine capture or DAC display output. Output options are selected in SCU2C. The "VGA mode" device is the PCI attached controller. The "Graphics CRT" is the ARM's internal display controller. The driver only supports a simple configuration consisting of a 40MHz pixel clock, fixed by hardware limitations, and the VGA output path. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
* drm/simple_kms_helper: Add {enable|disable}_vblank callback supportOleksandr Andrushchenko2018-04-192-0/+42
| | | | | | | | | | | | | | | | | If simple_kms_helper based driver needs to work with vblanks, then it has to provide drm_driver.{enable|disable}_vblank callbacks, because drm_simple_kms_helper.drm_crtc_funcs does not provide any. At the same time drm_driver.{enable|disable}_vblank callbacks are marked as deprecated and shouldn't be used by new drivers. Fix this by extending drm_simple_kms_helper.drm_crtc_funcs to provide the missing callbacks. Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1518425574-32671-2-git-send-email-andr2000@gmail.com (cherry picked from commit ac86cba96e2a439883d452772013049f54df2042) Signed-off-by: Joel Stanley <joel@jms.id.au>
* drm: introduce drm_dev_{get/put} functionsAishwarya Pant2018-04-194-22/+41
| | | | | | | | | | | | | | | | | Reference counting functions in the kernel typically use get/put suffixes. For maintaining coding style consistency, introduce drm_dev_{get/put} functions. All callers of drm_dev_ref() API have been converted in this patch and hence it has been dropped while the drm_dev_unref() API with non-trivial number of users remains for compatibility. The semantic patch scripts/coccinelle/api/drm-get-put.cocci has been updated with the new helper for conversion of drm_dev_unref() to drm_dev_put() Signed-off-by: Aishwarya Pant <aishpant@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/6babda56134035a98220d5d37a4fd4048df214ce.1506413698.git.aishpant@gmail.com (cherry picked from commit 9a96f55034e41b4e002b767e9218d55f03bdff7d) Signed-off-by: Joel Stanley <joel@jms.id.au>
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