diff options
Diffstat (limited to 'arch')
216 files changed, 9562 insertions, 3599 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 8290b69da202..213c7850d5fb 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -453,7 +453,7 @@ config ALPHA_IRONGATE config GENERIC_HWEIGHT bool - default y if !ALPHA_EV6 && !ALPHA_EV67 + default y if !ALPHA_EV67 config ALPHA_AVANTI bool diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c index eeb8a6d4a399..a5de5f1da9f2 100644 --- a/arch/arm/mach-imx/irq.c +++ b/arch/arm/mach-imx/irq.c @@ -127,7 +127,7 @@ static void imx_gpio_ack_irq(unsigned int irq) { DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); - ISR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); + ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32); } static void diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index a0724f2b24ce..9f55f5ae1044 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -232,8 +232,6 @@ static void __init intcp_init_irq(void) for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { if (i == 11) i = 22; - if (i == IRQ_CP_CPPLDINT) - i++; if (i == 29) break; set_irq_chip(i, &pic_chip); @@ -259,8 +257,7 @@ static void __init intcp_init_irq(void) set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } - set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq); - pic_unmask_irq(IRQ_CP_CPPLDINT); + set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq); } /* diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 19b372df544a..44bcb8097c7a 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -371,6 +371,7 @@ static int spitz_ohci_init(struct device *dev) static struct pxaohci_platform_data spitz_ohci_platform_data = { .port_mode = PMM_NPS_MODE, .init = spitz_ohci_init, + .power_budget = 150, }; diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 9e02bc3712a0..af6d2775cf82 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -59,6 +59,14 @@ neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg if (irr & (IRR_ETHERNET | IRR_USAR)) { desc->chip->mask(irq); + /* + * Ack the interrupt now to prevent re-entering + * this neponset handler. Again, this is safe + * since we'll check the IRR register prior to + * leaving. + */ + desc->chip->ack(irq); + if (irr & IRR_ETHERNET) { d = irq_desc + IRQ_NEPONSET_SMC9196; desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs); diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 799697d32dec..cebd48a3dae4 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -112,10 +112,9 @@ void __init versatile_init_irq(void) { unsigned int i; - vic_init(VA_VIC_BASE, IRQ_VIC_START, ~(1 << 31)); + vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0); - set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); - enable_irq(IRQ_VICSOURCE31); + set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq); /* Do second interrupt controller */ writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); diff --git a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c index 3852d0a4c1b5..1a7bdcef1926 100644 --- a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c +++ b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c @@ -104,7 +104,7 @@ acpi_processor_set_performance ( { u16 port = 0; u8 bit_width = 0; - int ret = 0; + int ret; u32 value = 0; int i = 0; struct cpufreq_freqs cpufreq_freqs; @@ -195,7 +195,6 @@ acpi_processor_set_performance ( udelay(10); } } else { - i = 0; value = (u32) data->acpi_data.states[state].status; } @@ -444,14 +443,15 @@ static struct freq_attr* acpi_cpufreq_attr[] = { }; static struct cpufreq_driver acpi_cpufreq_driver = { - .verify = acpi_cpufreq_verify, - .target = acpi_cpufreq_target, - .init = acpi_cpufreq_cpu_init, - .exit = acpi_cpufreq_cpu_exit, - .resume = acpi_cpufreq_resume, - .name = "acpi-cpufreq", - .owner = THIS_MODULE, - .attr = acpi_cpufreq_attr, + .verify = acpi_cpufreq_verify, + .target = acpi_cpufreq_target, + .init = acpi_cpufreq_cpu_init, + .exit = acpi_cpufreq_cpu_exit, + .resume = acpi_cpufreq_resume, + .name = "acpi-cpufreq", + .owner = THIS_MODULE, + .attr = acpi_cpufreq_attr, + .flags = CPUFREQ_STICKY, }; diff --git a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c index f275e0d4aee5..0d49d73d1b71 100644 --- a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c +++ b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c @@ -1,5 +1,5 @@ /* - * (C) 2004 Sebastian Witt <se.witt@gmx.net> + * (C) 2004-2006 Sebastian Witt <se.witt@gmx.net> * * Licensed under the terms of the GNU GPL License version 2. * Based upon reverse engineered information @@ -90,7 +90,7 @@ static int nforce2_calc_pll(unsigned int fsb) /* Try to calculate multiplier and divider up to 4 times */ while (((mul == 0) || (div == 0)) && (tried <= 3)) { - for (xdiv = 1; xdiv <= 0x80; xdiv++) + for (xdiv = 2; xdiv <= 0x80; xdiv++) for (xmul = 1; xmul <= 0xfe; xmul++) if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) == fsb + tried) { @@ -117,8 +117,7 @@ static void nforce2_write_pll(int pll) int temp; /* Set the pll addr. to 0x00 */ - temp = 0x00; - pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp); + pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, 0); /* Now write the value in all 64 registers */ for (temp = 0; temp <= 0x3f; temp++) @@ -266,7 +265,7 @@ static int nforce2_target(struct cpufreq_policy *policy, if (freqs.old == freqs.new) return 0; - dprintk(KERN_INFO "cpufreq: Old CPU frequency %d kHz, new %d kHz\n", + dprintk("Old CPU frequency %d kHz, new %d kHz\n", freqs.old, freqs.new); cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); @@ -278,7 +277,7 @@ static int nforce2_target(struct cpufreq_policy *policy, printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n", target_fsb); else - dprintk(KERN_INFO "cpufreq: Changed FSB successfully to %d\n", + dprintk("Changed FSB successfully to %d\n", target_fsb); /* Enable IRQs */ diff --git a/arch/i386/kernel/cpu/cpufreq/longhaul.c b/arch/i386/kernel/cpu/cpufreq/longhaul.c index 8ef38544453c..146f607e9c44 100644 --- a/arch/i386/kernel/cpu/cpufreq/longhaul.c +++ b/arch/i386/kernel/cpu/cpufreq/longhaul.c @@ -77,13 +77,17 @@ static char speedbuffer[8]; static char *print_speed(int speed) { - if (speed > 1000) { - if (speed%1000 == 0) - sprintf (speedbuffer, "%dGHz", speed/1000); - else - sprintf (speedbuffer, "%d.%dGHz", speed/1000, (speed%1000)/100); - } else - sprintf (speedbuffer, "%dMHz", speed); + if (speed < 1000) { + snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed); + return speedbuffer; + } + + if (speed%1000 == 0) + snprintf(speedbuffer, sizeof(speedbuffer), + "%dGHz", speed/1000); + else + snprintf(speedbuffer, sizeof(speedbuffer), + "%d.%dGHz", speed/1000, (speed%1000)/100); return speedbuffer; } @@ -675,7 +679,7 @@ static int __init longhaul_init(void) static void __exit longhaul_exit(void) { - int i=0; + int i; for (i=0; i < numscales; i++) { if (clock_ratio[i] == maxmult) { diff --git a/arch/i386/kernel/cpu/cpufreq/longrun.c b/arch/i386/kernel/cpu/cpufreq/longrun.c index e3868de4dc2e..b2689514295a 100644 --- a/arch/i386/kernel/cpu/cpufreq/longrun.c +++ b/arch/i386/kernel/cpu/cpufreq/longrun.c @@ -223,7 +223,6 @@ static unsigned int __init longrun_determine_freqs(unsigned int *low_freq, /* set to 0 to try_hi perf_pctg */ msr_lo &= 0xFFFFFF80; msr_hi &= 0xFFFFFF80; - msr_lo |= 0; msr_hi |= try_hi; wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k7.c b/arch/i386/kernel/cpu/cpufreq/powernow-k7.c index 2bf4237cb94e..694d4793bf6a 100644 --- a/arch/i386/kernel/cpu/cpufreq/powernow-k7.c +++ b/arch/i386/kernel/cpu/cpufreq/powernow-k7.c @@ -452,23 +452,23 @@ static int powernow_decode_bios (int maxfid, int startvid) pst = (struct pst_s *) p; - for (i = 0 ; i <psb->numpst; i++) { + for (j=0; j<psb->numpst; j++) { pst = (struct pst_s *) p; number_scales = pst->numpstates; if ((etuple == pst->cpuid) && check_fsb(pst->fsbspeed) && (maxfid==pst->maxfid) && (startvid==pst->startvid)) { - dprintk ("PST:%d (@%p)\n", i, pst); + dprintk ("PST:%d (@%p)\n", j, pst); dprintk (" cpuid: 0x%x fsb: %d maxFID: 0x%x startvid: 0x%x\n", pst->cpuid, pst->fsbspeed, pst->maxfid, pst->startvid); ret = get_ranges ((char *) pst + sizeof (struct pst_s)); return ret; - } else { + unsigned int k; p = (char *) pst + sizeof (struct pst_s); - for (j=0 ; j < number_scales; j++) + for (k=0; k<number_scales; k++) p+=2; } } @@ -581,10 +581,7 @@ static int __init powernow_cpu_init (struct cpufreq_policy *policy) rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val); - /* recalibrate cpu_khz */ - result = recalibrate_cpu_khz(); - if (result) - return result; + recalibrate_cpu_khz(); fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.CFID]; if (!fsb) { diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c index 71fffa174425..b4277f58f40c 100644 --- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c @@ -1,5 +1,5 @@ /* - * (c) 2003, 2004, 2005 Advanced Micro Devices, Inc. + * (c) 2003-2006 Advanced Micro Devices, Inc. * Your use of this code is subject to the terms and conditions of the * GNU general public license version 2. See "COPYING" or * http://www.gnu.org/licenses/gpl.html @@ -14,13 +14,13 @@ * Based upon datasheets & sample CPUs kindly provided by AMD. * * Valuable input gratefully received from Dave Jones, Pavel Machek, - * Dominik Brodowski, and others. + * Dominik Brodowski, Jacob Shin, and others. * Originally developed by Paul Devriendt. * Processor information obtained from Chapter 9 (Power and Thermal Management) * of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD * Opteron Processors" available for download from www.amd.com * - * Tables for specific CPUs can be infrerred from + * Tables for specific CPUs can be inferred from * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf */ @@ -46,7 +46,7 @@ #define PFX "powernow-k8: " #define BFX PFX "BIOS error: " -#define VERSION "version 1.60.2" +#define VERSION "version 2.00.00" #include "powernow-k8.h" /* serialize freq changes */ @@ -54,6 +54,8 @@ static DEFINE_MUTEX(fidvid_mutex); static struct powernow_k8_data *powernow_data[NR_CPUS]; +static int cpu_family = CPU_OPTERON; + #ifndef CONFIG_SMP static cpumask_t cpu_core_map[1]; #endif @@ -64,16 +66,36 @@ static u32 find_freq_from_fid(u32 fid) return 800 + (fid * 100); } + /* Return a frequency in KHz, given an input fid */ static u32 find_khz_freq_from_fid(u32 fid) { return 1000 * find_freq_from_fid(fid); } -/* Return a voltage in miliVolts, given an input vid */ -static u32 find_millivolts_from_vid(struct powernow_k8_data *data, u32 vid) +/* Return a frequency in MHz, given an input fid and did */ +static u32 find_freq_from_fiddid(u32 fid, u32 did) +{ + return 100 * (fid + 0x10) >> did; +} + +static u32 find_khz_freq_from_fiddid(u32 fid, u32 did) { - return 1550-vid*25; + return 1000 * find_freq_from_fiddid(fid, did); +} + +static u32 find_fid_from_pstate(u32 pstate) +{ + u32 hi, lo; + rdmsr(MSR_PSTATE_DEF_BASE + pstate, lo, hi); + return lo & HW_PSTATE_FID_MASK; +} + +static u32 find_did_from_pstate(u32 pstate) +{ + u32 hi, lo; + rdmsr(MSR_PSTATE_DEF_BASE + pstate, lo, hi); + return (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT; } /* Return the vco fid for an input fid @@ -98,6 +120,9 @@ static int pending_bit_stuck(void) { u32 lo, hi; + if (cpu_family) + return 0; + rdmsr(MSR_FIDVID_STATUS, lo, hi); return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0; } @@ -111,6 +136,14 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data) u32 lo, hi; u32 i = 0; + if (cpu_family) { + rdmsr(MSR_PSTATE_STATUS, lo, hi); + i = lo & HW_PSTATE_MASK; + rdmsr(MSR_PSTATE_DEF_BASE + i, lo, hi); + data->currfid = lo & HW_PSTATE_FID_MASK; + data->currdid = (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT; + return 0; + } do { if (i++ > 10000) { dprintk("detected change pending stuck\n"); @@ -175,7 +208,7 @@ static int write_new_fid(struct powernow_k8_data *data, u32 fid) do { wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION); if (i++ > 100) { - printk(KERN_ERR PFX "internal error - pending bit very stuck - no further pstate changes possible\n"); + printk(KERN_ERR PFX "Hardware error - pending bit very stuck - no further pstate changes possible\n"); return 1; } } while (query_current_values_with_pending_wait(data)); @@ -255,7 +288,15 @@ static int decrease_vid_code_by_step(struct powernow_k8_data *data, u32 reqvid, return 0; } -/* Change the fid and vid, by the 3 phases. */ +/* Change hardware pstate by single MSR write */ +static int transition_pstate(struct powernow_k8_data *data, u32 pstate) +{ + wrmsr(MSR_PSTATE_CTRL, pstate, 0); + data->currfid = find_fid_from_pstate(pstate); + return 0; +} + +/* Change Opteron/Athlon64 fid and vid, by the 3 phases. */ static int transition_fid_vid(struct powernow_k8_data *data, u32 reqfid, u32 reqvid) { if (core_voltage_pre_transition(data, reqvid)) @@ -474,26 +515,35 @@ static int check_supported_cpu(unsigned int cpu) goto out; eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); - if ((eax & CPUID_XFAM) != CPUID_XFAM_K8) + if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) && + ((eax & CPUID_XFAM) < CPUID_XFAM_10H)) goto out; - if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || - ((eax & CPUID_XMOD) > CPUID_XMOD_REV_G)) { - printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax); - goto out; - } + if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) { + if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || + ((eax & CPUID_XMOD) > CPUID_XMOD_REV_G)) { + printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax); + goto out; + } - eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); - if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { - printk(KERN_INFO PFX - "No frequency change capabilities detected\n"); - goto out; - } + eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); + if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { + printk(KERN_INFO PFX + "No frequency change capabilities detected\n"); + goto out; + } - cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); - if ((edx & P_STATE_TRANSITION_CAPABLE) != P_STATE_TRANSITION_CAPABLE) { - printk(KERN_INFO PFX "Power state transitions not supported\n"); - goto out; + cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); + if ((edx & P_STATE_TRANSITION_CAPABLE) != P_STATE_TRANSITION_CAPABLE) { + printk(KERN_INFO PFX "Power state transitions not supported\n"); + goto out; + } + } else { /* must be a HW Pstate capable processor */ + cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); + if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE) + cpu_family = CPU_HW_PSTATE; + else + goto out; } rc = 1; @@ -547,12 +597,18 @@ static void print_basics(struct powernow_k8_data *data) { int j; for (j = 0; j < data->numps; j++) { - if (data->powernow_table[j].frequency != CPUFREQ_ENTRY_INVALID) - printk(KERN_INFO PFX " %d : fid 0x%x (%d MHz), vid 0x%x (%d mV)\n", j, + if (data->powernow_table[j].frequency != CPUFREQ_ENTRY_INVALID) { + if (cpu_family) { + printk(KERN_INFO PFX " %d : fid 0x%x gid 0x%x (%d MHz)\n", j, (data->powernow_table[j].index & 0xff00) >> 8, + (data->powernow_table[j].index & 0xff0000) >> 16, + data->powernow_table[j].frequency/1000); + } else { + printk(KERN_INFO PFX " %d : fid 0x%x (%d MHz), vid 0x%x\n", j, data->powernow_table[j].index & 0xff, data->powernow_table[j].frequency/1000, - data->powernow_table[j].index >> 8, - find_millivolts_from_vid(data, data->powernow_table[j].index >> 8)); + data->powernow_table[j].index >> 8); + } + } } if (data->batps) printk(KERN_INFO PFX "Only %d pstates on battery\n", data->batps); @@ -702,7 +758,7 @@ static int find_psb_table(struct powernow_k8_data *data) #ifdef CONFIG_X86_POWERNOW_K8_ACPI static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) { - if (!data->acpi_data.state_count) + if (!data->acpi_data.state_count || cpu_family) return; data->irt = (data->acpi_data.states[index].control >> IRT_SHIFT) & IRT_MASK; @@ -715,9 +771,8 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) { - int i; - int cntlofreq = 0; struct cpufreq_frequency_table *powernow_table; + int ret_val; if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) { dprintk("register performance failed: bad ACPI data\n"); @@ -746,6 +801,85 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) goto err_out; } + if (cpu_family) + ret_val = fill_powernow_table_pstate(data, powernow_table); + else + ret_val = fill_powernow_table_fidvid(data, powernow_table); + if (ret_val) + goto err_out_mem; + + powernow_table[data->acpi_data.state_count].frequency = CPUFREQ_TABLE_END; + powernow_table[data->acpi_data.state_count].index = 0; + data->powernow_table = powernow_table; + + /* fill in data */ + data->numps = data->acpi_data.state_count; + print_basics(data); + powernow_k8_acpi_pst_values(data, 0); + + /* notify BIOS that we exist */ + acpi_processor_notify_smm(THIS_MODULE); + + return 0; + +err_out_mem: + kfree(powernow_table); + +err_out: + acpi_processor_unregister_performance(&data->acpi_data, data->cpu); + + /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */ + data->acpi_data.state_count = 0; + + return -ENODEV; +} + +static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table) +{ + int i; + + for (i = 0; i < data->acpi_data.state_count; i++) { + u32 index; + u32 hi = 0, lo = 0; + u32 fid; + u32 did; + + index = data->acpi_data.states[i].control & HW_PSTATE_MASK; + if (index > MAX_HW_PSTATE) { + printk(KERN_ERR PFX "invalid pstate %d - bad value %d.\n", i, index); + printk(KERN_ERR PFX "Please report to BIOS manufacturer\n"); + } + rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); + if (!(hi & HW_PSTATE_VALID_MASK)) { + dprintk("invalid pstate %d, ignoring\n", index); + powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID; + continue; + } + + fid = lo & HW_PSTATE_FID_MASK; + did = (lo & HW_PSTATE_DID_MASK) >> HW_PSTATE_DID_SHIFT; + + dprintk(" %d : fid 0x%x, did 0x%x\n", index, fid, did); + + powernow_table[i].index = index | (fid << HW_FID_INDEX_SHIFT) | (did << HW_DID_INDEX_SHIFT); + + powernow_table[i].frequency = find_khz_freq_from_fiddid(fid, did); + + if (powernow_table[i].frequency != (data->acpi_data.states[i].core_frequency * 1000)) { + printk(KERN_INFO PFX "invalid freq entries %u kHz vs. %u kHz\n", + powernow_table[i].frequency, + (unsigned int) (data->acpi_data.states[i].core_frequency * 1000)); + powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID; + continue; + } + } + return 0; +} + +static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table) +{ + int i; + int cntlofreq = 0; for (i = 0; i < data->acpi_data.state_count; i++) { u32 fid; u32 vid; @@ -786,7 +920,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) || (powernow_table[i].index != powernow_table[cntlofreq].index)) { printk(KERN_ERR PFX "Too many lo freq table entries\n"); - goto err_out_mem; + return 1; } dprintk("double low frequency table entry, ignoring it.\n"); @@ -804,31 +938,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) continue; } } - - powernow_table[data->acpi_data.state_count].frequency = CPUFREQ_TABLE_END; - powernow_table[data->acpi_data.state_count].index = 0; - data->powernow_table = powernow_table; - - /* fill in data */ - data->numps = data->acpi_data.state_count; - print_basics(data); - powernow_k8_acpi_pst_values(data, 0); - - /* notify BIOS that we exist */ - acpi_processor_notify_smm(THIS_MODULE); - return 0; - -err_out_mem: - kfree(powernow_table); - -err_out: - acpi_processor_unregister_performance(&data->acpi_data, data->cpu); - - /* data->acpi_data.state_count informs us at ->exit() whether ACPI was used */ - data->acpi_data.state_count = 0; - - return -ENODEV; } static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) @@ -844,20 +954,20 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned #endif /* CONFIG_X86_POWERNOW_K8_ACPI */ /* Take a frequency, and issue the fid/vid transition command */ -static int transition_frequency(struct powernow_k8_data *data, unsigned int index) +static int transition_frequency_fidvid(struct powernow_k8_data *data, unsigned int index) { - u32 fid; - u32 vid; + u32 fid = 0; + u32 vid = 0; int res, i; struct cpufreq_freqs freqs; dprintk("cpu %d transition to index %u\n", smp_processor_id(), index); + /* fid/vid correctness check for k8 */ /* fid are the lower 8 bits of the index we stored into - * the cpufreq frequency table in find_psb_table, vid are - * the upper 8 bits. + * the cpufreq frequency table in find_psb_table, vid + * are the upper 8 bits. */ - fid = data->powernow_table[index].index & 0xFF; vid = (data->powernow_table[index].index & 0xFF00) >> 8; @@ -881,22 +991,58 @@ static int transition_frequency(struct powernow_k8_data *data, unsigned int inde dprintk("cpu %d, changing to fid 0x%x, vid 0x%x\n", smp_processor_id(), fid, vid); - - freqs.cpu = data->cpu; freqs.old = find_khz_freq_from_fid(data->currfid); freqs.new = find_khz_freq_from_fid(fid); - for_each_cpu_mask(i, cpu_core_map[data->cpu]) { + + for_each_cpu_mask(i, *(data->available_cores)) { freqs.cpu = i; cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); } res = transition_fid_vid(data, fid, vid); - freqs.new = find_khz_freq_from_fid(data->currfid); - for_each_cpu_mask(i, cpu_core_map[data->cpu]) { + + for_each_cpu_mask(i, *(data->available_cores)) { freqs.cpu = i; cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - } + } + return res; +} + +/* Take a frequency, and issue the hardware pstate transition command */ +static int transition_frequency_pstate(struct powernow_k8_data *data, unsigned int index) +{ + u32 fid = 0; + u32 did = 0; + u32 pstate = 0; + int res, i; + struct cpufreq_freqs freqs; + + dprintk("cpu %d transition to index %u\n", smp_processor_id(), index); + + /* get fid did for hardware pstate transition */ + pstate = index & HW_PSTATE_MASK; + if (pstate > MAX_HW_PSTATE) + return 0; + fid = (index & HW_FID_INDEX_MASK) >> HW_FID_INDEX_SHIFT; + did = (index & HW_DID_INDEX_MASK) >> HW_DID_INDEX_SHIFT; + freqs.old = find_khz_freq_from_fiddid(data->currfid, data->currdid); + freqs.new = find_khz_freq_from_fiddid(fid, did); + + for_each_cpu_mask(i, *(data->available_cores)) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + } + + res = transition_pstate(data, pstate); + data->currfid = find_fid_from_pstate(pstate); + data->currdid = find_did_from_pstate(pstate); + freqs.new = find_khz_freq_from_fiddid(data->currfid, data->currdid); + + for_each_cpu_mask(i, *(data->available_cores)) { + freqs.cpu = i; + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } return res; } @@ -933,18 +1079,21 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi dprintk("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n", pol->cpu, targfreq, pol->min, pol->max, relation); - if (query_current_values_with_pending_wait(data)) { - ret = -EIO; + if (query_current_values_with_pending_wait(data)) goto err_out; - } - dprintk("targ: curr fid 0x%x, vid 0x%x\n", + if (cpu_family) + dprintk("targ: curr fid 0x%x, did 0x%x\n", + data->currfid, data->currvid); + else { + dprintk("targ: curr fid 0x%x, vid 0x%x\n", data->currfid, data->currvid); - if ((checkvid != data->currvid) || (checkfid != data->currfid)) { - printk(KERN_INFO PFX - "error - out of sync, fix 0x%x 0x%x, vid 0x%x 0x%x\n", - checkfid, data->currfid, checkvid, data->currvid); + if ((checkvid != data->currvid) || (checkfid != data->currfid)) { + printk(KERN_INFO PFX + "error - out of sync, fix 0x%x 0x%x, vid 0x%x 0x%x\n", + checkfid, data->currfid, checkvid, data->currvid); + } } if (cpufreq_frequency_table_target(pol, data->powernow_table, targfreq, relation, &newstate)) @@ -954,7 +1103,11 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi powernow_k8_acpi_pst_values(data, newstate); - if (transition_frequency(data, newstate)) { + if (cpu_family) + ret = transition_frequency_pstate(data, newstate); + else + ret = transition_frequency_fidvid(data, newstate); + if (ret) { printk(KERN_ERR PFX "transition frequency failed\n"); ret = 1; mutex_unlock(&fidvid_mutex); @@ -962,7 +1115,10 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi } mutex_unlock(&fidvid_mutex); - pol->cur = find_khz_freq_from_fid(data->currfid); + if (cpu_family) + pol->cur = find_khz_freq_from_fiddid(data->currfid, data->currdid); + else + pol->cur = find_khz_freq_from_fid(data->currfid); ret = 0; err_out: @@ -1007,14 +1163,13 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) * Use the PSB BIOS structure. This is only availabe on * an UP version, and is deprecated by AMD. */ - if ((num_online_cpus() != 1) || (num_possible_cpus() != 1)) { printk(KERN_ERR PFX "MP systems not supported by PSB BIOS structure\n"); kfree(data); return -ENODEV; } if (pol->cpu != 0) { - printk(KERN_ERR PFX "init not cpu 0\n"); + printk(KERN_ERR PFX "No _PSS objects for CPU other than CPU0\n"); kfree(data); return -ENODEV; } @@ -1042,20 +1197,28 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) if (query_current_values_with_pending_wait(data)) goto err_out; - fidvid_msr_init(); + if (!cpu_family) + fidvid_msr_init(); /* run on any CPU again */ set_cpus_allowed(current, oldmask); pol->governor = CPUFREQ_DEFAULT_GOVERNOR; - pol->cpus = cpu_core_map[pol->cpu]; + if (cpu_family) + pol->cpus = cpumask_of_cpu(pol->cpu); + else + pol->cpus = cpu_core_map[pol->cpu]; + data->available_cores = &(pol->cpus); /* Take a crude guess here. * That guess was in microseconds, so multiply with 1000 */ pol->cpuinfo.transition_latency = (((data->rvo + 8) * data->vstable * VST_UNITS_20US) + (3 * (1 << data->irt) * 10)) * 1000; - pol->cur = find_khz_freq_from_fid(data->currfid); + if (cpu_family) + pol->cur = find_khz_freq_from_fiddid(data->currfid, data->currdid); + else + pol->cur = find_khz_freq_from_fid(data->currfid); dprintk("policy current frequency %d kHz\n", pol->cur); /* min/max the cpu is capable of */ @@ -1069,8 +1232,12 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu); - printk("cpu_init done, current fid 0x%x, vid 0x%x\n", - data->currfid, data->currvid); + if (cpu_family) + dprintk("cpu_init done, current fid 0x%x, did 0x%x\n", + data->currfid, data->currdid); + else + dprintk("cpu_init done, current fid 0x%x, vid 0x%x\n", + data->currfid, data->currvid); powernow_data[pol->cpu] = data; @@ -1156,8 +1323,9 @@ static int __cpuinit powernowk8_init(void) } if (supported_cpus == num_online_cpus()) { - printk(KERN_INFO PFX "Found %d AMD Athlon 64 / Opteron " - "processors (" VERSION ")\n", supported_cpus); + printk(KERN_INFO PFX "Found %d %s " + "processors (" VERSION ")\n", supported_cpus, + boot_cpu_data.x86_model_id); return cpufreq_register_driver(&cpufreq_amd64_driver); } diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h index 79a7c5c87edc..bf8ad9e43da3 100644 --- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h +++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h @@ -1,5 +1,5 @@ /* - * (c) 2003, 2004, 2005 Advanced Micro Devices, Inc. + * (c) 2003-2006 Advanced Micro Devices, Inc. * Your use of this code is subject to the terms and conditions of the * GNU general public license version 2. See "COPYING" or * http://www.gnu.org/licenses/gpl.html @@ -21,8 +21,8 @@ struct powernow_k8_data { u32 plllock; /* pll lock time, units 1 us */ u32 exttype; /* extended interface = 1 */ - /* keep track of the current fid / vid */ - u32 currvid, currfid; + /* keep track of the current fid / vid or did */ + u32 currvid, currfid, currdid; /* the powernow_table includes all frequency and vid/fid pairings: * fid are the lower 8 bits of the index, vid are the upper 8 bits. @@ -34,6 +34,10 @@ struct powernow_k8_data { * used to determine valid frequency/vid/fid states */ struct acpi_processor_performance acpi_data; #endif + /* we need to keep track of associated cores, but let cpufreq + * handle hotplug events - so just point at cpufreq pol->cpus + * structure */ + cpumask_t *available_cores; }; @@ -43,6 +47,7 @@ struct powernow_k8_data { #define CPUID_XFAM_K8 0 #define CPUID_XMOD 0x000f0000 /* extended model */ #define CPUID_XMOD_REV_G 0x00060000 +#define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ #define CPUID_USE_XFAM_XMOD 0x00000f00 #define CPUID_GET_MAX_CAPABILITIES 0x80000000 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 @@ -79,6 +84,32 @@ struct powernow_k8_data { #define MSR_S_HI_CURRENT_VID 0x0000003f #define MSR_C_HI_STP_GNT_BENIGN 0x00000001 + +/* Hardware Pstate _PSS and MSR definitions */ +#define USE_HW_PSTATE 0x00000080 +#define HW_PSTATE_FID_MASK 0x0000003f +#define HW_PSTATE_DID_MASK 0x000001c0 +#define HW_PSTATE_DID_SHIFT 6 +#define HW_PSTATE_MASK 0x00000007 +#define HW_PSTATE_VALID_MASK 0x80000000 +#define HW_FID_INDEX_SHIFT 8 +#define HW_FID_INDEX_MASK 0x0000ff00 +#define HW_DID_INDEX_SHIFT 16 +#define HW_DID_INDEX_MASK 0x00ff0000 +#define HW_WATTS_MASK 0xff +#define HW_PWR_DVR_MASK 0x300 +#define HW_PWR_DVR_SHIFT 8 +#define HW_PWR_MAX_MULT 3 +#define MAX_HW_PSTATE 8 /* hw pstate supports up to 8 */ +#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */ +#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */ +#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */ + +/* define the two driver architectures */ +#define CPU_OPTERON 0 +#define CPU_HW_PSTATE 1 + + /* * There are restrictions frequencies have to follow: * - only 1 entry in the low fid table ( <=1.4GHz ) @@ -182,6 +213,9 @@ static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); +static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); +static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); + #ifdef CONFIG_SMP static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) { diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c index b0ff9075708c..ce54ff12c15d 100644 --- a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c +++ b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c @@ -250,7 +250,7 @@ static int centrino_cpu_init_table(struct cpufreq_policy *policy) if (model->cpu_id == NULL) { /* No match at all */ - dprintk(KERN_INFO PFX "no support for CPU model \"%s\": " + dprintk("no support for CPU model \"%s\": " "send /proc/cpuinfo to " MAINTAINER "\n", cpu->x86_model_id); return -ENOENT; @@ -258,10 +258,10 @@ static int centrino_cpu_init_table(struct cpufreq_policy *policy) if (model->op_points == NULL) { /* Matched a non-match */ - dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n", + dprintk("no table support for CPU model \"%s\"\n", cpu->x86_model_id); #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI - dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n"); + dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n"); #endif return -ENOENT; } @@ -368,7 +368,7 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy) /* register with ACPI core */ if (acpi_processor_register_performance(&p, cpu)) { - dprintk(KERN_INFO PFX "obtaining ACPI data failed\n"); + dprintk("obtaining ACPI data failed\n"); return -EIO; } @@ -465,7 +465,7 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy) kfree(centrino_model[cpu]); err_unreg: acpi_processor_unregister_performance(&p, cpu); - dprintk(KERN_INFO PFX "invalid ACPI data\n"); + dprintk("invalid ACPI data\n"); return (result); } #else @@ -499,7 +499,7 @@ static int centrino_cpu_init(struct cpufreq_policy *policy) centrino_cpu[policy->cpu] = &cpu_ids[i]; if (!centrino_cpu[policy->cpu]) { - dprintk(KERN_INFO PFX "found unsupported CPU with " + dprintk("found unsupported CPU with " "Enhanced SpeedStep: send /proc/cpuinfo to " MAINTAINER "\n"); return -ENODEV; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e8ff09fe73d9..35e038a974c6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -119,6 +119,32 @@ config MIPS_MIRAGE select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_LITTLE_ENDIAN +config BASLER_EXCITE + bool "Basler eXcite smart camera support" + select DMA_COHERENT + select HW_HAS_PCI + select IRQ_CPU + select IRQ_CPU_RM7K + select IRQ_CPU_RM9K + select SERIAL_RM9000 + select SYS_HAS_CPU_RM9000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + The eXcite is a smart camera platform manufactured by + Basler Vision Technologies AG + +config BASLER_EXCITE_PROTOTYPE + bool "Support for pre-release units" + depends on BASLER_EXCITE + default n + help + Pre-series (prototype) units are different from later ones in + some ways. Select this option if you have one of these. Please + note that a kernel built with this option selected will not be + able to run on normal units. + config MIPS_COBALT bool "Cobalt Server" select DMA_NONCOHERENT @@ -142,6 +168,9 @@ config MACH_DECSTATION select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_128HZ + select SYS_SUPPORTS_256HZ + select SYS_SUPPORTS_1024HZ help This enables support for DEC's MIPS based workstations. For details see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the @@ -239,6 +268,7 @@ config MACH_JAZZ select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL + select SYS_SUPPORTS_100HZ help This a family of machines based on the MIPS R4030 chipset which was used by several vendors to build RISC/os and Windows NT workstations. @@ -327,6 +357,27 @@ config MIPS_SEAD This enables support for the MIPS Technologies SEAD evaluation board. +config WR_PPMC + bool "Support for Wind River PPMC board" + select IRQ_CPU + select BOOT_ELF32 + select DMA_NONCOHERENT + select HW_HAS_PCI + select MIPS_GT64120 + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R1 + select SYS_HAS_CPU_NEVADA + select SYS_HAS_CPU_RM7000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + help + This enables support for the Wind River MIPS32 4KC PPMC evaluation + board, which is based on GT64120 bridge chip. + config MIPS_SIM bool 'MIPS simulator (MIPSsim)' select DMA_NONCOHERENT @@ -438,53 +489,16 @@ config MIPS_XXS1500 config PNX8550_V2PCI bool "Philips PNX8550 based Viper2-PCI board" + depends on BROKEN select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN config PNX8550_JBS bool "Philips PNX8550 based JBS board" + depends on BROKEN select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN -config DDB5074 - bool "NEC DDB Vrc-5074 (EXPERIMENTAL)" - depends on EXPERIMENTAL - select DDB5XXX_COMMON - select DMA_NONCOHERENT - select HAVE_STD_PC_SERIAL_PORT - select HW_HAS_PCI - select IRQ_CPU - select I8259 - select ISA - select SYS_HAS_CPU_R5000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_LITTLE_ENDIAN - help - This enables support for the VR5000-based NEC DDB Vrc-5074 - evaluation board. - -config DDB5476 - bool "NEC DDB Vrc-5476" - select DDB5XXX_COMMON - select DMA_NONCOHERENT - select HAVE_STD_PC_SERIAL_PORT - select HW_HAS_PCI - select IRQ_CPU - select I8259 - select ISA - select SYS_HAS_CPU_R5432 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_LITTLE_ENDIAN - help - This enables support for the R5432-based NEC DDB Vrc-5476 - evaluation board. - - Features : kernel debugging, serial terminal, NFS root fs, on-board - ether port USB, AC97, PCI, PCI VGA card & framebuffer console, - IDE controller, PS2 keyboard, PS2 mouse, etc. - config DDB5477 bool "NEC DDB Vrc-5477" select DDB5XXX_COMMON @@ -546,6 +560,20 @@ config QEMU simulate actual MIPS hardware platforms. More information on Qemu can be found at http://www.linux-mips.org/wiki/Qemu. +config MARKEINS + bool "Support for NEC EMMA2RH Mark-eins" + select DMA_NONCOHERENT + select HW_HAS_PCI + select IRQ_CPU + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_CPU_R5000 + help + This enables support for the R5432-based NEC Mark-eins + boards with R5500 CPU. + config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC @@ -555,6 +583,7 @@ config SGI_IP22 select HW_HAS_EISA select IP22_CPU_SCACHE select IRQ_CPU + select NO_ISA if ISA select SWAP_IO_SPACE select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 @@ -577,6 +606,7 @@ config SGI_IP27 select SYS_HAS_CPU_R10000 select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_NUMA help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y @@ -707,8 +737,8 @@ config SIBYTE_CRHONE config SNI_RM200_PCI bool "SNI RM200 PCI" - select ARC - select ARC32 + select ARC if CPU_LITTLE_ENDIAN + select ARC32 if CPU_LITTLE_ENDIAN select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select DMA_NONCOHERENT @@ -719,10 +749,13 @@ config SNI_RM200_PCI select I8253 select I8259 select ISA + select SWAP_IO_SPACE if CPU_BIG_ENDIAN select SYS_HAS_CPU_R4X00 + select SYS_HAS_CPU_R5000 + select R5000_CPU_SCACHE select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL + select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN help @@ -979,6 +1012,11 @@ config SOC_PNX8550 config SWAP_IO_SPACE bool +config EMMA2RH + bool + depends on MARKEINS + default y + # # Unfortunately not all GT64120 systems run the chip at the same clock. # As the user for the clock rate and try to minimize the available options. @@ -1607,6 +1645,28 @@ config ARCH_FLATMEM_ENABLE def_bool y depends on !NUMA +config ARCH_DISCONTIGMEM_ENABLE + bool + default y if SGI_IP27 + help + Say Y to upport efficient handling of discontiguous physical memory, + for architectures which are either NUMA (Non-Uniform Memory Access) + or have huge holes in the physical address space for other reasons. + See <file:Documentation/vm/numa> for more. + +config NUMA + bool "NUMA Support" + depends on SYS_SUPPORTS_NUMA + help + Say Y to compile the kernel to support NUMA (Non-Uniform Memory + Access). This option improves performance on systems with more + than two nodes; on two node systems it is generally better to + leave it disabled; on single node systems disable this option + disabled. + +config SYS_SUPPORTS_NUMA + bool + config NODES_SHIFT int default "6" @@ -1651,6 +1711,77 @@ config NR_CPUS This is purely to save memory - each supported CPU adds approximately eight kilobytes to the kernel image. +# +# Timer Interrupt Frequency Configuration +# + +choice + prompt "Timer frequency" + default HZ_250 + help + Allows the configuration of the timer frequency. + + config HZ_48 + bool "48 HZ" if SYS_SUPPORTS_48HZ + + config HZ_100 + bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ + + config HZ_128 + bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ + + config HZ_250 + bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ + + config HZ_256 + bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ + + config HZ_1000 + bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ + + config HZ_1024 + bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ + +endchoice + +config SYS_SUPPORTS_48HZ + bool + +config SYS_SUPPORTS_100HZ + bool + +config SYS_SUPPORTS_128HZ + bool + +config SYS_SUPPORTS_250HZ + bool + +config SYS_SUPPORTS_256HZ + bool + +config SYS_SUPPORTS_1000HZ + bool + +config SYS_SUPPORTS_1024HZ + bool + +config SYS_SUPPORTS_ARBIT_HZ + bool + default y if !SYS_SUPPORTS_48HZ && !SYS_SUPPORTS_100HZ && \ + !SYS_SUPPORTS_128HZ && !SYS_SUPPORTS_250HZ && \ + !SYS_SUPPORTS_256HZ && !SYS_SUPPORTS_1000HZ && \ + !SYS_SUPPORTS_1024HZ + +config HZ + int + default 48 if HZ_48 + default 100 if HZ_100 + default 128 if HZ_128 + default 250 if HZ_250 + default 256 if HZ_256 + default 1000 if HZ_1000 + default 1024 if HZ_1024 + source "kernel/Kconfig.preempt" config RTC_DS1742 @@ -1710,6 +1841,9 @@ source "drivers/pci/Kconfig" config ISA bool +config NO_ISA + bool + config EISA bool "EISA support" depends on HW_HAS_EISA @@ -1840,6 +1974,32 @@ config PM bool "Power Management support (EXPERIMENTAL)" depends on EXPERIMENTAL && SOC_AU1X00 +config APM + tristate "Advanced Power Management Emulation" + depends on PM + ---help--- + APM is a BIOS specification for saving power using several different + techniques. This is mostly useful for battery powered systems with + APM compliant BIOSes. If you say Y here, the system time will be + reset after a RESUME operation, the /proc/apm device will provide + battery status information, and user-space programs will receive + notification of APM "events" (e.g. battery status change). + + In order to use APM, you will need supporting software. For location + and more information, read <file:Documentation/pm.txt> and the + Battery Powered Linux mini-HOWTO, available from + <http://www.tldp.org/docs.html#howto>. + + This driver does not spin down disk drives (see the hdparm(8) + manpage ("man 8 hdparm") for that), and it doesn't turn off + VESA-compliant "green" monitors. + + Generally, if you don't have a battery in your machine, there isn't + much point in using this driver and you should say N. If you get + random kernel OOPSes or reboots that don't seem to be related to + anything, try disabling/enabling this option (or disabling/enabling + APM in your BIOS). + endmenu source "net/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 133900aca992..d5930148495a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -83,6 +83,8 @@ cflags-y += -msoft-float LDFLAGS_vmlinux += -G 0 -static -n -nostdlib MODFLAGS += -mlong-calls +cflags-y += -ffreestanding + # # We explicitly add the endianness specifier if needed, this allows # to compile kernels with a toolchain for the other endianness. We @@ -285,6 +287,13 @@ cflags-$(CONFIG_MIPS_EV96100) += -Iinclude/asm-mips/mach-ev96100 load-$(CONFIG_MIPS_EV96100) += 0xffffffff80100000 # +# Wind River PPMC Board (4KC + GT64120) +# +core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/ +cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc +load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 + +# # Globespan IVR eval board with QED 5231 CPU # core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/ @@ -379,6 +388,13 @@ cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3 load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 # +# Basler eXcite +# +core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ +cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite +load-$(CONFIG_BASLER_EXCITE) += 0x80100000 + +# # Momentum Jaguar ATX # core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ @@ -395,18 +411,6 @@ load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000 core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ # -# NEC DDB Vrc-5074 -# -core-$(CONFIG_DDB5074) += arch/mips/ddb5xxx/ddb5074/ -load-$(CONFIG_DDB5074) += 0xffffffff80080000 - -# -# NEC DDB Vrc-5476 -# -core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/ -load-$(CONFIG_DDB5476) += 0xffffffff80080000 - -# # NEC DDB Vrc-5477 # core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ @@ -468,6 +472,15 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/ #cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 +# NEC EMMA2RH boards +# +core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/ +cflags-$(CONFIG_EMMA2RH) += -Iinclude/asm-mips/mach-emma2rh + +# NEC EMMA2RH Mark-eins +core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/ +load-$(CONFIG_MARKEINS) += 0xffffffff88100000 + # # SGI IP22 (Indy/Indigo2) # diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c index 0b2c03c52319..5a1e3687cafa 100644 --- a/arch/mips/au1000/common/au1xxx_irqmap.c +++ b/arch/mips/au1000/common/au1xxx_irqmap.c @@ -55,7 +55,7 @@ * Careful if you change match 2 request! * The interrupt handler is called directly from the low level dispatch code. */ -au1xxx_irq_map_t au1xxx_ic0_map[] = { +au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = { #if defined(CONFIG_SOC_AU1000) { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, @@ -220,5 +220,5 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = { }; -int au1xxx_ic0_nr_irqs = sizeof(au1xxx_ic0_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map); diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index 4e5a6e1a9a6e..b1392abac809 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c @@ -40,17 +40,17 @@ /* TBD */ static struct resource pci_io_resource = { - "pci IO space", - (u32)PCI_IO_START, - (u32)PCI_IO_END, - IORESOURCE_IO + .start = PCI_IO_START, + .end = PCI_IO_END, + .name = "PCI IO space", + .flags = IORESOURCE_IO }; static struct resource pci_mem_resource = { - "pci memory space", - (u32)PCI_MEM_START, - (u32)PCI_MEM_END, - IORESOURCE_MEM + .start = PCI_MEM_START, + .end = PCI_MEM_END, + .name = "PCI memory space", + .flags = IORESOURCE_MEM }; extern struct pci_ops au1x_pci_ops; diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index 307e98c29ddc..97165b6b3894 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -49,17 +49,13 @@ extern void __init board_setup(void); extern void au1000_restart(char *); extern void au1000_halt(void); extern void au1000_power_off(void); -extern struct resource ioport_resource; -extern struct resource iomem_resource; -extern void (*board_time_init)(void); extern void au1x_time_init(void); -extern void (*board_timer_setup)(struct irqaction *irq); extern void au1x_timer_setup(struct irqaction *irq); extern void au1xxx_time_init(void); extern void au1xxx_timer_setup(struct irqaction *irq); extern void set_cpuspec(void); -void __init plat_setup(void) +void __init plat_mem_setup(void) { struct cpu_spec *sp; char *argptr; diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index f74d66a58a21..842e1b5ac4a1 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -50,10 +50,6 @@ #include <linux/mc146818rtc.h> #include <linux/timex.h> -extern void do_softirq(void); -extern volatile unsigned long wall_jiffies; -unsigned long missed_heart_beats = 0; - static unsigned long r4k_offset; /* Amount to increment compare reg each time */ static unsigned long r4k_cur; /* What counter should be at next timer irq */ int no_au1xxx_32khz; @@ -388,10 +384,9 @@ static unsigned long do_fast_pm_gettimeoffset(void) } #endif -void au1xxx_timer_setup(struct irqaction *irq) +void __init au1xxx_timer_setup(struct irqaction *irq) { - unsigned int est_freq; - extern unsigned long (*do_gettimeoffset)(void); + unsigned int est_freq; printk("calculating r4koff... "); r4k_offset = cal_r4koff(); diff --git a/arch/mips/au1000/csb250/irqmap.c b/arch/mips/au1000/csb250/irqmap.c index 5cb1166be35c..57d60401905e 100644 --- a/arch/mips/au1000/csb250/irqmap.c +++ b/arch/mips/au1000/csb250/irqmap.c @@ -47,7 +47,7 @@ #include <asm/system.h> #include <asm/au1000.h> -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, @@ -57,4 +57,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/db1x00/irqmap.c b/arch/mips/au1000/db1x00/irqmap.c index f63024a9893a..0138c5b7c860 100644 --- a/arch/mips/au1000/db1x00/irqmap.c +++ b/arch/mips/au1000/db1x00/irqmap.c @@ -80,7 +80,7 @@ char irq_tab_alchemy[][5] __initdata = { #endif -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { #ifndef CONFIG_MIPS_MIRAGE #ifdef CONFIG_MIPS_DB1550 @@ -101,4 +101,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/hydrogen3/irqmap.c b/arch/mips/au1000/hydrogen3/irqmap.c index 6eacaa0daa49..14e1ed37cf6b 100644 --- a/arch/mips/au1000/hydrogen3/irqmap.c +++ b/arch/mips/au1000/hydrogen3/irqmap.c @@ -47,10 +47,10 @@ #include <asm/system.h> #include <asm/au1000.h> -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { /* { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, */ { AU1000_GPIO_21, INTC_INT_LOW_LEVEL, 0 }, }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/mtx-1/irqmap.c b/arch/mips/au1000/mtx-1/irqmap.c index f9a0a8b9def2..4693a4eb2b82 100644 --- a/arch/mips/au1000/mtx-1/irqmap.c +++ b/arch/mips/au1000/mtx-1/irqmap.c @@ -58,7 +58,7 @@ char irq_tab_alchemy[][5] __initdata = { [7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */ }; -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, @@ -66,4 +66,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/pb1000/irqmap.c b/arch/mips/au1000/pb1000/irqmap.c index a3c460e3c23e..156500ba467f 100644 --- a/arch/mips/au1000/pb1000/irqmap.c +++ b/arch/mips/au1000/pb1000/irqmap.c @@ -47,8 +47,8 @@ #include <asm/system.h> #include <asm/mach-au1x00/au1000.h> -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 }, }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/pb1100/irqmap.c b/arch/mips/au1000/pb1100/irqmap.c index 43be7158b9ab..d986916221b7 100644 --- a/arch/mips/au1000/pb1100/irqmap.c +++ b/arch/mips/au1000/pb1100/irqmap.c @@ -47,11 +47,11 @@ #include <asm/system.h> #include <asm/mach-au1x00/au1000.h> -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted# { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG# { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ# { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ# }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c index 59e70e5cf325..bacc0c6bfe67 100644 --- a/arch/mips/au1000/pb1200/irqmap.c +++ b/arch/mips/au1000/pb1200/irqmap.c @@ -55,11 +55,11 @@ #define PB1200_INT_END DB1200_INT_END #endif -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); /* * Support for External interrupts on the PbAu1200 Development platform. diff --git a/arch/mips/au1000/pb1500/irqmap.c b/arch/mips/au1000/pb1500/irqmap.c index 8cb76c2edb5e..409d1612bb63 100644 --- a/arch/mips/au1000/pb1500/irqmap.c +++ b/arch/mips/au1000/pb1500/irqmap.c @@ -52,7 +52,7 @@ char irq_tab_alchemy[][5] __initdata = { [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */ }; -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, @@ -60,4 +60,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/pb1550/irqmap.c b/arch/mips/au1000/pb1550/irqmap.c index 47c7a1c19f4b..24a9d186cf5a 100644 --- a/arch/mips/au1000/pb1550/irqmap.c +++ b/arch/mips/au1000/pb1550/irqmap.c @@ -52,9 +52,9 @@ char irq_tab_alchemy[][5] __initdata = { [13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */ }; -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c index 52f2f7daeb05..3844c6429e27 100644 --- a/arch/mips/au1000/xxs1500/irqmap.c +++ b/arch/mips/au1000/xxs1500/irqmap.c @@ -47,7 +47,7 @@ #include <asm/system.h> #include <asm/au1000.h> -au1xxx_irq_map_t au1xxx_irq_map[] = { +au1xxx_irq_map_t __initdata au1xxx_irq_map[] = { { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, @@ -63,4 +63,4 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, }; -int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t); +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile new file mode 100644 index 000000000000..519142c2e4ef --- /dev/null +++ b/arch/mips/basler/excite/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for Basler eXcite +# + +obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \ + excite_device.o excite_procfs.o + +obj-$(CONFIG_KGDB) += excite_dbg_io.o +obj-m += excite_iodev.o diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c new file mode 100644 index 000000000000..83f6bddf578b --- /dev/null +++ b/arch/mips/basler/excite/excite_dbg_io.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/linkage.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <asm/gdb-stub.h> +#include <asm/rm9k-ocd.h> +#include <excite.h> + +#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1 +#error Debug port used by serial driver +#endif + +#define UART_CLK 25000000 +#define BASE_BAUD (UART_CLK / 16) +#define REGISTER_BASE_0 0x0208UL +#define REGISTER_BASE_1 0x0238UL + +#define REGISTER_BASE_DBG REGISTER_BASE_1 + +#define CPRR 0x0004 +#define UACFG 0x0200 +#define UAINTS 0x0204 +#define UARBR (REGISTER_BASE_DBG + 0x0000) +#define UATHR (REGISTER_BASE_DBG + 0x0004) +#define UADLL (REGISTER_BASE_DBG + 0x0008) +#define UAIER (REGISTER_BASE_DBG + 0x000c) +#define UADLH (REGISTER_BASE_DBG + 0x0010) +#define UAIIR (REGISTER_BASE_DBG + 0x0014) +#define UAFCR (REGISTER_BASE_DBG + 0x0018) +#define UALCR (REGISTER_BASE_DBG + 0x001c) +#define UAMCR (REGISTER_BASE_DBG + 0x0020) +#define UALSR (REGISTER_BASE_DBG + 0x0024) +#define UAMSR (REGISTER_BASE_DBG + 0x0028) +#define UASCR (REGISTER_BASE_DBG + 0x002c) + +#define PARITY_NONE 0 +#define PARITY_ODD 0x08 +#define PARITY_EVEN 0x18 +#define PARITY_MARK 0x28 +#define PARITY_SPACE 0x38 + +#define DATA_5BIT 0x0 +#define DATA_6BIT 0x1 +#define DATA_7BIT 0x2 +#define DATA_8BIT 0x3 + +#define STOP_1BIT 0x0 +#define STOP_2BIT 0x4 + +#define BAUD_DBG 57600 +#define PARITY_DBG PARITY_NONE +#define DATA_DBG DATA_8BIT +#define STOP_DBG STOP_1BIT + +/* Initialize the serial port for KGDB debugging */ +void __init excite_kgdb_init(void) +{ + const u32 divisor = BASE_BAUD / BAUD_DBG; + + /* Take the UART out of reset */ + titan_writel(0x00ff1cff, CPRR); + titan_writel(0x00000000, UACFG); + titan_writel(0x00000002, UACFG); + + titan_writel(0x0, UALCR); + titan_writel(0x0, UAIER); + + /* Disable FIFOs */ + titan_writel(0x00, UAFCR); + + titan_writel(0x80, UALCR); + titan_writel(divisor & 0xff, UADLL); + titan_writel((divisor & 0xff00) >> 8, UADLH); + titan_writel(0x0, UALCR); + + titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR); + + /* Enable receiver interrupt */ + titan_readl(UARBR); + titan_writel(0x1, UAIER); +} + +int getDebugChar(void) +{ + while (!(titan_readl(UALSR) & 0x1)); + return titan_readl(UARBR); +} + +int putDebugChar(int data) +{ + while (!(titan_readl(UALSR) & 0x20)); + titan_writel(data, UATHR); + return 1; +} + +/* KGDB interrupt handler */ +asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs) +{ + if (unlikely( + ((titan_readl(UAIIR) & 0x7) == 4) + && ((titan_readl(UARBR) & 0xff) == 0x3))) + set_async_breakpoint(®s->cp0_epc); +} diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c new file mode 100644 index 000000000000..34ec76716fa0 --- /dev/null +++ b/arch/mips/basler/excite/excite_device.c @@ -0,0 +1,404 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ioport.h> +#include <linux/err.h> +#include <linux/jiffies.h> +#include <linux/sched.h> +#include <asm/types.h> +#include <asm/rm9k-ocd.h> + +#include <excite.h> +#include <rm9k_eth.h> +#include <rm9k_wdt.h> +#include <rm9k_xicap.h> +#include <excite_nandflash.h> + +#include "excite_iodev.h" + +#define RM9K_GE_UNIT 0 +#define XICAP_UNIT 0 +#define NAND_UNIT 0 + +#define DLL_TIMEOUT 3 /* seconds */ + + +#define RINIT(__start__, __end__, __name__, __parent__) { \ + .name = __name__ "_0", \ + .start = (__start__), \ + .end = (__end__), \ + .flags = 0, \ + .parent = (__parent__) \ +} + +#define RINIT_IRQ(__irq__, __name__) { \ + .name = __name__ "_0", \ + .start = (__irq__), \ + .end = (__irq__), \ + .flags = IORESOURCE_IRQ, \ + .parent = NULL \ +} + + + +enum { + slice_xicap, + slice_eth +}; + + + +static struct resource + excite_ctr_resource = { + .name = "GPI counters", + .start = 0, + .end = 5, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_gpislice_resource = { + .name = "GPI slices", + .start = 0, + .end = 1, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_mdio_channel_resource = { + .name = "MDIO channels", + .start = 0, + .end = 1, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_fifomem_resource = { + .name = "FIFO memory", + .start = 0, + .end = 767, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_scram_resource = { + .name = "Scratch RAM", + .start = EXCITE_PHYS_SCRAM, + .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_fpga_resource = { + .name = "System FPGA", + .start = EXCITE_PHYS_FPGA, + .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_nand_resource = { + .name = "NAND flash control", + .start = EXCITE_PHYS_NAND, + .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_titan_resource = { + .name = "TITAN registers", + .start = EXCITE_PHYS_TITAN, + .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }; + + + +static void adjust_resources(struct resource *res, unsigned int n) +{ + struct resource *p; + const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM + | IORESOURCE_IRQ | IORESOURCE_DMA; + + for (p = res; p < res + n; p++) { + const struct resource * const parent = p->parent; + if (parent) { + p->start += parent->start; + p->end += parent->start; + p->flags = parent->flags & mask; + } + } +} + + + +#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) +static struct resource xicap_rsrc[] = { + RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource), + RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource), + RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource), + RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource), + RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource), + RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource), + RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource), + RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource), + RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ) +}; + +static struct platform_device xicap_pdev = { + .name = XICAP_NAME, + .id = XICAP_UNIT, + .num_resources = ARRAY_SIZE(xicap_rsrc), + .resource = xicap_rsrc +}; + +/* + * Create a platform device for the GPI port that receives the + * image data from the embedded camera. + */ +static int __init xicap_devinit(void) +{ + unsigned long tend; + u32 reg; + int retval; + + adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc)); + + /* Power up the slice and configure it. */ + reg = titan_readl(CPTC1R); + reg &= ~(0x11100 << slice_xicap); + titan_writel(reg, CPTC1R); + + /* Enable slice & DLL. */ + reg= titan_readl(CPRR); + reg &= ~(0x00030003 << (slice_xicap * 2)); + titan_writel(reg, CPRR); + + /* Wait for DLLs to lock */ + tend = jiffies + DLL_TIMEOUT * HZ; + while (time_before(jiffies, tend)) { + if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4)))) + break; + yield(); + } + + if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) { + printk(KERN_ERR "%s: DLL not locked after %u seconds\n", + xicap_pdev.name, DLL_TIMEOUT); + retval = -ETIME; + } else { + /* Register platform device */ + retval = platform_device_register(&xicap_pdev); + } + + return retval; +} + +device_initcall(xicap_devinit); +#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */ + + + +#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) +static struct resource wdt_rsrc[] = { + RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource), + RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource), + RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ) +}; + +static struct platform_device wdt_pdev = { + .name = WDT_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(wdt_rsrc), + .resource = wdt_rsrc +}; + +/* + * Create a platform device for the GPI port that receives the + * image data from the embedded camera. + */ +static int __init wdt_devinit(void) +{ + adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc)); + return platform_device_register(&wdt_pdev); +} + +device_initcall(wdt_devinit); +#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */ + + + +static struct resource excite_nandflash_rsrc[] = { + RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource) +}; + +static struct platform_device excite_nandflash_pdev = { + .name = "excite_nand", + .id = NAND_UNIT, + .num_resources = ARRAY_SIZE(excite_nandflash_rsrc), + .resource = excite_nandflash_rsrc +}; + +/* + * Create a platform device for the access to the nand-flash + * port + */ +static int __init excite_nandflash_devinit(void) +{ + adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc)); + + /* nothing to be done here */ + + /* Register platform device */ + return platform_device_register(&excite_nandflash_pdev); +} + +device_initcall(excite_nandflash_devinit); + + + +static struct resource iodev_rsrc[] = { + RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ) +}; + +static struct platform_device io_pdev = { + .name = IODEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(iodev_rsrc), + .resource = iodev_rsrc +}; + +/* + * Create a platform device for the external I/O ports. + */ +static int __init io_devinit(void) +{ + adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc)); + return platform_device_register(&io_pdev); +} + +device_initcall(io_devinit); + + + + +#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) +static struct resource rm9k_ge_rsrc[] = { + RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource), + RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource), + RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource), + RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource), + RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource), + RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource), + RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource), + RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource), + RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource), + RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource), + RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource), + RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource), + RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource), + RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN), + RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY) +}; + +static struct platform_device rm9k_ge_pdev = { + .name = RM9K_GE_NAME, + .id = RM9K_GE_UNIT, + .num_resources = ARRAY_SIZE(rm9k_ge_rsrc), + .resource = rm9k_ge_rsrc +}; + + + +/* + * Create a platform device for the Ethernet port. + */ +static int __init rm9k_ge_devinit(void) +{ + u32 reg; + + adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc)); + + /* Power up the slice and configure it. */ + reg = titan_readl(CPTC1R); + reg &= ~(0x11000 << slice_eth); + reg |= 0x100 << slice_eth; + titan_writel(reg, CPTC1R); + + /* Take the MAC out of reset, reset the DLLs. */ + reg = titan_readl(CPRR); + reg &= ~(0x00030000 << (slice_eth * 2)); + reg |= 0x3 << (slice_eth * 2); + titan_writel(reg, CPRR); + + return platform_device_register(&rm9k_ge_pdev); +} + +device_initcall(rm9k_ge_devinit); +#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */ + + + +static int __init excite_setup_devs(void) +{ + int res; + u32 reg; + + /* Enable xdma and fifo interrupts */ + reg = titan_readl(0x0050); + titan_writel(reg | 0x18000000, 0x0050); + + res = request_resource(&iomem_resource, &excite_titan_resource); + if (res) + return res; + res = request_resource(&iomem_resource, &excite_scram_resource); + if (res) + return res; + res = request_resource(&iomem_resource, &excite_fpga_resource); + if (res) + return res; + res = request_resource(&iomem_resource, &excite_nand_resource); + if (res) + return res; + excite_fpga_resource.flags = excite_fpga_resource.parent->flags & + ( IORESOURCE_IO | IORESOURCE_MEM + | IORESOURCE_IRQ | IORESOURCE_DMA); + excite_nand_resource.flags = excite_nand_resource.parent->flags & + ( IORESOURCE_IO | IORESOURCE_MEM + | IORESOURCE_IRQ | IORESOURCE_DMA); + + return 0; +} + +arch_initcall(excite_setup_devs); + diff --git a/arch/mips/basler/excite/excite_flashtest.c b/arch/mips/basler/excite/excite_flashtest.c new file mode 100644 index 000000000000..f0024a8e3294 --- /dev/null +++ b/arch/mips/basler/excite/excite_flashtest.c @@ -0,0 +1,294 @@ +/* +* Copyright (C) 2005 by Basler Vision Technologies AG +* Author: Thies Moeller <thies.moeller@baslerweb.com> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/ioport.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/kernel.h> + +#include <excite.h> + +#include <asm/io.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/partitions.h> +#include <asm/rm9k-ocd.h> // for ocd_write +#include <linux/workqueue.h> // for queue + +#include "excite_nandflash.h" +#include "nandflash.h" + +#define PFX "excite flashtest: " +typedef void __iomem *io_reg_t; + +#define io_readb(__a__) __raw_readb((__a__)) +#define io_writeb(__v__, __a__) __raw_writeb((__v__), (__a__)) + + + +static inline const struct resource *excite_nandflash_get_resource( + struct platform_device *d, unsigned long flags, const char *basename) +{ + const char fmt[] = "%s_%u"; + char buf[80]; + + if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf)) + return NULL; + + return platform_get_resource_byname(d, flags, buf); +} + +static inline io_reg_t +excite_nandflash_map_regs(struct platform_device *d, const char *basename) +{ + void *result = NULL; + const struct resource *const r = + excite_nandflash_get_resource(d, IORESOURCE_MEM, basename); + if (r) + result = ioremap_nocache(r->start, r->end + 1 - r->start); + return result; +} + +/* controller and mtd information */ + +struct excite_nandflash_drvdata { + struct mtd_info board_mtd; + struct nand_chip board_chip; + io_reg_t regs; +}; + + +/* command and control functions */ +static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs; + + switch (cmd) { + /* Select the command latch */ + case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD; + break; + /* Deselect the command latch */ + case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA; + break; + /* Select the address latch */ + case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR; + break; + /* Deselect the address latch */ + case NAND_CTL_CLRALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA; + break; + /* Select the chip -- not used */ + case NAND_CTL_SETNCE: + break; + /* Deselect the chip -- not used */ + case NAND_CTL_CLRNCE: + break; + } + + this->IO_ADDR_R = this->IO_ADDR_W; +} + +/* excite_nandflash_devready() + * + * returns 0 if the nand is busy, 1 if it is ready + */ +static int excite_nandflash_devready(struct mtd_info *mtd) +{ + struct excite_nandflash_drvdata *drvdata = + container_of(mtd, struct excite_nandflash_drvdata, board_mtd); + + return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS); +} + +/* device management functions */ + +/* excite_nandflash_remove + * + * called by device layer to remove the driver + * the binding to the mtd and all allocated + * resources are released + */ +static int excite_nandflash_remove(struct device *dev) +{ + struct excite_nandflash_drvdata *this = dev_get_drvdata(dev); + + pr_info(PFX "remove"); + + dev_set_drvdata(dev, NULL); + + if (this == NULL) { + pr_debug(PFX "call remove without private data!!"); + return 0; + } + + + /* free the common resources */ + if (this->regs != NULL) { + iounmap(this->regs); + this->regs = NULL; + } + + kfree(this); + + return 0; +} + +static int elapsed; + +void my_workqueue_handler(void *arg) +{ + elapsed = 1; +} + +DECLARE_WORK(sigElapsed, my_workqueue_handler, 0); + + +/* excite_nandflash_probe + * + * called by device layer when it finds a device matching + * one our driver can handled. This code checks to see if + * it can allocate all necessary resources then calls the + * nand layer to look for devices +*/ +static int excite_nandflash_probe(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + struct excite_nandflash_drvdata *drvdata; /* private driver data */ + struct nand_chip *board_chip; /* private flash chip data */ + struct mtd_info *board_mtd; /* mtd info for this board */ + + int err = 0; + int count = 0; + struct timeval tv,endtv; + unsigned int dt; + + pr_info(PFX "probe dev: (%p)\n", dev); + + pr_info(PFX "adjust LB timing\n"); + ocd_writel(0x00000330, LDP2); + + drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL); + if (unlikely(!drvdata)) { + printk(KERN_ERR PFX "no memory for drvdata\n"); + err = -ENOMEM; + goto mem_error; + } + + /* Initialize structures */ + memset(drvdata, 0, sizeof(*drvdata)); + + /* bind private data into driver */ + dev_set_drvdata(dev, drvdata); + + /* allocate and map the resource */ + drvdata->regs = + excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS); + + if (unlikely(!drvdata->regs)) { + printk(KERN_ERR PFX "cannot reserve register region\n"); + err = -ENXIO; + goto io_error; + } + + /* initialise our chip */ + board_chip = &drvdata->board_chip; + + board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA; + board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA; + + board_chip->hwcontrol = excite_nandflash_hwcontrol; + board_chip->dev_ready = excite_nandflash_devready; + + board_chip->chip_delay = 25; + #if 0 + /* TODO: speedup the initial scan */ + board_chip->options = NAND_USE_FLASH_BBT; + #endif + board_chip->eccmode = NAND_ECC_SOFT; + + /* link chip to mtd */ + board_mtd = &drvdata->board_mtd; + board_mtd->priv = board_chip; + + + pr_info(PFX "FlashTest\n"); + elapsed = 0; +/* schedule_delayed_work(&sigElapsed, 1*HZ); + while (!elapsed) { + io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS); + count++; + } + pr_info(PFX "reads in 1 sec --> %d\n",count); +*/ + do_gettimeofday(&tv); + for (count = 0 ; count < 1000000; count ++) { + io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS); + } + do_gettimeofday(&endtv); + dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec - tv.tv_usec; + pr_info(PFX "%8d us timeval\n",dt); + pr_info(PFX "EndFlashTest\n"); + +/* return with error to unload everything +*/ +io_error: + iounmap(drvdata->regs); + +mem_error: + kfree(drvdata); + + if (err == 0) + err = -EINVAL; + return err; +} + +static struct device_driver excite_nandflash_driver = { + .name = "excite_nand", + .bus = &platform_bus_type, + .probe = excite_nandflash_probe, + .remove = excite_nandflash_remove, +}; + +static int __init excite_nandflash_init(void) +{ + pr_info(PFX "register Driver (Rev: $Revision:$)\n"); + return driver_register(&excite_nandflash_driver); +} + +static void __exit excite_nandflash_exit(void) +{ + driver_unregister(&excite_nandflash_driver); + pr_info(PFX "Driver unregistered"); +} + +module_init(excite_nandflash_init); +module_exit(excite_nandflash_exit); + +MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>"); +MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/basler/excite/excite_fpga.h b/arch/mips/basler/excite/excite_fpga.h new file mode 100644 index 000000000000..38fcda703a0b --- /dev/null +++ b/arch/mips/basler/excite/excite_fpga.h @@ -0,0 +1,80 @@ +#ifndef EXCITE_FPGA_H_INCLUDED +#define EXCITE_FPGA_H_INCLUDED + + +/** + * Adress alignment of the individual FPGA bytes. + * The address arrangement of the individual bytes of the FPGA is two + * byte aligned at the embedded MK2 platform. + */ +#ifdef EXCITE_CCI_FPGA_MK2 +typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2))); +#else +typedef unsigned char excite_cci_fpga_align_t; +#endif + + +/** + * Size of Dual Ported RAM. + */ +#define EXCITE_DPR_SIZE 263 + + +/** + * Size of Reserved Status Fields in Dual Ported RAM. + */ +#define EXCITE_DPR_STATUS_SIZE 7 + + + +/** + * FPGA. + * Hardware register layout of the FPGA interface. The FPGA must accessed + * byte wise solely. + * @see EXCITE_CCI_DPR_MK2 + */ +typedef struct excite_fpga { + + /** + * Dual Ported RAM. + */ + excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE]; + + /** + * Status. + */ + excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE]; + +#ifdef EXCITE_CCI_FPGA_MK2 + /** + * RM9000 Interrupt. + * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite. + */ + excite_cci_fpga_align_t rm9k_int; +#else + /** + * MK2 Interrupt. + * Write access initiates interrupt at the ARM processor of the MK2. + */ + excite_cci_fpga_align_t mk2_int; + + excite_cci_fpga_align_t gap[0x1000-0x10f]; + + /** + * IRQ Source/Acknowledge. + */ + excite_cci_fpga_align_t rm9k_irq_src; + + /** + * IRQ Mask. + * Set bits enable the related interrupt. + */ + excite_cci_fpga_align_t rm9k_irq_mask; +#endif + + +} excite_fpga; + + + +#endif /* ndef EXCITE_FPGA_H_INCLUDED */ diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c new file mode 100644 index 000000000000..91121e523043 --- /dev/null +++ b/arch/mips/basler/excite/excite_iodev.c @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2005 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/compiler.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/wait.h> +#include <linux/poll.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/miscdevice.h> + +#include "excite_iodev.h" + + + +static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int); +static int __init iodev_probe(struct device *); +static int __exit iodev_remove(struct device *); +static int iodev_open(struct inode *, struct file *); +static int iodev_release(struct inode *, struct file *); +static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *); +static unsigned int iodev_poll(struct file *, struct poll_table_struct *); +static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *); + + + +static const char iodev_name[] = "iodev"; +static unsigned int iodev_irq; +static DECLARE_WAIT_QUEUE_HEAD(wq); + + + +static struct file_operations fops = +{ + .owner = THIS_MODULE, + .open = iodev_open, + .release = iodev_release, + .read = iodev_read, + .poll = iodev_poll +}; + +static struct miscdevice miscdev = +{ + .minor = MISC_DYNAMIC_MINOR, + .name = iodev_name, + .fops = &fops +}; + +static struct device_driver iodev_driver = +{ + .name = (char *) iodev_name, + .bus = &platform_bus_type, + .owner = THIS_MODULE, + .probe = iodev_probe, + .remove = __exit_p(iodev_remove) +}; + + + +static const struct resource * +iodev_get_resource(struct platform_device *pdv, const char *name, + unsigned int type) +{ + char buf[80]; + if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf) + return NULL; + return platform_get_resource_byname(pdv, type, buf); +} + + + +/* No hotplugging on the platform bus - use __init */ +static int __init iodev_probe(struct device *dev) +{ + struct platform_device * const pdv = to_platform_device(dev); + const struct resource * const ri = + iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ); + + if (unlikely(!ri)) + return -ENXIO; + + iodev_irq = ri->start; + return misc_register(&miscdev); +} + + + +static int __exit iodev_remove(struct device *dev) +{ + return misc_deregister(&miscdev); +} + + + +static int iodev_open(struct inode *i, struct file *f) +{ + return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT, + iodev_name, &miscdev); +} + + + +static int iodev_release(struct inode *i, struct file *f) +{ + free_irq(iodev_irq, &miscdev); + return 0; +} + + + + +static ssize_t +iodev_read(struct file *f, char __user *d, size_t s, loff_t *o) +{ + ssize_t ret; + DEFINE_WAIT(w); + + prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE); + if (!signal_pending(current)) + schedule(); + ret = signal_pending(current) ? -ERESTARTSYS : 0; + finish_wait(&wq, &w); + return ret; +} + + +static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p) +{ + poll_wait(f, &wq, p); + return POLLOUT | POLLWRNORM; +} + + + + +static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs) +{ + wake_up(&wq); + return IRQ_HANDLED; +} + + + +static int __init iodev_init_module(void) +{ + return driver_register(&iodev_driver); +} + + + +static void __exit iodev_cleanup_module(void) +{ + driver_unregister(&iodev_driver); +} + +module_init(iodev_init_module); +module_exit(iodev_cleanup_module); + + + +MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>"); +MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler"); +MODULE_VERSION("0.0"); +MODULE_LICENSE("GPL"); diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h new file mode 100644 index 000000000000..cbfbb5d2ee62 --- /dev/null +++ b/arch/mips/basler/excite/excite_iodev.h @@ -0,0 +1,10 @@ +#ifndef __EXCITE_IODEV_H__ +#define __EXCITE_IODEV_H__ + +/* Device name */ +#define IODEV_NAME "iodev" + +/* Resource names */ +#define IODEV_RESOURCE_IRQ "excite_iodev_irq" + +#endif /* __EXCITE_IODEV_H__ */ diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c new file mode 100644 index 000000000000..511ad8730f54 --- /dev/null +++ b/arch/mips/basler/excite/excite_irq.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslereb.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <asm/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/irq_cpu.h> +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/rm9k-ocd.h> + +#include <excite.h> + +extern asmlinkage void excite_handle_int(void); + +/* + * Initialize the interrupt handler + */ +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(0); + rm7k_cpu_irq_init(8); + rm9k_cpu_irq_init(12); + +#ifdef CONFIG_KGDB + excite_kgdb_init(); +#endif +} + +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + const u32 + interrupts = read_c0_cause() >> 8, + mask = ((read_c0_status() >> 8) & 0x000000ff) | + (read_c0_intcontrol() & 0x0000ff00), + pending = interrupts & mask; + u32 msgintflags, msgintmask, msgint; + + /* process timer interrupt */ + if (pending & (1 << TIMER_IRQ)) { + do_IRQ(TIMER_IRQ, regs); + return; + } + + /* Process PCI interrupts */ +#if USB_IRQ < 10 + msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20)); + if ((pending & (1 << USB_IRQ)) && msgint) { +#else + if (pending & (1 << USB_IRQ)) { +#endif + do_IRQ(USB_IRQ, regs); + return; + } + + /* Process TITAN interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20)); + if ((pending & (1 << TITAN_IRQ)) && msgint) { + ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); +#if defined(CONFIG_KGDB) + excite_kgdb_inthdl(regs); +#endif + do_IRQ(TITAN_IRQ, regs); + return; + } + + /* Process FPGA line #0 interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20)); + if ((pending & (1 << FPGA0_IRQ)) && msgint) { + do_IRQ(FPGA0_IRQ, regs); + return; + } + + /* Process FPGA line #1 interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20)); + if ((pending & (1 << FPGA1_IRQ)) && msgint) { + do_IRQ(FPGA1_IRQ, regs); + return; + } + + /* Process PHY interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20)); + if ((pending & (1 << PHY_IRQ)) && msgint) { + do_IRQ(PHY_IRQ, regs); + return; + } + + /* Process spurious interrupts */ + spurious_interrupt(regs); +} diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c new file mode 100644 index 000000000000..c62be0341fb8 --- /dev/null +++ b/arch/mips/basler/excite/excite_procfs.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2004, 2005 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * + * Procfs support for Basler eXcite + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/proc_fs.h> +#include <linux/stat.h> +#include <asm/page.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/rm9k-ocd.h> + +#include <excite.h> + +static int excite_get_unit_id(char *buf, char **addr, off_t offs, int size) +{ + const int len = snprintf(buf, PAGE_SIZE, "%06x", unit_id); + const int w = len - offs; + *addr = buf + offs; + return w < size ? w : size; +} + +static int +excite_bootrom_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + void __iomem * src; + + if (off >= EXCITE_SIZE_BOOTROM) { + *eof = 1; + return 0; + } + + if ((off + count) > EXCITE_SIZE_BOOTROM) + count = EXCITE_SIZE_BOOTROM - off; + + src = ioremap(EXCITE_PHYS_BOOTROM + off, count); + if (src) { + memcpy_fromio(page, src, count); + iounmap(src); + *start = page; + } else { + count = -ENOMEM; + } + + return count; +} + +void excite_procfs_init(void) +{ + /* Create & populate /proc/excite */ + struct proc_dir_entry * const pdir = proc_mkdir("excite", &proc_root); + if (pdir) { + struct proc_dir_entry * e; + + e = create_proc_info_entry("unit_id", S_IRUGO, pdir, + excite_get_unit_id); + if (e) e->size = 6; + + e = create_proc_read_entry("bootrom", S_IRUGO, pdir, + excite_bootrom_read, NULL); + if (e) e->size = EXCITE_SIZE_BOOTROM; + } +} diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c new file mode 100644 index 000000000000..84724b270753 --- /dev/null +++ b/arch/mips/basler/excite/excite_prom.c @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com) + * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and + * Manish Lachwani. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/smp.h> +#include <linux/module.h> +#include <asm/io.h> +#include <asm/pgtable.h> +#include <asm/processor.h> +#include <asm/reboot.h> +#include <asm/system.h> +#include <asm/bootinfo.h> +#include <asm/string.h> + +#include <excite.h> + +/* This struct is used by Redboot to pass arguments to the kernel */ +typedef struct +{ + char *name; + char *val; +} t_env_var; + +struct parmblock { + t_env_var memsize; + t_env_var modetty0; + t_env_var ethaddr; + t_env_var env_end; + char *argv[2]; + char text[0]; +}; + +static unsigned int prom_argc; +static const char ** prom_argv; +static const t_env_var * prom_env; + +static void prom_halt(void) __attribute__((noreturn)); +static void prom_exit(void) __attribute__((noreturn)); + + + +const char *get_system_type(void) +{ + return "Basler eXcite"; +} + +/* + * Halt the system + */ +static void prom_halt(void) +{ + printk(KERN_NOTICE "\n** System halted.\n"); + while (1) + asm volatile ( + "\t.set\tmips3\n" + "\twait\n" + "\t.set\tmips0\n" + ); +} + +/* + * Reset the CPU and re-enter Redboot + */ +static void prom_exit(void) +{ + unsigned int i; + volatile unsigned char * const flg = + (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR); + + /* Clear the watchdog reset flag, set the reboot flag */ + *flg &= ~0x01; + *flg |= 0x80; + + for (i = 0; i < 10; i++) { + *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02; + iob(); + mdelay(1000); + } + + printk(KERN_NOTICE "Reset failed\n"); + prom_halt(); +} + +static const char __init *prom_getenv(char *name) +{ + const t_env_var * p; + for (p = prom_env; p->name != NULL; p++) + if(strcmp(name, p->name) == 0) + break; + return p->val; +} + +/* + * Init routine which accepts the variables from Redboot + */ +void __init prom_init(void) +{ + const struct parmblock * const pb = (struct parmblock *) fw_arg2; + + prom_argc = fw_arg0; + prom_argv = (const char **) fw_arg1; + prom_env = &pb->memsize; + + /* Callbacks for halt, restart */ + _machine_restart = (void (*)(char *)) prom_exit; + _machine_halt = prom_halt; + +#ifdef CONFIG_32BIT + /* copy command line */ + strcpy(arcs_cmdline, prom_argv[1]); + memsize = simple_strtol(prom_getenv("memsize"), NULL, 16); + strcpy(modetty, prom_getenv("modetty0")); +#endif /* CONFIG_32BIT */ + +#ifdef CONFIG_64BIT +# error 64 bit support not implemented +#endif /* CONFIG_64BIT */ + + mips_machgroup = MACH_GROUP_TITAN; + mips_machtype = MACH_TITAN_EXCITE; +} + +/* This is called from free_initmem(), so we need to provide it */ +void __init prom_free_prom_memory(void) +{ + /* Nothing to do */ +} diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c new file mode 100644 index 000000000000..005b025605e6 --- /dev/null +++ b/arch/mips/basler/excite/excite_setup.c @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2004, 2005 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and + * Manish Lachwani. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/tty.h> +#include <linux/serial_core.h> +#include <linux/serial.h> +#include <linux/ioport.h> +#include <linux/spinlock.h> +#include <asm/bootinfo.h> +#include <asm/mipsregs.h> +#include <asm/pgtable-32.h> +#include <asm/io.h> +#include <asm/time.h> +#include <asm/rm9k-ocd.h> + +#include <excite.h> + +#define TITAN_UART_CLK 25000000 + +#if 1 +/* normal serial port assignment */ +#define REGBASE_SER0 0x0208 +#define REGBASE_SER1 0x0238 +#define MASK_SER0 0x1 +#define MASK_SER1 0x2 +#else +/* serial ports swapped */ +#define REGBASE_SER0 0x0238 +#define REGBASE_SER1 0x0208 +#define MASK_SER0 0x2 +#define MASK_SER1 0x1 +#endif + +unsigned long memsize; +char modetty[30]; +unsigned int titan_irq = TITAN_IRQ; +static void __iomem * ctl_regs; +u32 unit_id; + +volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD); +volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN); + +/* Protect access to shared GPI registers */ +spinlock_t titan_lock = SPIN_LOCK_UNLOCKED; +int titan_irqflags; + + +static void excite_timer_init(void) +{ + const u32 modebit5 = ocd_readl(0x00e4); + unsigned int + mult = ((modebit5 >> 11) & 0x1f) + 2, + div = ((modebit5 >> 16) & 0x1f) + 2; + + if (div == 33) div = 1; + mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2; +} + +static void excite_timer_setup(struct irqaction *irq) +{ + /* The eXcite platform uses the alternate timer interrupt */ + set_c0_intcontrol(0x80); + setup_irq(TIMER_IRQ, irq); +} + +static int __init excite_init_console(void) +{ +#if defined(CONFIG_SERIAL_8250) + static __initdata char serr[] = + KERN_ERR "Serial port #%u setup failed\n"; + struct uart_port up; + + /* Take the DUART out of reset */ + titan_writel(0x00ff1cff, CPRR); + +#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1) + /* Enable both ports */ + titan_writel(MASK_SER0 | MASK_SER1, UACFG); +#else + /* Enable port #0 only */ + titan_writel(MASK_SER0, UACFG); +#endif /* defined(CONFIG_KGDB) */ + + /* + * Set up serial port #0. Do not use autodetection; the result is + * not what we want. + */ + memset(&up, 0, sizeof(up)); + up.membase = (char *) titan_addr(REGBASE_SER0); + up.irq = TITAN_IRQ; + up.uartclk = TITAN_UART_CLK; + up.regshift = 0; + up.iotype = UPIO_MEM32; + up.type = PORT_RM9000; + up.flags = UPF_SHARE_IRQ; + up.line = 0; + if (early_serial_setup(&up)) + printk(serr, up.line); + +#if CONFIG_SERIAL_8250_NR_UARTS > 1 + /* And now for port #1. */ + up.membase = (char *) titan_addr(REGBASE_SER1); + up.line = 1; + if (early_serial_setup(&up)) + printk(serr, up.line); +#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */ +#else + /* Leave the DUART in reset */ + titan_writel(0x00ff3cff, CPRR); +#endif /* defined(CONFIG_SERIAL_8250) */ + + return 0; +} + +static int __init excite_platform_init(void) +{ + unsigned int i; + unsigned char buf[3]; + u8 reg; + void __iomem * dpr; + + /* BIU buffer allocations */ + ocd_writel(8, CPURSLMT); /* CPU */ + titan_writel(4, CPGRWL); /* GPI / Ethernet */ + + /* Map control registers located in FPGA */ + ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16); + if (!ctl_regs) + panic("eXcite: failed to map platform control registers\n"); + memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf)); + unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16); + + /* Clear the reboot flag */ + dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1); + reg = __raw_readb(dpr); + __raw_writeb(reg & 0x7f, dpr); + iounmap(dpr); + + /* Interrupt controller setup */ + for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) { + ocd_writel(0x00000000, i + 0x04); + ocd_writel(0xffffffff, i + 0x0c); + } + ocd_writel(0x2, NMICONFIG); + + ocd_writel(0x1 << (TITAN_MSGINT % 0x20), + INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20))); + ocd_writel((0x1 << (FPGA0_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))); + ocd_writel((0x1 << (FPGA1_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))); + ocd_writel((0x1 << (PHY_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))); +#if USB_IRQ < 10 + ocd_writel((0x1 << (USB_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))); +#endif + /* Enable the packet FIFO, XDMA and XDMA arbiter */ + titan_writel(0x00ff18ff, CPRR); + + /* + * Set up the PADMUX. Power down all ethernet slices, + * they will be powered up and configured at device startup. + */ + titan_writel(0x00878206, CPTC1R); + titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */ + + /* Reset and enable the FIFO block */ + titan_writel(0x00000001, SDRXFCIE); + titan_writel(0x00000001, SDTXFCIE); + titan_writel(0x00000100, SDRXFCIE); + titan_writel(0x00000000, SDTXFCIE); + + /* + * Initialize the common interrupt shared by all components of + * the GPI/Ethernet subsystem. + */ + titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0); + titan_writel(TITAN_MSGINT, CPCFG1); + + /* + * XDMA configuration. + * In order for the XDMA to be sharable among multiple drivers, + * the setup must be done here in the platform. The reason is that + * this setup can only be done while the XDMA is in reset. If this + * were done in a driver, it would interrupt all other drivers + * using the XDMA. + */ + titan_writel(0x80021dff, GXCFG); /* XDMA reset */ + titan_writel(0x00000000, CPXCISRA); + titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */ +#if defined (CONFIG_HIGHMEM) +# error change for HIGHMEM support! +#else + titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */ +#endif + titan_writel(0, GXDMA_DESCADR); + + for (i = 0x5040; i <= 0x5300; i += 0x0040) + titan_writel(0x80080000, i); /* reset channel */ + + titan_writel((0x1 << 29) /* no sparse tx descr. */ + | (0x1 << 28) /* no sparse rx descr. */ + | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */ + | (0x1 << 21) | (0x1 << 22) /* data coherency */ + | (0x1 << 17) + | 0x1dff, + GXCFG); + +#if defined(CONFIG_SMP) +# error No SMP support +#else + /* All interrupts go to core #0 only. */ + titan_writel(0x1f007fff, CPDST0A); + titan_writel(0x00000000, CPDST0B); + titan_writel(0x0000ff3f, CPDST1A); + titan_writel(0x00000000, CPDST1B); + titan_writel(0x00ffffff, CPXDSTA); + titan_writel(0x00000000, CPXDSTB); +#endif + + /* Enable DUART interrupts, disable everything else. */ + titan_writel(0x04000000, CPGIG0ER); + titan_writel(0x000000c0, CPGIG1ER); + + excite_procfs_init(); + return 0; +} + +void __init plat_setup(void) +{ + volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000; + + /* Announce RAM to system */ + add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); + + /* Set up timer initialization hooks */ + board_time_init = excite_timer_init; + board_timer_setup = excite_timer_setup; + + /* Set up the peripheral address map */ + *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0; + *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0; + *(boot_ocd_base + (LKB11 / sizeof (u32))) = 0; + *(boot_ocd_base + (LKB12 / sizeof (u32))) = 0; + wmb(); + *(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4; + wmb(); + + ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5); + ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5); + ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13); + ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13); + + /* Local bus slot #0 */ + ocd_writel(0x00040510, LDP0); + ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9); + ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9); + + /* Local bus slot #2 */ + ocd_writel(0x00000330, LDP2); + ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11); + ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11); + + /* Local bus slot #3 */ + ocd_writel(0x00123413, LDP3); + ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12); + ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12); +} + + + +console_initcall(excite_init_console); +arch_initcall(excite_platform_init); + +EXPORT_SYMBOL(titan_lock); +EXPORT_SYMBOL(titan_irqflags); +EXPORT_SYMBOL(titan_irq); +EXPORT_SYMBOL(ocd_base); +EXPORT_SYMBOL(titan_base); diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c index 45c2d27c7564..300797d5f558 100644 --- a/arch/mips/cobalt/console.c +++ b/arch/mips/cobalt/console.c @@ -41,3 +41,8 @@ void __init cobalt_early_console(void) printk("Cobalt: early console registered\n"); } + +void __init disable_early_printk(void) +{ + unregister_console(&cons_info); +} diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 4f9ea1210023..ca719d6398bd 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -68,19 +68,46 @@ static void __init cobalt_timer_setup(struct irqaction *irq) extern struct pci_ops gt64111_pci_ops; static struct resource cobalt_mem_resource = { - "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM + .start = GT64111_MEM_BASE, + .end = GT64111_MEM_END, + .name = "PCI memory", + .flags = IORESOURCE_MEM }; static struct resource cobalt_io_resource = { - "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO + .start = 0x1000, + .end = 0xffff, + .name = "PCI I/O", + .flags = IORESOURCE_IO }; static struct resource cobalt_io_resources[] = { - { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, - { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, - { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, - { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, - { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, + { + .start = 0x00, + .end = 0x1f, + .name = "dma1", + .flags = IORESOURCE_BUSY + }, { + .start = 0x40, + .end = 0x5f, + .name = "timer", + .flags = IORESOURCE_BUSY + }, { + .start = 0x60, + .end = 0x6f, + .name = "keyboard", + .flags = IORESOURCE_BUSY + }, { + .start = 0x80, + .end = 0x8f, + .name = "dma page reg", + .flags = IORESOURCE_BUSY + }, { + .start = 0xc0, + .end = 0xdf, + .name = "dma2", + .flags = IORESOURCE_BUSY + }, }; #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource)) @@ -93,7 +120,7 @@ static struct pci_controller cobalt_pci_controller = { .io_offset = 0 - GT64111_IO_BASE }; -void __init plat_setup(void) +void __init plat_mem_setup(void) { static struct uart_port uart; unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index 4b080bcb258f..0cc1b3c51959 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_ATLAS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -143,6 +141,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index d85cda58d650..dabf90a94b21 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -145,6 +143,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_SMP=y CONFIG_NR_CPUS=4 CONFIG_PREEMPT_NONE=y diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index ca0af1683a00..aeb7be804799 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set @@ -132,6 +130,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 7d269e609282..d680d3e17112 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -129,6 +127,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 579b665e3339..6a7aa401462f 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index e5eb53867422..5c2da563e528 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index a43fb2329fd5..85ef90ce0944 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index ad632d87c4ef..6f757d8a5a6c 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -132,6 +130,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 8130e23dc255..da4c7e811bef 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -131,6 +129,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig index 8c911b671415..c1c6bfee970e 100644 --- a/arch/mips/configs/ddb5477_defconfig +++ b/arch/mips/configs/ddb5477_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set CONFIG_DDB5477=y # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -129,6 +127,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index d838496e114f..d5d0d3faae94 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -41,8 +41,6 @@ CONFIG_MACH_DECSTATION=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -128,6 +126,17 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_128=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_128HZ=y +CONFIG_SYS_SUPPORTS_256HZ=y +CONFIG_SYS_SUPPORTS_1024HZ=y +CONFIG_HZ=128 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 0760f4318910..439677ba751c 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig new file mode 100644 index 000000000000..01f29f44f3e8 --- /dev/null +++ b/arch/mips/configs/emma2rh_defconfig @@ -0,0 +1,1207 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.17 +# Sun Jun 18 13:46:53 2006 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_WR_PPMC is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +CONFIG_MARKEINS=y +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_EMMA2RH=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_BKL=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_RELAY is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set +CONFIG_OBSOLETE_INTERMODULE=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_FWMARK is not set +CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_QUEUE is not set + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +# CONFIG_IP6_NF_QUEUE is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x1e000000 +CONFIG_MTD_PHYSMAP_LEN=0x02000000 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +CONFIG_NATSEMI=y +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +CONFIG_RTC=m +CONFIG_GEN_RTC=m +CONFIG_GEN_RTC_X=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_ISA is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +CONFIG_I2C_DEBUG_CORE=y +# CONFIG_I2C_DEBUG_ALGO is not set +CONFIG_I2C_DEBUG_BUS=y +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +CONFIG_VIDEO_V4L2=y + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_XFS_FS=m +CONFIG_XFS_EXPORT=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +CONFIG_NFS_DIRECTIO=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_NFSD_TCP=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_DEBUG_FS is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig index 7067f608b22c..5248a1d8131d 100644 --- a/arch/mips/configs/ev64120_defconfig +++ b/arch/mips/configs/ev64120_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_EV64120=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -131,6 +129,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig index 00b56ed0e638..4858491ce669 100644 --- a/arch/mips/configs/ev96100_defconfig +++ b/arch/mips/configs/ev96100_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_EV96100=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -135,6 +133,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig new file mode 100644 index 000000000000..f2ce64cb41a8 --- /dev/null +++ b/arch/mips/configs/excite_defconfig @@ -0,0 +1,1220 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.16-rc4 +# Thu Feb 23 13:15:27 2006 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +CONFIG_BASLER_EXCITE=y +# CONFIG_BASLER_EXCITE_PROTOTYPE is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_DMA_COHERENT=y +CONFIG_SERIAL_RM9000=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_CPU_RM7K=y +CONFIG_IRQ_CPU_RM9K=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RM9000=y +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM9000=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +# CONFIG_SMP is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_BKL=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +CONFIG_SLAB=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +# CONFIG_LBD is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +# CONFIG_PCI_LEGACY_PROC is not set +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +CONFIG_MTD_NAND_BASLER_EXCITE=y +# CONFIG_MTD_NAND_BASLER_EXCITE_RDNBY is not set +# CONFIG_MTD_NAND_BASLER_EXCITE_PERF is not set +# CONFIG_MTD_NAND_NANDSIM is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM_COUNT=16 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_FC is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_TITAN_GE is not set +CONFIG_RM9K_GE=m + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_WDT_RM9K_GPI=m + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON_OLD is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_DD=y + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=m +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y + +# +# Logo configuration +# +# CONFIG_LOGO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +CONFIG_USB_HIDINPUT=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_ITMTOUCH is not set +# CONFIG_USB_EGALAX is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_ATI_REMOTE2 is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +CONFIG_USB_ARTTFT=m +# CONFIG_USB_ARTTOUCH is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGETKIT is not set +# CONFIG_USB_PHIDGETSERVO is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# SN Devices +# + +# +# EDAC - error detection and reporting (RAS) +# + +# +# eXcite frame capture support +# +CONFIG_EXCITE_FCAP=m +CONFIG_EXCITE_FCAP_GPI=m + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 607e2985ffe3..879ba1ad99ca 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -136,6 +134,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index f724b4b2ecf2..bb1426806430 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -63,7 +61,7 @@ CONFIG_SGI_IP27=y # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set -# CONFIG_SGI_SN0_N_MODE is not set +# CONFIG_SGI_SN_N_MODE is not set CONFIG_ARCH_DISCONTIGMEM_ENABLE=y CONFIG_NUMA=y # CONFIG_MAPPED_KERNEL is not set @@ -135,6 +133,15 @@ CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_MIGRATION=y CONFIG_SMP=y CONFIG_NR_CPUS=64 diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 8f11d3565b2d..31b3c92a3841 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -136,6 +134,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig index 757adf23853d..809bae9013ac 100644 --- a/arch/mips/configs/it8172_defconfig +++ b/arch/mips/configs/it8172_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_ITE8172=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig index 021761a8a237..55108fd67844 100644 --- a/arch/mips/configs/ivr_defconfig +++ b/arch/mips/configs/ivr_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_IVR=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -127,6 +125,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig index 08f6c30b0abc..ef2843436057 100644 --- a/arch/mips/configs/jaguar-atx_defconfig +++ b/arch/mips/configs/jaguar-atx_defconfig @@ -41,8 +41,6 @@ CONFIG_MOMENCO_JAGUAR_ATX=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -136,6 +134,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 # CONFIG_SMP is not set CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 38b1e026e10d..5ef5a08289a5 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -125,6 +123,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig index 4d25990a0a05..eabcff26fc0e 100644 --- a/arch/mips/configs/lasat200_defconfig +++ b/arch/mips/configs/lasat200_defconfig @@ -41,8 +41,6 @@ CONFIG_LASAT=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -134,6 +132,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 977f52be51dc..b73cff0d83ca 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_MALTA=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -154,6 +152,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 00560e0143f1..8dd27b55413d 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_SIM=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -138,6 +136,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 286a018375b2..5d6ff3c352c9 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set @@ -132,6 +130,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig index 1ce4310fd92a..fe5e3dd915f5 100644 --- a/arch/mips/configs/ocelot_3_defconfig +++ b/arch/mips/configs/ocelot_3_defconfig @@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT_3=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -136,6 +134,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 # CONFIG_SMP is not set CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig index 8a6aa5012f89..f4a33ce47e50 100644 --- a/arch/mips/configs/ocelot_c_defconfig +++ b/arch/mips/configs/ocelot_c_defconfig @@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT_C=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -133,6 +131,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig index f9ee35eeb762..21dea9549feb 100644 --- a/arch/mips/configs/ocelot_defconfig +++ b/arch/mips/configs/ocelot_defconfig @@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -137,6 +135,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig index b48bdee2411f..c63b1ca8c8b3 100644 --- a/arch/mips/configs/ocelot_g_defconfig +++ b/arch/mips/configs/ocelot_g_defconfig @@ -41,8 +41,6 @@ CONFIG_MOMENCO_OCELOT_G=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -136,6 +134,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 01aac40634b4..6f5c7261e9de 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -132,6 +130,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 398c3c265b9f..5676f3747fd5 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -131,6 +129,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index ea282a53bb66..a1c479fa613b 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_PB1550=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -131,6 +129,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 4c57e564db0b..b2d991b80309 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set CONFIG_PNX8550_JBS=y -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig index 3c8f35162fec..fe092ac92e89 100644 --- a/arch/mips/configs/pnx8550-v2pci_defconfig +++ b/arch/mips/configs/pnx8550-v2pci_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set CONFIG_PNX8550_V2PCI=y # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig index 4bcc01dea041..db8701344cee 100644 --- a/arch/mips/configs/qemu_defconfig +++ b/arch/mips/configs/qemu_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -128,6 +126,15 @@ CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_SMP is not set +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 3d441932e43a..b16731f3684b 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -138,6 +136,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index edfb9679a25a..8b0dd8651264 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -138,6 +136,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index e388a3dae0a9..ff34ed66fe65 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -149,6 +147,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT_NONE=y diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 6b8a6a416a25..77edeae7f018 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS_SEAD=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -134,6 +132,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index dba0bdcdcf29..6aa229d54851 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set @@ -134,6 +132,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig index 5a924c1a5803..a187b1f0004c 100644 --- a/arch/mips/configs/tb0229_defconfig +++ b/arch/mips/configs/tb0229_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set @@ -134,6 +132,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 9f215ea350dc..258457fcbe11 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set @@ -135,6 +133,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index ac7765eb8da7..68af54f746e1 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set CONFIG_MACH_VR41XX=y # CONFIG_PMC_YOSEMITE is not set @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/wrppmc_defconfig index 8d88ac1bbfeb..40572a3c8cac 100644 --- a/arch/mips/configs/ddb5476_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.17-rc2 -# Mon Apr 24 14:51:00 2006 +# Linux kernel version: 2.6.16.11 +# Fri May 5 17:11:22 2006 # CONFIG_MIPS=y @@ -32,6 +32,7 @@ CONFIG_MIPS=y # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +CONFIG_WR_PPMC=y # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set @@ -41,8 +42,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -CONFIG_DDB5476=y # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -64,24 +63,23 @@ CONFIG_DDB5476=y # CONFIG_TOSHIBA_RBTX4927 is not set # CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_I8259=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y -CONFIG_DDB5XXX_COMMON=y +CONFIG_MIPS_GT64120=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection # -# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set @@ -92,7 +90,7 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set -CONFIG_CPU_R5432=y +# CONFIG_CPU_R5432 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -100,11 +98,16 @@ CONFIG_CPU_R5432=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_R5432=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # Kernel type @@ -115,11 +118,15 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y # CONFIG_MIPS_MT is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -129,6 +136,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -145,27 +161,31 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y +# CONFIG_SWAP is not set CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set -CONFIG_RELAY=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_EPOLL=y +# CONFIG_EPOLL is not set CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 CONFIG_SLAB=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 @@ -174,14 +194,18 @@ CONFIG_BASE_SMALL=0 # # Loadable module support # -# CONFIG_MODULES is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_KMOD is not set # # Block layer # # CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set # # IO Schedulers @@ -201,7 +225,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y -CONFIG_ISA=y +CONFIG_PCI_LEGACY_PROC=y CONFIG_MMU=y # @@ -212,13 +236,16 @@ CONFIG_MMU=y # # PCI Hotplug Support # -# CONFIG_HOTPLUG_PCI is not set +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_FAKE is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set # # Executable file formats # CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set +CONFIG_BINFMT_MISC=y CONFIG_TRAD_SIGNALS=y # @@ -231,35 +258,33 @@ CONFIG_NET=y # # CONFIG_NETDEBUG is not set CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set +CONFIG_PACKET_MMAP=y CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y +# CONFIG_NET_KEY is not set CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set +CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set +CONFIG_IP_PNP_RARP=y # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +CONFIG_ARPD=y # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_BIC=y # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set # CONFIG_NETFILTER is not set # @@ -301,13 +326,7 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_SOFTMAC=y -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y +# CONFIG_IEEE80211 is not set # # Device Drivers @@ -318,13 +337,12 @@ CONFIG_WIRELESS_EXT=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y +# CONFIG_FW_LOADER is not set # # Connector - unified userspace <-> kernelspace linker # -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y +# CONFIG_CONNECTOR is not set # # Memory Technology Devices (MTD) @@ -339,7 +357,6 @@ CONFIG_PROC_EVENTS=y # # Plug and Play support # -# CONFIG_PNP is not set # # Block devices @@ -352,53 +369,25 @@ CONFIG_PROC_EVENTS=y # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set # # ATA/ATAPI/MFM/RLL support # -CONFIG_IDE=y -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_IDE_ARM is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set +# CONFIG_IDE is not set # # SCSI device support # -CONFIG_RAID_ATTRS=y +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set - -# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set @@ -440,34 +429,48 @@ CONFIG_PHYLIB=y # # MII PHY device drivers # -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_SMC is not set # CONFIG_DM9000 is not set -# CONFIG_NET_VENDOR_RACAL is not set # # Tulip family network device support # # CONFIG_NET_TULIP is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set # CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +CONFIG_E100=y +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_LAN_SAA9730 is not set # # Ethernet (1000 Mbit) @@ -483,6 +486,7 @@ CONFIG_NET_ETHERNET=y # CONFIG_SKGE is not set # CONFIG_SKY2 is not set # CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set @@ -529,46 +533,18 @@ CONFIG_NET_ETHERNET=y # # Input device support # -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +# CONFIG_INPUT is not set # # Hardware I/O ports # -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # # Character devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y +# CONFIG_VT is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -576,9 +552,8 @@ CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 # CONFIG_SERIAL_8250_EXTENDED is not set # @@ -600,8 +575,7 @@ CONFIG_LEGACY_PTY_COUNT=256 # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set +CONFIG_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -637,14 +611,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Hardware Monitoring support # -# CONFIG_HWMON is not set +CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_HWMON_DEBUG_CHIP is not set # # Misc devices # # +# Multimedia Capabilities Port drivers +# + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -657,49 +637,7 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Graphics support # -CONFIG_FB=y -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_MACMODES is not set -CONFIG_FB_FIRMWARE_EDID=y -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_SMIVGX is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_VIRTUAL is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set - -# -# Logo configuration -# -# CONFIG_LOGO is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_FB is not set # # Sound @@ -711,7 +649,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set # @@ -729,19 +666,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_MMC is not set # -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# # InfiniBand support # # CONFIG_INFINIBAND is not set @@ -751,16 +675,9 @@ CONFIG_USB_ARCH_HAS_EHCI=y # # -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# # File systems # -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set @@ -774,7 +691,7 @@ CONFIG_INOTIFY=y CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y +# CONFIG_FUSE_FS is not set # # CD-ROM/DVD Filesystems @@ -795,9 +712,10 @@ CONFIG_FUSE_FS=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_TMPFS is not set +CONFIG_TMPFS=y # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set # CONFIG_CONFIGFS_FS is not set # @@ -821,12 +739,14 @@ CONFIG_RAMFS=y # Network File Systems # CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set # CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set @@ -861,46 +781,19 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_DEBUG_FS is not set -# CONFIG_UNWIND_INFO is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=any" +CONFIG_CMDLINE="console=ttyS0,115200n8" # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set # # Cryptographic options # -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO is not set # # Hardware crypto devices @@ -909,9 +802,7 @@ CONFIG_CRYPTO_CRC32C=y # # Library routines # -# CONFIG_CRC_CCITT is not set +CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC32=y CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index b52d709de962..7ece2c008e9b 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set CONFIG_PMC_YOSEMITE=y @@ -130,6 +128,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT_NONE=y diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c index b8d1f7489f3b..00c62c1c28a3 100644 --- a/arch/mips/ddb5xxx/common/prom.c +++ b/arch/mips/ddb5xxx/common/prom.c @@ -56,13 +56,7 @@ void __init prom_init(void) mips_machgroup = MACH_GROUP_NEC_DDB; -#if defined(CONFIG_DDB5074) - mips_machtype = MACH_NEC_DDB5074; - add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); -#elif defined(CONFIG_DDB5476) - mips_machtype = MACH_NEC_DDB5476; - add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); -#elif defined(CONFIG_DDB5477) +#if defined(CONFIG_DDB5477) ddb5477_runtime_detection(); add_memory_region(0, board_ram_size, BOOT_MEM_RAM); #endif diff --git a/arch/mips/ddb5xxx/ddb5074/Makefile b/arch/mips/ddb5xxx/ddb5074/Makefile deleted file mode 100644 index 304c02107b46..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines -# under Linux. -# - -obj-y += setup.o irq.o nile4_pic.o - -EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c deleted file mode 100644 index 60c087b7738c..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/irq.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> - -#include <asm/i8259.h> -#include <asm/io.h> -#include <asm/irq_cpu.h> -#include <asm/ptrace.h> -#include <asm/nile4.h> -#include <asm/ddb5xxx/ddb5xxx.h> -#include <asm/ddb5xxx/ddb5074.h> - - -static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; - -#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ -#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ -#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ - -#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ -#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ -#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ - -#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ -#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ - -#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ -#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ - -#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ -#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ - - -static void m1543_irq_setup(void) -{ - /* - * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all - * the possible IO sources in the M1543 are in use by us. We will - * use the following mapping: - * - * IRQ1 - keyboard (default set by M1543) - * IRQ3 - reserved for UART B (default set by M1543) (note that - * the schematics for the DDB Vrc-5074 board seem to - * indicate that IRQ3 is connected to the DS1386 - * watchdog timer interrupt output so we might have - * a conflict) - * IRQ4 - reserved for UART A (default set by M1543) - * IRQ5 - parallel (default set by M1543) - * IRQ8 - DS1386 time of day (RTC) interrupt - * IRQ12 - mouse - */ - - /* - * Assing mouse interrupt to IRQ12 - */ - - /* Enter configuration mode */ - outb(0x51, M1543_PNP_CONFIG); - outb(0x23, M1543_PNP_CONFIG); - - /* Select logical device 7 (Keyboard) */ - outb(0x07, M1543_PNP_INDEX); - outb(0x07, M1543_PNP_DATA); - - /* Select IRQ12 */ - outb(0x72, M1543_PNP_INDEX); - outb(0x0c, M1543_PNP_DATA); - - outb(0x30, M1543_PNP_INDEX); - printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA)); - - outb(0x70, M1543_PNP_INDEX); - printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA)); - - /* Leave configration mode */ - outb(0xbb, M1543_PNP_CONFIG); - - -} - -static void ddb_local0_irqdispatch(struct pt_regs *regs) -{ - u32 mask; - int nile4_irq; - - mask = nile4_get_irq_stat(0); - - /* Handle the timer interrupt first */ -#if 0 - if (mask & (1 << NILE4_INT_GPT)) { - do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs); - mask &= ~(1 << NILE4_INT_GPT); - } -#endif - for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) - if (mask & 1) { - if (nile4_irq == NILE4_INT_INTE) { - int i8259_irq; - - nile4_clear_irq(NILE4_INT_INTE); - i8259_irq = nile4_i8259_iack(); - do_IRQ(i8259_irq, regs); - } else - do_IRQ(nile4_to_irq(nile4_irq), regs); - - } -} - -static void ddb_local1_irqdispatch(void) -{ - printk("ddb_local1_irqdispatch called\n"); -} - -static void ddb_buserror_irq(void) -{ - printk("ddb_buserror_irq called\n"); -} - -static void ddb_8254timer_irq(void) -{ - printk("ddb_8254timer_irq called\n"); -} - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & CAUSEF_IP2) - ddb_local0_irqdispatch(regs); - else if (pending & CAUSEF_IP3) - ddb_local1_irqdispatch(); - else if (pending & CAUSEF_IP6) - ddb_buserror_irq(); - else if (pending & (CAUSEF_IP4 | CAUSEF_IP5)) - ddb_8254timer_irq(); -} - -void __init arch_init_irq(void) -{ - /* setup cascade interrupts */ - setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade); - - nile4_irq_setup(NILE4_IRQ_BASE); - m1543_irq_setup(); - init_i8259_irqs(); - - - printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE); - - mips_cpu_irq_init(CPU_IRQ_BASE); - - printk("enabling 8259 cascade\n"); - - ddb5074_led_hex(0); - - /* Enable the interrupt cascade */ - nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE); -} diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c deleted file mode 100644 index 8743ffce8653..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * arch/mips/ddb5476/nile4.c -- - * low-level PIC code for NEC Vrc-5476 (Nile 4) - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - */ -#include <linux/config.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> - -#include <asm/addrspace.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -static int irq_base; - -/* - * Interrupt Programming - */ -void nile4_map_irq(int nile4_irq, int cpu_irq) -{ - u32 offset, t; - - offset = DDB_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = ddb_in32(offset); - t &= ~(7 << (nile4_irq * 4)); - t |= cpu_irq << (nile4_irq * 4); - ddb_out32(offset, t); -} - -void nile4_map_irq_all(int cpu_irq) -{ - u32 all, t; - - all = cpu_irq; - all |= all << 4; - all |= all << 8; - all |= all << 16; - t = ddb_in32(DDB_INTCTRL); - t &= 0x88888888; - t |= all; - ddb_out32(DDB_INTCTRL, t); - t = ddb_in32(DDB_INTCTRL + 4); - t &= 0x88888888; - t |= all; - ddb_out32(DDB_INTCTRL + 4, t); -} - -void nile4_enable_irq(unsigned int nile4_irq) -{ - u32 offset, t; - - nile4_irq-=irq_base; - - ddb5074_led_hex(8); - - offset = DDB_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - ddb5074_led_hex(9); - t = ddb_in32(offset); - ddb5074_led_hex(0xa); - t |= 8 << (nile4_irq * 4); - ddb_out32(offset, t); - ddb5074_led_hex(0xb); -} - -void nile4_disable_irq(unsigned int nile4_irq) -{ - u32 offset, t; - - nile4_irq-=irq_base; - - offset = DDB_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = ddb_in32(offset); - t &= ~(8 << (nile4_irq * 4)); - ddb_out32(offset, t); -} - -void nile4_disable_irq_all(void) -{ - ddb_out32(DDB_INTCTRL, 0); - ddb_out32(DDB_INTCTRL + 4, 0); -} - -u16 nile4_get_irq_stat(int cpu_irq) -{ - return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2); -} - -void nile4_enable_irq_output(int cpu_irq) -{ - u32 t; - - t = ddb_in32(DDB_INTSTAT1 + 4); - t |= 1 << (16 + cpu_irq); - ddb_out32(DDB_INTSTAT1, t); -} - -void nile4_disable_irq_output(int cpu_irq) -{ - u32 t; - - t = ddb_in32(DDB_INTSTAT1 + 4); - t &= ~(1 << (16 + cpu_irq)); - ddb_out32(DDB_INTSTAT1, t); -} - -void nile4_set_pci_irq_polarity(int pci_irq, int high) -{ - u32 t; - - t = ddb_in32(DDB_INTPPES); - if (high) - t &= ~(1 << (pci_irq * 2)); - else - t |= 1 << (pci_irq * 2); - ddb_out32(DDB_INTPPES, t); -} - -void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) -{ - u32 t; - - t = ddb_in32(DDB_INTPPES); - if (level) - t |= 2 << (pci_irq * 2); - else - t &= ~(2 << (pci_irq * 2)); - ddb_out32(DDB_INTPPES, t); -} - -void nile4_clear_irq(int nile4_irq) -{ - nile4_irq-=irq_base; - ddb_out32(DDB_INTCLR, 1 << nile4_irq); -} - -void nile4_clear_irq_mask(u32 mask) -{ - ddb_out32(DDB_INTCLR, mask); -} - -u8 nile4_i8259_iack(void) -{ - u8 irq; - u32 reg; - - /* Set window 0 for interrupt acknowledge */ - reg = ddb_in32(DDB_PCIINIT0); - - ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); - irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); - /* restore window 0 for PCI I/O space */ - // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); - ddb_out32(DDB_PCIINIT0, reg); - - /* i8269.c set the base vector to be 0x0 */ - return irq ; -} - -static unsigned int nile4_irq_startup(unsigned int irq) { - - nile4_enable_irq(irq); - return 0; - -} - -static void nile4_ack_irq(unsigned int irq) { - - ddb5074_led_hex(4); - - nile4_clear_irq(irq); - ddb5074_led_hex(2); - nile4_disable_irq(irq); - - ddb5074_led_hex(0); -} - -static void nile4_irq_end(unsigned int irq) { - - ddb5074_led_hex(3); - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - ddb5074_led_hex(5); - nile4_enable_irq(irq); - ddb5074_led_hex(7); - } - - ddb5074_led_hex(1); -} - -#define nile4_irq_shutdown nile4_disable_irq - -static hw_irq_controller nile4_irq_controller = { - .typename = "nile4", - .startup = nile4_irq_startup, - .shutdown = nile4_irq_shutdown, - .enable = nile4_enable_irq, - .disable = nile4_disable_irq, - .ack = nile4_ack_irq, - .end = nile4_irq_end, -}; - -void nile4_irq_setup(u32 base) { - - int i; - - irq_base=base; - - /* Map all interrupts to CPU int #0 */ - nile4_map_irq_all(0); - - /* PCI INTA#-E# must be level triggered */ - nile4_set_pci_irq_level_or_edge(0, 1); - nile4_set_pci_irq_level_or_edge(1, 1); - nile4_set_pci_irq_level_or_edge(2, 1); - nile4_set_pci_irq_level_or_edge(3, 1); - nile4_set_pci_irq_level_or_edge(4, 1); - - /* PCI INTA#-D# must be active low, INTE# must be active high */ - nile4_set_pci_irq_polarity(0, 0); - nile4_set_pci_irq_polarity(1, 0); - nile4_set_pci_irq_polarity(2, 0); - nile4_set_pci_irq_polarity(3, 0); - nile4_set_pci_irq_polarity(4, 1); - - - for (i = 0; i < 16; i++) { - nile4_clear_irq(i); - nile4_disable_irq(i); - } - - /* Enable CPU int #0 */ - nile4_enable_irq_output(0); - - for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &nile4_irq_controller; - } -} - -#if defined(CONFIG_RUNTIME_DEBUG) -void nile4_dump_irq_status(void) -{ - printk(KERN_DEBUG " - CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), - (void *) ddb_in32(DDB_CPUSTAT)); - printk(KERN_DEBUG " - INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), - (void *) ddb_in32(DDB_INTCTRL)); - printk(KERN_DEBUG - "INTSTAT0 = %p:%p\n", - (void *) ddb_in32(DDB_INTSTAT0 + 4), - (void *) ddb_in32(DDB_INTSTAT0)); - printk(KERN_DEBUG - "INTSTAT1 = %p:%p\n", - (void *) ddb_in32(DDB_INTSTAT1 + 4), - (void *) ddb_in32(DDB_INTSTAT1)); - printk(KERN_DEBUG - "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), - (void *) ddb_in32(DDB_INTCLR)); - printk(KERN_DEBUG - "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), - (void *) ddb_in32(DDB_INTPPES)); -} - -#endif diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c deleted file mode 100644 index 91456b068c2e..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/setup.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include <linux/init.h> -#include <linux/kbd_ll.h> -#include <linux/kernel.h> -#include <linux/kdev_t.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/pci.h> -#include <linux/ide.h> -#include <linux/ioport.h> -#include <linux/irq.h> -#include <linux/pm.h> - -#include <asm/addrspace.h> -#include <asm/bcache.h> -#include <asm/irq.h> -#include <asm/reboot.h> -#include <asm/gdb-stub.h> -#include <asm/time.h> -#include <asm/nile4.h> -#include <asm/ddb5xxx/ddb5074.h> -#include <asm/ddb5xxx/ddb5xxx.h> - -static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; - -static void ddb_machine_restart(char *command) -{ - u32 t; - - /* PCI cold reset */ - t = nile4_in32(NILE4_PCICTRL + 4); - t |= 0x40000000; - nile4_out32(NILE4_PCICTRL + 4, t); - /* CPU cold reset */ - t = nile4_in32(NILE4_CPUSTAT); - t |= 1; - nile4_out32(NILE4_CPUSTAT, t); - /* Call the PROM */ - back_to_prom(); -} - -static void ddb_machine_halt(void) -{ - printk("DDB Vrc-5074 halted.\n"); - do { - } while (1); -} - -static void ddb_machine_power_off(void) -{ - printk("DDB Vrc-5074 halted. Please turn off the power.\n"); - do { - } while (1); -} - -extern void rtc_ds1386_init(unsigned long base); - -extern void (*board_timer_setup) (struct irqaction * irq); - -static void __init ddb_timer_init(struct irqaction *irq) -{ - /* set the clock to 1 Hz */ - nile4_out32(NILE4_T2CTRL, 1000000); - /* enable the General-Purpose Timer */ - nile4_out32(NILE4_T2CTRL + 4, 0x00000001); - /* reset timer */ - nile4_out32(NILE4_T2CNTR, 0); - /* enable interrupt */ - setup_irq(nile4_to_irq(NILE4_INT_GPT), irq); - nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT)); - change_c0_status(ST0_IM, - IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); - -} - -static void __init ddb_time_init(void) -{ - /* we have ds1396 RTC chip */ - rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE)); -} - - - -void __init plat_setup(void) -{ - set_io_port_base(NILE4_PCI_IO_BASE); - isa_slot_offset = NILE4_PCI_MEM_BASE; - board_timer_setup = ddb_timer_init; - board_time_init = ddb_time_init; - - - _machine_restart = ddb_machine_restart; - _machine_halt = ddb_machine_halt; - pm_power_off = ddb_machine_power_off; - - ddb_out32(DDB_BAR0, 0); - - ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10); - ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10); - - /* Reboot on panic */ - panic_timeout = 180; -} - -#define USE_NILE4_SERIAL 0 - -#if USE_NILE4_SERIAL -#define ns16550_in(reg) nile4_in8((reg)*8) -#define ns16550_out(reg, val) nile4_out8((reg)*8, (val)) -#else -#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8) -static inline u8 ns16550_in(u32 reg) -{ - return *(volatile u8 *) (NS16550_BASE + reg); -} - -static inline void ns16550_out(u32 reg, u8 val) -{ - *(volatile u8 *) (NS16550_BASE + reg) = val; -} -#endif - -#define NS16550_RBR 0 -#define NS16550_THR 0 -#define NS16550_DLL 0 -#define NS16550_IER 1 -#define NS16550_DLM 1 -#define NS16550_FCR 2 -#define NS16550_IIR 2 -#define NS16550_LCR 3 -#define NS16550_MCR 4 -#define NS16550_LSR 5 -#define NS16550_MSR 6 -#define NS16550_SCR 7 - -#define NS16550_LSR_DR 0x01 /* Data ready */ -#define NS16550_LSR_OE 0x02 /* Overrun */ -#define NS16550_LSR_PE 0x04 /* Parity error */ -#define NS16550_LSR_FE 0x08 /* Framing error */ -#define NS16550_LSR_BI 0x10 /* Break */ -#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */ -#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */ -#define NS16550_LSR_ERR 0x80 /* Error */ - - -void _serinit(void) -{ -#if USE_NILE4_SERIAL - ns16550_out(NS16550_LCR, 0x80); - ns16550_out(NS16550_DLM, 0x00); - ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */ - ns16550_out(NS16550_LCR, 0x00); - ns16550_out(NS16550_LCR, 0x03); - ns16550_out(NS16550_FCR, 0x47); -#else - /* done by PMON */ -#endif -} - -void _putc(char c) -{ - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); - ns16550_out(NS16550_THR, c); - if (c == '\n') { - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); - ns16550_out(NS16550_THR, '\r'); - } -} - -void _puts(const char *s) -{ - char c; - while ((c = *s++)) - _putc(c); -} - -char _getc(void) -{ - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR)); - return ns16550_in(NS16550_RBR); -} - -int _testc(void) -{ - return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0; -} - - -/* - * Hexadecimal 7-segment LED - */ -void ddb5074_led_hex(int hex) -{ - outb(hex, 0x80); -} - - -/* - * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543 - */ -struct pci_dev *pci_pmu = NULL; - -void ddb5074_led_d2(int on) -{ - u8 t; - - if (pci_pmu) { - pci_read_config_byte(pci_pmu, 0x7e, &t); - if (on) - t &= 0x7f; - else - t |= 0x80; - pci_write_config_byte(pci_pmu, 0x7e, t); - } -} - -void ddb5074_led_d3(int on) -{ - u8 t; - - if (pci_pmu) { - pci_read_config_byte(pci_pmu, 0x7e, &t); - if (on) - t &= 0xbf; - else - t |= 0x40; - pci_write_config_byte(pci_pmu, 0x7e, t); - } -} diff --git a/arch/mips/ddb5xxx/ddb5476/Makefile b/arch/mips/ddb5xxx/ddb5476/Makefile deleted file mode 100644 index ab0312cb47b4..000000000000 --- a/arch/mips/ddb5xxx/ddb5476/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines -# under Linux. -# - -obj-y += setup.o irq.o nile4_pic.o vrc5476_irq.o -obj-$(CONFIG_KGDB) += dbg_io.o - -EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/ddb5xxx/ddb5476/dbg_io.c b/arch/mips/ddb5xxx/ddb5476/dbg_io.c deleted file mode 100644 index f2296a999953..000000000000 --- a/arch/mips/ddb5xxx/ddb5476/dbg_io.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * kgdb io functions for DDB5476. We use the second serial port. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* ======================= CONFIG ======================== */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xa60002f8 -#define MAX_BAUD 115200 - -/* distance in bytes between two serial registers */ -#define REG_OFFSET 1 - -/* - * 0 - kgdb does serial init - * 1 - kgdb skip serial init - */ -static int remoteDebugInitialized = 0; - -/* - * the default baud rate *if* kgdb does serial init - */ -#define BAUD_DEFAULT UART16550_BAUD_38400 - -/* ======================= END OF CONFIG ======================== */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up baud rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff --git a/arch/mips/ddb5xxx/ddb5476/irq.c b/arch/mips/ddb5xxx/ddb5476/irq.c deleted file mode 100644 index 7583a1f30711..000000000000 --- a/arch/mips/ddb5xxx/ddb5476/irq.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * Re-write the whole thing to use new irq.c file. - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - */ -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/types.h> -#include <linux/interrupt.h> - -#include <asm/i8259.h> -#include <asm/io.h> -#include <asm/ptrace.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ -#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ -#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ - -#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ -#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ -#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ - -#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ -#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ - -#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ -#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ - -#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ -#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ - -static void m1543_irq_setup(void) -{ - /* - * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all - * the possible IO sources in the M1543 are in use by us. We will - * use the following mapping: - * - * IRQ1 - keyboard (default set by M1543) - * IRQ3 - reserved for UART B (default set by M1543) (note that - * the schematics for the DDB Vrc-5476 board seem to - * indicate that IRQ3 is connected to the DS1386 - * watchdog timer interrupt output so we might have - * a conflict) - * IRQ4 - reserved for UART A (default set by M1543) - * IRQ5 - parallel (default set by M1543) - * IRQ8 - DS1386 time of day (RTC) interrupt - * IRQ9 - USB (hardwired in ddb_setup) - * IRQ10 - PMU (hardwired in ddb_setup) - * IRQ12 - mouse - * IRQ14,15 - IDE controller (need to be confirmed, jsun) - */ - - /* - * Assing mouse interrupt to IRQ12 - */ - - /* Enter configuration mode */ - outb(0x51, M1543_PNP_CONFIG); - outb(0x23, M1543_PNP_CONFIG); - - /* Select logical device 7 (Keyboard) */ - outb(0x07, M1543_PNP_INDEX); - outb(0x07, M1543_PNP_DATA); - - /* Select IRQ12 */ - outb(0x72, M1543_PNP_INDEX); - outb(0x0c, M1543_PNP_DATA); - - /* Leave configration mode */ - outb(0xbb, M1543_PNP_CONFIG); -} - -static void nile4_irq_setup(void) -{ - int i; - - /* Map all interrupts to CPU int #0 (IP2) */ - nile4_map_irq_all(0); - - /* PCI INTA#-E# must be level triggered */ - nile4_set_pci_irq_level_or_edge(0, 1); - nile4_set_pci_irq_level_or_edge(1, 1); - nile4_set_pci_irq_level_or_edge(2, 1); - nile4_set_pci_irq_level_or_edge(3, 1); - - /* PCI INTA#, B#, D# must be active low, INTC# must be active high */ - nile4_set_pci_irq_polarity(0, 0); - nile4_set_pci_irq_polarity(1, 0); - nile4_set_pci_irq_polarity(2, 1); - nile4_set_pci_irq_polarity(3, 0); - - for (i = 0; i < 16; i++) - nile4_clear_irq(i); - - /* Enable CPU int #0 */ - nile4_enable_irq_output(0); - - /* memory resource acquire in ddb_setup */ -} - -static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; -static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL }; - -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); -extern void mips_cpu_irq_init(u32 irq_base); -extern void vrc5476_irq_init(u32 irq_base); - -extern void vrc5476_irq_dispatch(struct pt_regs *regs); - -asmlinkage void plat_irq_dispatch(struct pt_regs *regs) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP7) - do_IRQ(CPU_IRQ_BASE + 7, regs); - else if (pending & STATUSF_IP2) - vrc5476_irq_dispatch(regs); - else if (pending & STATUSF_IP3) - do_IRQ(CPU_IRQ_BASE + 3, regs); - else if (pending & STATUSF_IP4) - do_IRQ(CPU_IRQ_BASE + 4, regs); - else if (pending & STATUSF_IP5) - do_IRQ(CPU_IRQ_BASE + 5, regs); - else if (pending & STATUSF_IP6) - do_IRQ(CPU_IRQ_BASE + 6, regs); - else if (pending & STATUSF_IP0) - do_IRQ(CPU_IRQ_BASE, regs); - else if (pending & STATUSF_IP1) - do_IRQ(CPU_IRQ_BASE + 1, regs); - - vrc5476_irq_dispatch(regs); -} - -void __init arch_init_irq(void) -{ - /* hardware initialization */ - nile4_irq_setup(); - m1543_irq_setup(); - - /* controller setup */ - init_i8259_irqs(); - vrc5476_irq_init(VRC5476_IRQ_BASE); - mips_cpu_irq_init(CPU_IRQ_BASE); - - /* setup cascade interrupts */ - setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade); - - /* setup error interrupts for debugging */ - setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error); - setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error); - setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error); - setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error); - setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error); - setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error); -} diff --git a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c b/arch/mips/ddb5xxx/ddb5476/nile4_pic.c deleted file mode 100644 index e930cee7944f..000000000000 --- a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * arch/mips/ddb5476/nile4.c -- - * low-level PIC code for NEC Vrc-5476 (Nile 4) - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - */ -#include <linux/config.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include <asm/addrspace.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - - -/* - * Interrupt Programming - */ -void nile4_map_irq(int nile4_irq, int cpu_irq) -{ - u32 offset, t; - - offset = DDB_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = ddb_in32(offset); - t &= ~(7 << (nile4_irq * 4)); - t |= cpu_irq << (nile4_irq * 4); - ddb_out32(offset, t); -} - -void nile4_map_irq_all(int cpu_irq) -{ - u32 all, t; - - all = cpu_irq; - all |= all << 4; - all |= all << 8; - all |= all << 16; - t = ddb_in32(DDB_INTCTRL); - t &= 0x88888888; - t |= all; - ddb_out32(DDB_INTCTRL, t); - t = ddb_in32(DDB_INTCTRL + 4); - t &= 0x88888888; - t |= all; - ddb_out32(DDB_INTCTRL + 4, t); -} - -void nile4_enable_irq(int nile4_irq) -{ - u32 offset, t; - - offset = DDB_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = ddb_in32(offset); - t |= 8 << (nile4_irq * 4); - ddb_out32(offset, t); -} - -void nile4_disable_irq(int nile4_irq) -{ - u32 offset, t; - - offset = DDB_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = ddb_in32(offset); - t &= ~(8 << (nile4_irq * 4)); - ddb_out32(offset, t); -} - -void nile4_disable_irq_all(void) -{ - ddb_out32(DDB_INTCTRL, 0); - ddb_out32(DDB_INTCTRL + 4, 0); -} - -u16 nile4_get_irq_stat(int cpu_irq) -{ - return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2); -} - -void nile4_enable_irq_output(int cpu_irq) -{ - u32 t; - - t = ddb_in32(DDB_INTSTAT1 + 4); - t |= 1 << (16 + cpu_irq); - ddb_out32(DDB_INTSTAT1, t); -} - -void nile4_disable_irq_output(int cpu_irq) -{ - u32 t; - - t = ddb_in32(DDB_INTSTAT1 + 4); - t &= ~(1 << (16 + cpu_irq)); - ddb_out32(DDB_INTSTAT1, t); -} - -void nile4_set_pci_irq_polarity(int pci_irq, int high) -{ - u32 t; - - t = ddb_in32(DDB_INTPPES); - if (high) - t &= ~(1 << (pci_irq * 2)); - else - t |= 1 << (pci_irq * 2); - ddb_out32(DDB_INTPPES, t); -} - -void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) -{ - u32 t; - - t = ddb_in32(DDB_INTPPES); - if (level) - t |= 2 << (pci_irq * 2); - else - t &= ~(2 << (pci_irq * 2)); - ddb_out32(DDB_INTPPES, t); -} - -void nile4_clear_irq(int nile4_irq) -{ - ddb_out32(DDB_INTCLR, 1 << nile4_irq); -} - -void nile4_clear_irq_mask(u32 mask) -{ - ddb_out32(DDB_INTCLR, mask); -} - -u8 nile4_i8259_iack(void) -{ - u8 irq; - u32 reg; - - /* Set window 0 for interrupt acknowledge */ - reg = ddb_in32(DDB_PCIINIT0); - - ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); - irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); - /* restore window 0 for PCI I/O space */ - // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); - ddb_out32(DDB_PCIINIT0, reg); - - /* i8269.c set the base vector to be 0x0 */ - return irq + I8259_IRQ_BASE; -} - -#if defined(CONFIG_RUNTIME_DEBUG) -void nile4_dump_irq_status(void) -{ - printk(KERN_DEBUG " - CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), - (void *) ddb_in32(DDB_CPUSTAT)); - printk(KERN_DEBUG " - INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), - (void *) ddb_in32(DDB_INTCTRL)); - printk(KERN_DEBUG - "INTSTAT0 = %p:%p\n", - (void *) ddb_in32(DDB_INTSTAT0 + 4), - (void *) ddb_in32(DDB_INTSTAT0)); - printk(KERN_DEBUG - "INTSTAT1 = %p:%p\n", - (void *) ddb_in32(DDB_INTSTAT1 + 4), - (void *) ddb_in32(DDB_INTSTAT1)); - printk(KERN_DEBUG - "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), - (void *) ddb_in32(DDB_INTCLR)); - printk(KERN_DEBUG - "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), - (void *) ddb_in32(DDB_INTPPES)); -} -#endif diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c deleted file mode 100644 index c902adef5942..000000000000 --- a/arch/mips/ddb5xxx/ddb5476/setup.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include <linux/init.h> -#include <linux/kbd_ll.h> -#include <linux/kernel.h> -#include <linux/kdev_t.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/pci.h> -#include <linux/pm.h> - -#include <asm/addrspace.h> -#include <asm/bcache.h> -#include <asm/irq.h> -#include <asm/reboot.h> -#include <asm/gdb-stub.h> -#include <asm/time.h> -#include <asm/debug.h> -#include <asm/traps.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ - -#ifdef USE_CPU_COUNTER_TIMER - -#define CPU_COUNTER_FREQUENCY 83000000 -#else -/* otherwise we use general purpose timer */ -#define TIMER_FREQUENCY 83000000 -#define TIMER_BASE DDB_T2CTRL -#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT) -#endif - -static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; - -static void ddb_machine_restart(char *command) -{ - u32 t; - - /* PCI cold reset */ - t = ddb_in32(DDB_PCICTRL + 4); - t |= 0x40000000; - ddb_out32(DDB_PCICTRL + 4, t); - /* CPU cold reset */ - t = ddb_in32(DDB_CPUSTAT); - t |= 1; - ddb_out32(DDB_CPUSTAT, t); - /* Call the PROM */ - back_to_prom(); -} - -static void ddb_machine_halt(void) -{ - printk(KERN_NOTICE "DDB Vrc-5476 halted.\n"); - while (1); -} - -static void ddb_machine_power_off(void) -{ - printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n"); - while (1); -} - -extern void rtc_ds1386_init(unsigned long base); - -static void __init ddb_time_init(void) -{ -#if defined(USE_CPU_COUNTER_TIMER) - mips_hpt_frequency = CPU_COUNTER_FREQUENCY; -#endif - - /* we have ds1396 RTC chip */ - rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE)); -} - - -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); -static void __init ddb_timer_setup(struct irqaction *irq) -{ -#if defined(USE_CPU_COUNTER_TIMER) - - unsigned int count; - - /* we are using the cpu counter for timer interrupts */ - setup_irq(CPU_IRQ_BASE + 7, irq); - - /* to generate the first timer interrupt */ - count = read_c0_count(); - write_c0_compare(count + 1000); - -#else - - ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ); - ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */ - setup_irq(TIMER_IRQ, irq); -#endif -} - -static struct { - struct resource dma1; - struct resource timer; - struct resource rtc; - struct resource dma_page_reg; - struct resource dma2; -} ddb5476_ioport = { - { - "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, { - "timer", 0x40, 0x5f, IORESOURCE_BUSY}, { - "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, { - "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, { - "dma2", 0xc0, 0xdf, IORESOURCE_BUSY} -}; - -static struct { - struct resource nile4; -} ddb5476_iomem = { - { "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY} -}; - - -static void ddb5476_board_init(void); - -void __init plat_setup(void) -{ - set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); - - board_time_init = ddb_time_init; - board_timer_setup = ddb_timer_setup; - - _machine_restart = ddb_machine_restart; - _machine_halt = ddb_machine_halt; - pm_power_off = ddb_machine_power_off; - - /* request io port/mem resources */ - if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) || - request_resource(&ioport_resource, &ddb5476_ioport.timer) || - request_resource(&ioport_resource, &ddb5476_ioport.rtc) || - request_resource(&ioport_resource, - &ddb5476_ioport.dma_page_reg) - || request_resource(&ioport_resource, &ddb5476_ioport.dma2) - || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) { - printk - ("ddb_setup - requesting oo port resources failed.\n"); - for (;;); - } - - /* Reboot on panic */ - panic_timeout = 180; - - /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */ - /* *(long*)0xbfa00218 = 0x8; */ - - /* board initialization stuff */ - ddb5476_board_init(); -} - -/* - * We don't trust bios. We essentially does hardware re-initialization - * as complete as possible, as far as we know we can safely do. - */ -static void ddb5476_board_init(void) -{ - /* ----------- setup PDARs ------------ */ - /* check SDRAM0, whether we are on MEM bus does not matter */ - db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) == - ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1)); - - /* SDRAM1 should be turned off. What is this for anyway ? */ - db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); - - /* flash 1&2, DDB status, DDB control */ - ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0); - ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0); - ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0); - ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0); - - /* shut off other pdar so they don't accidentally get into the way */ - ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0); - ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0); - ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0); - - /* verify VRC5477 base addr */ - /* don't care about some details */ - db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) == - ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0)); - - /* verify BOOT ROM addr */ - /* don't care about some details */ - db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) == - ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); - - /* setup PCI windows - window1 for MEM/config, window0 for IO */ - ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1); - ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); - - ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); - ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32); - - /* ----------- setup PDARs ------------ */ - /* this is problematic - it will reset Aladin which cause we loose - * serial port, and we don't know how to set up Aladin chip again. - */ - // ddb_pci_reset_bus(); - - ddb_out32(DDB_BAR0, 0x00000008); - - ddb_out32(DDB_BARC, 0xffffffff); - ddb_out32(DDB_BARB, 0xffffffff); - ddb_out32(DDB_BAR1, 0xffffffff); - ddb_out32(DDB_BAR2, 0xffffffff); - ddb_out32(DDB_BAR3, 0xffffffff); - ddb_out32(DDB_BAR4, 0xffffffff); - ddb_out32(DDB_BAR5, 0xffffffff); - ddb_out32(DDB_BAR6, 0xffffffff); - ddb_out32(DDB_BAR7, 0xffffffff); - ddb_out32(DDB_BAR8, 0xffffffff); - - /* ----------- switch PCI1 to PCI CONFIG space ------------ */ - ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1); - ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32); - - /* ----- M1543 PCI setup ------ */ - - /* we know M1543 PCI-ISA controller is at addr:18 */ - /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */ - *(volatile unsigned char *) 0xa8040072 &= 0xf0; - *(volatile unsigned char *) 0xa8040072 |= 0xa; - - /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001) - * no IOCHRDY signal, (bit 7 - 1) - * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1) - * Make USB Master INTAJ level to edge conversion (bit 4 - 1) - */ - *(unsigned char *) 0xa8040074 = 0xd1; - - /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011) - * SCI routing to IRQ 13 disabled (bit 7 - 1) - * SCI interrupt level to edge conversion bypassed (bit 4 - 0) - */ - *(unsigned char *) 0xa8040076 = 0x83; - - /* setup IDE controller - * enable IDE controller (bit 6 - 1) - * IDE IDSEL to be addr:24 (bit 4:5 - 11) - * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) - * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0) - * primary IRQ is 14, secondary is 15 (bit 1:0 - 01 - */ - // *(unsigned char*)0xa8040058 = 0x71; - // *(unsigned char*)0xa8040058 = 0x79; - // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state - *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state - -#if 0 - /* this is not necessary if M5229 does not use SIRQ */ - *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14 - *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14 -#endif - - /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */ - /* M5229 IDSEL is addr:24; see above setting */ - *(unsigned char *) 0xa9000050 |= 0x1; - - /* enable bus master (bit 2) and IO decoding (bit 0) */ - *(unsigned char *) 0xa9000004 |= 0x5; - - /* enable native, copied from arch/ppc/k2boot/head.S */ - /* TODO - need volatile, need to be portable */ - *(unsigned char *) 0xa9000009 = 0xff; - - /* ----- end of M1543 PCI setup ------ */ - - /* ----- reset on-board ether chip ------ */ - *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */ - *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */ - - /* send reset command */ - *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */ - - /* disable ether chip */ - *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */ - - /* put it into sleep */ - *((volatile u32 *) 0xa8020040) = 0x80000000; - - /* ----- end of reset on-board ether chip ------ */ - - /* ----------- switch PCI1 back to PCI MEM space ------------ */ - ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); - ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32); -} diff --git a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c deleted file mode 100644 index a3c5e7b18018..000000000000 --- a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * The irq controller for vrc5476. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/types.h> -#include <linux/ptrace.h> - -#include <asm/system.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -static int irq_base; - -static void vrc5476_irq_enable(uint irq) -{ - nile4_enable_irq(irq - irq_base); -} - -static void vrc5476_irq_disable(uint irq) -{ - nile4_disable_irq(irq - irq_base); -} - -static unsigned int vrc5476_irq_startup(uint irq) -{ - nile4_enable_irq(irq - irq_base); - return 0; -} - -#define vrc5476_irq_shutdown vrc5476_irq_disable - -static void vrc5476_irq_ack(uint irq) -{ - nile4_clear_irq(irq - irq_base); - nile4_disable_irq(irq - irq_base); -} - -static void vrc5476_irq_end(uint irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - vrc5476_irq_enable(irq); -} - -static hw_irq_controller vrc5476_irq_controller = { - .typename = "vrc5476", - .startup = vrc5476_irq_startup, - .shutdown = vrc5476_irq_shutdown, - .enable = vrc5476_irq_enable, - .disable = vrc5476_irq_disable, - .ack = vrc5476_irq_ack, - .end = vrc5476_irq_end -}; - -void __init -vrc5476_irq_init(u32 base) -{ - u32 i; - - irq_base = base; - for (i= base; i< base + NUM_VRC5476_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &vrc5476_irq_controller; - } -} - - -void -vrc5476_irq_dispatch(struct pt_regs *regs) -{ - u32 mask; - int nile4_irq; - - mask = nile4_get_irq_stat(0); - - /* quick check for possible time interrupt */ - if (mask & (1 << VRC5476_IRQ_GPT)) { - do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs); - return; - } - - /* check for i8259 interrupts */ - if (mask & (1 << VRC5476_I8259_CASCADE)) { - int i8259_irq = nile4_i8259_iack(); - do_IRQ(I8259_IRQ_BASE + i8259_irq, regs); - return; - } - - /* regular nile4 interrupts (we should not really have any */ - for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) { - if (mask & 1) { - do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs); - return; - } - } - spurious_interrupt(regs); -} diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c index 2f566034cc44..93167ecdb424 100644 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ b/arch/mips/ddb5xxx/ddb5477/setup.c @@ -171,7 +171,7 @@ static void ddb5477_board_init(void); extern struct pci_controller ddb5477_ext_controller; extern struct pci_controller ddb5477_io_controller; -void __init plat_setup(void) +void __init plat_mem_setup(void) { /* initialize board - we don't trust the loader */ ddb5477_board_init(); diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index ad5d436d80c1..9c707b9ceb65 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -147,7 +147,7 @@ static void __init dec_be_init(void) extern void dec_time_init(void); extern void dec_timer_setup(struct irqaction *); -void __init plat_setup(void) +void __init plat_mem_setup(void) { board_be_init = dec_be_init; board_time_init = dec_time_init; diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index 74cb055d4bf6..76e4d09ff4d2 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -181,7 +181,7 @@ void __init dec_time_init(void) } /* Set up the rate of periodic DS1287 interrupts. */ - CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A); + CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A); } EXPORT_SYMBOL(do_settimeofday); diff --git a/arch/mips/defconfig b/arch/mips/defconfig index 607e2985ffe3..879ba1ad99ca 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -41,8 +41,6 @@ CONFIG_MIPS=y # CONFIG_MIPS_XXS1500 is not set # CONFIG_PNX8550_V2PCI is not set # CONFIG_PNX8550_JBS is not set -# CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set @@ -136,6 +134,15 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set diff --git a/arch/mips/emma2rh/common/Makefile b/arch/mips/emma2rh/common/Makefile new file mode 100644 index 000000000000..859121b3867d --- /dev/null +++ b/arch/mips/emma2rh/common/Makefile @@ -0,0 +1,13 @@ +# +# arch/mips/emma2rh/common/Makefile +# Makefile for the common code of NEC EMMA2RH based board. +# +# Copyright (C) NEC Electronics Corporation 2005-2006 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# + +obj-$(CONFIG_MARKEINS) += irq.o irq_emma2rh.o prom.o diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c new file mode 100644 index 000000000000..b075281e50e9 --- /dev/null +++ b/arch/mips/emma2rh/common/irq.c @@ -0,0 +1,108 @@ +/* + * arch/mips/emma2rh/common/irq.c + * This file is common irq dispatcher. + * + * Copyright (C) NEC Electronics Corporation 2005-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/types.h> + +#include <asm/i8259.h> +#include <asm/system.h> +#include <asm/mipsregs.h> +#include <asm/debug.h> +#include <asm/addrspace.h> +#include <asm/bootinfo.h> + +#include <asm/emma2rh/emma2rh.h> + +/* + * the first level int-handler will jump here if it is a emma2rh irq + */ +asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs) +{ + u32 intStatus; + u32 bitmask; + u32 i; + + intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) + & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); + +#ifdef EMMA2RH_SW_CASCADE + if (intStatus & + (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + u32 swIntStatus; + swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) + & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); + for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { + if (swIntStatus & bitmask) { + do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs); + return; + } + } + } +#endif + + for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { + if (intStatus & bitmask) { + do_IRQ(EMMA2RH_IRQ_BASE + i, regs); + return; + } + } + + intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) + & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); + +#ifdef EMMA2RH_GPIO_CASCADE + if (intStatus & + (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + u32 gpioIntStatus; + gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) + & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { + if (gpioIntStatus & bitmask) { + do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs); + return; + } + } + } +#endif + + for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { + if (intStatus & bitmask) { + do_IRQ(EMMA2RH_IRQ_BASE + i, regs); + return; + } + } + + intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) + & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2); + + for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) { + if (intStatus & bitmask) { + do_IRQ(EMMA2RH_IRQ_BASE + i, regs); + return; + } + } +} diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c new file mode 100644 index 000000000000..b886aa94ca90 --- /dev/null +++ b/arch/mips/emma2rh/common/irq_emma2rh.c @@ -0,0 +1,134 @@ +/* + * arch/mips/emma2rh/common/irq_emma2rh.c + * This file defines the irq handler for EMMA2RH. + * + * Copyright (C) NEC Electronics Corporation 2005-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * EMMA2RH defines 64 IRQs. + * + * This file exports one function: + * emma2rh_irq_init(u32 irq_base); + */ + +#include <linux/interrupt.h> +#include <linux/types.h> +#include <linux/ptrace.h> + +#include <asm/debug.h> + +#include <asm/emma2rh/emma2rh.h> + +/* number of total irqs supported by EMMA2RH */ +#define NUM_EMMA2RH_IRQ 96 + +static int emma2rh_irq_base = -1; + +void ll_emma2rh_irq_enable(int); +void ll_emma2rh_irq_disable(int); + +static void emma2rh_irq_enable(unsigned int irq) +{ + ll_emma2rh_irq_enable(irq - emma2rh_irq_base); +} + +static void emma2rh_irq_disable(unsigned int irq) +{ + ll_emma2rh_irq_disable(irq - emma2rh_irq_base); +} + +static unsigned int emma2rh_irq_startup(unsigned int irq) +{ + emma2rh_irq_enable(irq); + return 0; +} + +#define emma2rh_irq_shutdown emma2rh_irq_disable + +static void emma2rh_irq_ack(unsigned int irq) +{ + /* disable interrupt - some handler will re-enable the irq + * and if the interrupt is leveled, we will have infinite loop + */ + ll_emma2rh_irq_disable(irq - emma2rh_irq_base); +} + +static void emma2rh_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + ll_emma2rh_irq_enable(irq - emma2rh_irq_base); +} + +hw_irq_controller emma2rh_irq_controller = { + .typename = "emma2rh_irq", + .startup = emma2rh_irq_startup, + .shutdown = emma2rh_irq_shutdown, + .enable = emma2rh_irq_enable, + .disable = emma2rh_irq_disable, + .ack = emma2rh_irq_ack, + .end = emma2rh_irq_end, + .set_affinity = NULL /* no affinity stuff for UP */ +}; + +void emma2rh_irq_init(u32 irq_base) +{ + u32 i; + + for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &emma2rh_irq_controller; + } + + emma2rh_irq_base = irq_base; +} + +void ll_emma2rh_irq_enable(int emma2rh_irq) +{ + u32 reg_value; + u32 reg_bitmask; + u32 reg_index; + + reg_index = EMMA2RH_BHIF_INT_EN_0 + + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) + * (emma2rh_irq / 32); + reg_value = emma2rh_in32(reg_index); + reg_bitmask = 0x1 << (emma2rh_irq % 32); + db_assert((reg_value & reg_bitmask) == 0); + emma2rh_out32(reg_index, reg_value | reg_bitmask); +} + +void ll_emma2rh_irq_disable(int emma2rh_irq) +{ + u32 reg_value; + u32 reg_bitmask; + u32 reg_index; + + reg_index = EMMA2RH_BHIF_INT_EN_0 + + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) + * (emma2rh_irq / 32); + reg_value = emma2rh_in32(reg_index); + reg_bitmask = 0x1 << (emma2rh_irq % 32); + db_assert((reg_value & reg_bitmask) != 0); + emma2rh_out32(reg_index, reg_value & ~reg_bitmask); +} diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c new file mode 100644 index 000000000000..8bba0b02a204 --- /dev/null +++ b/arch/mips/emma2rh/common/prom.c @@ -0,0 +1,77 @@ +/* + * arch/mips/emma2rh/common/prom.c + * This file is prom file. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/common/prom.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> + +#include <asm/addrspace.h> +#include <asm/bootinfo.h> +#include <asm/emma2rh/emma2rh.h> +#include <asm/debug.h> + +const char *get_system_type(void) +{ + switch (mips_machtype) { + case MACH_NEC_MARKEINS: + return "NEC EMMA2RH Mark-eins"; + default: + return "Unknown NEC board"; + } +} + +/* [jsun@junsun.net] PMON passes arguments in C main() style */ +void __init prom_init(void) +{ + int argc = fw_arg0; + char **arg = (char **)fw_arg1; + int i; + + /* if user passes kernel args, ignore the default one */ + if (argc > 1) + arcs_cmdline[0] = '\0'; + + /* arg[0] is "g", the rest is boot parameters */ + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_EMMA2RH; + +#if defined(CONFIG_MARKEINS) + mips_machtype = MACH_NEC_MARKEINS; + add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); +#endif + +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/emma2rh/markeins/Makefile b/arch/mips/emma2rh/markeins/Makefile new file mode 100644 index 000000000000..14fc268b175c --- /dev/null +++ b/arch/mips/emma2rh/markeins/Makefile @@ -0,0 +1,13 @@ +# +# arch/mips/emma2rh/markeins/Makefile +# Makefile for the common code of NEC EMMA2RH based board. +# +# Copyright (C) NEC Electronics Corporation 2005-2006 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# + +obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c new file mode 100644 index 000000000000..76dc3faeaf4e --- /dev/null +++ b/arch/mips/emma2rh/markeins/irq.c @@ -0,0 +1,134 @@ +/* + * arch/mips/emma2rh/markeins/irq.c + * This file defines the irq handler for EMMA2RH. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/types.h> +#include <linux/ptrace.h> +#include <linux/delay.h> + +#include <asm/i8259.h> +#include <asm/irq_cpu.h> +#include <asm/system.h> +#include <asm/mipsregs.h> +#include <asm/debug.h> +#include <asm/addrspace.h> +#include <asm/bootinfo.h> + +#include <asm/emma2rh/emma2rh.h> + +/* + * IRQ mapping + * + * 0-7: 8 CPU interrupts + * 0 - software interrupt 0 + * 1 - software interrupt 1 + * 2 - most Vrc5477 interrupts are routed to this pin + * 3 - (optional) some other interrupts routed to this pin for debugg + * 4 - not used + * 5 - not used + * 6 - not used + * 7 - cpu timer (used by default) + * + */ + +extern void emma2rh_sw_irq_init(u32 base); +extern void emma2rh_gpio_irq_init(u32 base); +extern void emma2rh_irq_init(u32 base); +extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs); + +static struct irqaction irq_cascade = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = "cascade", + .dev_id = NULL, + .next = NULL, +}; + +void __init arch_init_irq(void) +{ + u32 reg; + + db_run(printk("markeins_irq_setup invoked.\n")); + + /* by default, interrupts are disabled. */ + emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0); + emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0); + emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0); + emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0); + emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0); + emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0); + emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0); + + clear_c0_status(0xff00); + set_c0_status(0x0400); + +#define GPIO_PCI (0xf<<15) + /* setup GPIO interrupt for PCI interface */ + /* direction input */ + reg = emma2rh_in32(EMMA2RH_GPIO_DIR); + emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI); + /* disable interrupt */ + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI); + /* level triggerd */ + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE); + emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI); + reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A); + emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI)); + /* interrupt clear */ + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI); + + /* init all controllers */ + emma2rh_irq_init(EMMA2RH_IRQ_BASE); + emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE); + emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE); + mips_cpu_irq_init(CPU_IRQ_BASE); + + /* setup cascade interrupts */ + setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); + setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); +} + +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & STATUSF_IP7) + do_IRQ(CPU_IRQ_BASE + 7, regs); + else if (pending & STATUSF_IP2) + emma2rh_irq_dispatch(regs); + else if (pending & STATUSF_IP1) + do_IRQ(CPU_IRQ_BASE + 1, regs); + else if (pending & STATUSF_IP0) + do_IRQ(CPU_IRQ_BASE + 0, regs); + else + spurious_interrupt(regs); +} + + diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c new file mode 100644 index 000000000000..1783fdab6459 --- /dev/null +++ b/arch/mips/emma2rh/markeins/irq_markeins.c @@ -0,0 +1,197 @@ +/* + * arch/mips/emma2rh/markeins/irq_markeins.c + * This file defines the irq handler for Mark-eins. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/types.h> +#include <linux/ptrace.h> + +#include <asm/debug.h> +#include <asm/emma2rh/emma2rh.h> + +static int emma2rh_sw_irq_base = -1; +static int emma2rh_gpio_irq_base = -1; + +void ll_emma2rh_sw_irq_enable(int reg); +void ll_emma2rh_sw_irq_disable(int reg); +void ll_emma2rh_gpio_irq_enable(int reg); +void ll_emma2rh_gpio_irq_disable(int reg); + +static void emma2rh_sw_irq_enable(unsigned int irq) +{ + ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base); +} + +static void emma2rh_sw_irq_disable(unsigned int irq) +{ + ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); +} + +static unsigned int emma2rh_sw_irq_startup(unsigned int irq) +{ + emma2rh_sw_irq_enable(irq); + return 0; +} + +#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable + +static void emma2rh_sw_irq_ack(unsigned int irq) +{ + ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); +} + +static void emma2rh_sw_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base); +} + +hw_irq_controller emma2rh_sw_irq_controller = { + .typename = "emma2rh_sw_irq", + .startup = emma2rh_sw_irq_startup, + .shutdown = emma2rh_sw_irq_shutdown, + .enable = emma2rh_sw_irq_enable, + .disable = emma2rh_sw_irq_disable, + .ack = emma2rh_sw_irq_ack, + .end = emma2rh_sw_irq_end, + .set_affinity = NULL, +}; + +void emma2rh_sw_irq_init(u32 irq_base) +{ + u32 i; + + for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 2; + irq_desc[i].handler = &emma2rh_sw_irq_controller; + } + + emma2rh_sw_irq_base = irq_base; +} + +void ll_emma2rh_sw_irq_enable(int irq) +{ + u32 reg; + + db_assert(irq >= 0); + db_assert(irq < NUM_EMMA2RH_IRQ_SW); + + reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); + reg |= 1 << irq; + emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); +} + +void ll_emma2rh_sw_irq_disable(int irq) +{ + u32 reg; + + db_assert(irq >= 0); + db_assert(irq < 32); + + reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); +} + +static void emma2rh_gpio_irq_enable(unsigned int irq) +{ + ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base); +} + +static void emma2rh_gpio_irq_disable(unsigned int irq) +{ + ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); +} + +static unsigned int emma2rh_gpio_irq_startup(unsigned int irq) +{ + emma2rh_gpio_irq_enable(irq); + return 0; +} + +#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable + +static void emma2rh_gpio_irq_ack(unsigned int irq) +{ + irq -= emma2rh_gpio_irq_base; + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); + ll_emma2rh_gpio_irq_disable(irq); +} + +static void emma2rh_gpio_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base); +} + +hw_irq_controller emma2rh_gpio_irq_controller = { + .typename = "emma2rh_gpio_irq", + .startup = emma2rh_gpio_irq_startup, + .shutdown = emma2rh_gpio_irq_shutdown, + .enable = emma2rh_gpio_irq_enable, + .disable = emma2rh_gpio_irq_disable, + .ack = emma2rh_gpio_irq_ack, + .end = emma2rh_gpio_irq_end, + .set_affinity = NULL, +}; + +void emma2rh_gpio_irq_init(u32 irq_base) +{ + u32 i; + + for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 2; + irq_desc[i].handler = &emma2rh_gpio_irq_controller; + } + + emma2rh_gpio_irq_base = irq_base; +} + +void ll_emma2rh_gpio_irq_enable(int irq) +{ + u32 reg; + + db_assert(irq >= 0); + db_assert(irq < NUM_EMMA2RH_IRQ_GPIO); + + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg |= 1 << irq; + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); +} + +void ll_emma2rh_gpio_irq_disable(int irq) +{ + u32 reg; + + db_assert(irq >= 0); + db_assert(irq < NUM_EMMA2RH_IRQ_GPIO); + + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); +} diff --git a/arch/mips/emma2rh/markeins/led.c b/arch/mips/emma2rh/markeins/led.c new file mode 100644 index 000000000000..b65254c1bfe9 --- /dev/null +++ b/arch/mips/emma2rh/markeins/led.c @@ -0,0 +1,60 @@ +/* + * arch/mips/emma2rh/markeins/led.c + * This file defines the led display for Mark-eins. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/string.h> +#include <asm/emma2rh/emma2rh.h> + +const unsigned long clear = 0x20202020; + +#define LED_BASE 0xb1400038 + +void markeins_led_clear(void) +{ + emma2rh_out32(LED_BASE, clear); + emma2rh_out32(LED_BASE + 4, clear); +} + +void markeins_led(const char *str) +{ + int i; + int len = strlen(str); + + markeins_led_clear(); + if (len > 8) + len = 8; + + if (emma2rh_in32(0xb0000800) & (0x1 << 18)) + for (i = 0; i < len; i++) + emma2rh_out8(LED_BASE + i, str[i]); + else + for (i = 0; i < len; i++) + emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)), + str[i]); +} + +void markeins_led_hex(u32 val) +{ + char str[10]; + + sprintf(str, "%08x", val); + markeins_led(str); +} diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c new file mode 100644 index 000000000000..6c1eeae1a898 --- /dev/null +++ b/arch/mips/emma2rh/markeins/platform.c @@ -0,0 +1,170 @@ +/* + * arch/mips/emma2rh/markeins/platofrm.c + * This file sets up platform devices for EMMA2RH Mark-eins. + * + * Copyright(C) MontaVista Software Inc, 2006 + * + * Author: dmitry pervushin <dpervushin@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/ioport.h> +#include <linux/serial_8250.h> +#include <linux/mtd/physmap.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/addrspace.h> +#include <asm/time.h> +#include <asm/bcache.h> +#include <asm/irq.h> +#include <asm/reboot.h> +#include <asm/gdb-stub.h> +#include <asm/traps.h> +#include <asm/debug.h> + +#include <asm/emma2rh/emma2rh.h> + + +#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */ + +static struct resource i2c_emma_resources_0[] = { + { NULL, EMMA2RH_IRQ_PIIC0, EMMA2RH_IRQ_PIIC0, IORESOURCE_IRQ }, + { NULL, KSEG1ADDR(EMMA2RH_PIIC0_BASE), KSEG1ADDR(EMMA2RH_PIIC0_BASE + 0x1000), 0 }, +}; + +struct resource i2c_emma_resources_1[] = { + { NULL, EMMA2RH_IRQ_PIIC1, EMMA2RH_IRQ_PIIC1, IORESOURCE_IRQ }, + { NULL, KSEG1ADDR(EMMA2RH_PIIC1_BASE), KSEG1ADDR(EMMA2RH_PIIC1_BASE + 0x1000), 0 }, +}; + +struct resource i2c_emma_resources_2[] = { + { NULL, EMMA2RH_IRQ_PIIC2, EMMA2RH_IRQ_PIIC2, IORESOURCE_IRQ }, + { NULL, KSEG1ADDR(EMMA2RH_PIIC2_BASE), KSEG1ADDR(EMMA2RH_PIIC2_BASE + 0x1000), 0 }, +}; + +struct platform_device i2c_emma_devices[] = { + [0] = { + .name = I2C_EMMA2RH, + .id = 0, + .resource = i2c_emma_resources_0, + .num_resources = ARRAY_SIZE(i2c_emma_resources_0), + }, + [1] = { + .name = I2C_EMMA2RH, + .id = 1, + .resource = i2c_emma_resources_1, + .num_resources = ARRAY_SIZE(i2c_emma_resources_1), + }, + [2] = { + .name = I2C_EMMA2RH, + .id = 2, + .resource = i2c_emma_resources_2, + .num_resources = ARRAY_SIZE(i2c_emma_resources_2), + }, +}; + +#define EMMA2RH_SERIAL_CLOCK 18544000 +#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST + +static struct plat_serial8250_port platform_serial_ports[] = { + [0] = { + .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), + .irq = EMMA2RH_IRQ_PFUR0, + .uartclk = EMMA2RH_SERIAL_CLOCK, + .regshift = 4, + .iotype = UPIO_MEM, + .flags = EMMA2RH_SERIAL_FLAGS, + }, + [1] = { + .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), + .irq = EMMA2RH_IRQ_PFUR1, + .uartclk = EMMA2RH_SERIAL_CLOCK, + .regshift = 4, + .iotype = UPIO_MEM, + .flags = EMMA2RH_SERIAL_FLAGS, + }, + [2] = { + .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3), + .irq = EMMA2RH_IRQ_PFUR2, + .uartclk = EMMA2RH_SERIAL_CLOCK, + .regshift = 4, + .iotype = UPIO_MEM, + .flags = EMMA2RH_SERIAL_FLAGS, + }, + [3] = { + .flags = 0, + }, +}; + +static struct platform_device serial_emma = { + .name = "serial8250", + .dev = { + .platform_data = &platform_serial_ports, + }, +}; + +static struct platform_device *devices[] = { + &i2c_emma_devices[0], + &i2c_emma_devices[1], + &i2c_emma_devices[2], + &serial_emma, +}; + +static struct mtd_partition markeins_parts[] = { + [0] = { + .name = "RootFS", + .offset = 0x00000000, + .size = 0x00c00000, + }, + [1] = { + .name = "boot code area", + .offset = MTDPART_OFS_APPEND, + .size = 0x00100000, + }, + [2] = { + .name = "kernel image", + .offset = MTDPART_OFS_APPEND, + .size = 0x00300000, + }, + [3] = { + .name = "RootFS2", + .offset = MTDPART_OFS_APPEND, + .size = 0x00c00000, + }, + [4] = { + .name = "boot code area2", + .offset = MTDPART_OFS_APPEND, + .size = 0x00100000, + }, + [5] = { + .name = "kernel image2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static int __init platform_devices_setup(void) +{ + physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts)); + return platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +arch_initcall(platform_devices_setup); + diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c new file mode 100644 index 000000000000..7d98fdbf8390 --- /dev/null +++ b/arch/mips/emma2rh/markeins/setup.c @@ -0,0 +1,182 @@ +/* + * arch/mips/emma2rh/markeins/setup.c + * This file is setup for EMMA2RH Mark-eins. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c. + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/initrd.h> +#include <linux/irq.h> +#include <linux/ide.h> +#include <linux/ioport.h> +#include <linux/param.h> /* for HZ */ +#include <linux/root_dev.h> +#include <linux/serial.h> +#include <linux/serial_core.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/addrspace.h> +#include <asm/time.h> +#include <asm/bcache.h> +#include <asm/irq.h> +#include <asm/reboot.h> +#include <asm/gdb-stub.h> +#include <asm/traps.h> +#include <asm/debug.h> + +#include <asm/emma2rh/emma2rh.h> + +#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ + +extern void markeins_led(const char *); + +static int bus_frequency = 0; + +static void markeins_machine_restart(char *command) +{ + static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000; + + printk("cannot EMMA2RH Mark-eins restart.\n"); + markeins_led("restart."); + back_to_prom(); +} + +static void markeins_machine_halt(void) +{ + printk("EMMA2RH Mark-eins halted.\n"); + markeins_led("halted."); + while (1) ; +} + +static void markeins_machine_power_off(void) +{ + printk("EMMA2RH Mark-eins halted. Please turn off the power.\n"); + markeins_led("poweroff."); + while (1) ; +} + +static unsigned long clock[4] = { 166500000, 187312500, 199800000, 210600000 }; + +static unsigned int __init detect_bus_frequency(unsigned long rtc_base) +{ + u32 reg; + + /* detect from boot strap */ + reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); + reg = (reg >> 4) & 0x3; + return clock[reg]; +} + +static void __init emma2rh_time_init(void) +{ + u32 reg; + if (bus_frequency == 0) + bus_frequency = detect_bus_frequency(0); + + reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); + if ((reg & 0x3) == 0) + reg = (reg >> 6) & 0x3; + else { + reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL); + reg = (reg >> 4) & 0x3; + } + mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2; +} + +static void __init emma2rh_timer_setup(struct irqaction *irq) +{ + /* we are using the cpu counter for timer interrupts */ + setup_irq(CPU_IRQ_BASE + 7, irq); +} + +static void markeins_board_init(void); +extern void markeins_irq_setup(void); + +static void inline __init markeins_sio_setup(void) +{ +#ifdef CONFIG_KGDB_8250 + struct uart_port emma_port; + + memset(&emma_port, 0, sizeof(emma_port)); + + emma_port.flags = + UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; + emma_port.iotype = UPIO_MEM; + emma_port.regshift = 4; /* I/O addresses are every 8 bytes */ + emma_port.uartclk = 18544000; /* Clock rate of the chip */ + + emma_port.line = 0; + emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3); + emma_port.membase = (u8*)emma_port.mapbase; + early_serial_setup(&emma_port); + + emma_port.line = 1; + emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3); + emma_port.membase = (u8*)emma_port.mapbase; + early_serial_setup(&emma_port); + + emma_port.irq = EMMA2RH_IRQ_PFUR1; + kgdb8250_add_port(1, &emma_port); +#endif +} + +void __init plat_mem_setup(void) +{ + /* initialize board - we don't trust the loader */ + markeins_board_init(); + + set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE)); + + board_time_init = emma2rh_time_init; + board_timer_setup = emma2rh_timer_setup; + + _machine_restart = markeins_machine_restart; + _machine_halt = markeins_machine_halt; + pm_power_off = markeins_machine_power_off; + + /* setup resource limits */ + ioport_resource.start = EMMA2RH_PCI_IO_BASE; + ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1; + iomem_resource.start = EMMA2RH_IO_BASE; + iomem_resource.end = EMMA2RH_ROM_BASE - 1; + + /* Reboot on panic */ + panic_timeout = 180; + + markeins_sio_setup(); +} + +static void __init markeins_board_init(void) +{ + u32 val; + + val = emma2rh_in32(EMMA2RH_PBRD_INT_EN); /* open serial interrupts. */ + emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa); + val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL); /* set serial clocks. */ + emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5); /* 18MHz */ + emma2rh_out32(EMMA2RH_PCI_CONTROL, 0); + + markeins_led("MVL E2RH"); +} diff --git a/arch/mips/galileo-boards/ev96100/setup.c b/arch/mips/galileo-boards/ev96100/setup.c index 78dbb18edeb8..a04aea6123da 100644 --- a/arch/mips/galileo-boards/ev96100/setup.c +++ b/arch/mips/galileo-boards/ev96100/setup.c @@ -55,7 +55,7 @@ extern void mips_reboot_setup(void); unsigned char mac_0_1[12]; -void __init plat_setup(void) +void __init plat_mem_setup(void) { unsigned int config = read_c0_config(); unsigned int status = read_c0_status(); diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c index 6d859d1e7a2d..4236da31ecc6 100644 --- a/arch/mips/gt64120/ev64120/setup.c +++ b/arch/mips/gt64120/ev64120/setup.c @@ -71,7 +71,7 @@ unsigned long __init prom_free_prom_memory(void) */ extern void gt64120_time_init(void); -void __init plat_setup(void) +void __init plat_mem_setup(void) { _machine_restart = galileo_machine_restart; _machine_halt = galileo_machine_halt; diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c index 20b65d3d2151..1193a22c4693 100644 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ b/arch/mips/gt64120/momenco_ocelot/setup.c @@ -152,7 +152,7 @@ void PMON_v2_setup() gt64120_base = 0xe0000000; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); unsigned int tmpword; diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile new file mode 100644 index 000000000000..72606b9af12a --- /dev/null +++ b/arch/mips/gt64120/wrppmc/Makefile @@ -0,0 +1,14 @@ +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright 2006 Wind River System, Inc. +# Author: Rongkai.Zhan <rongkai.zhan@windriver.com> +# +# Makefile for the Wind River MIPS 4KC PPMC Eval Board +# + +obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o + +EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/gt64120/wrppmc/int-handler.S b/arch/mips/gt64120/wrppmc/int-handler.S new file mode 100644 index 000000000000..edee7b394175 --- /dev/null +++ b/arch/mips/gt64120/wrppmc/int-handler.S @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle + * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com> + */ +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> +#include <asm/mach-wrppmc/mach-gt64120.h> + + .align 5 + .set noat +NESTED(handle_IRQ, PT_SIZE, sp) + SAVE_ALL + CLI # Important: mark KERNEL mode ! + .set at + + mfc0 t0, CP0_CAUSE # get pending interrupts + mfc0 t1, CP0_STATUS # get enabled interrupts + and t0, t0, t1 # get allowed interrupts + andi t0, t0, 0xFF00 + beqz t0, 1f + move a1, sp # Prepare 'struct pt_regs *regs' pointer + + andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer + bnez t1, handle_cputimer_irq + andi t1, t0, CAUSEF_IP6 # UART 16550 port + bnez t1, handle_uart_irq + andi t1, t0, CAUSEF_IP3 # PCI INT_A + bnez t1, handle_pci_intA_irq + + /* wrong alarm or masked ... */ +1: j spurious_interrupt + nop +END(handle_IRQ) + + .align 5 +handle_cputimer_irq: + li a0, WRPPMC_MIPS_TIMER_IRQ + jal do_IRQ + j ret_from_irq + + .align 5 +handle_uart_irq: + li a0, WRPPMC_UART16550_IRQ + jal do_IRQ + j ret_from_irq + + .align 5 +handle_pci_intA_irq: + li a0, WRPPMC_PCI_INTA_IRQ + jal do_IRQ + j ret_from_irq + diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c new file mode 100644 index 000000000000..8605687e24ed --- /dev/null +++ b/arch/mips/gt64120/wrppmc/irq.c @@ -0,0 +1,63 @@ +/* + * irq.c: GT64120 Interrupt Controller + * + * Copyright (C) 2006, Wind River System Inc. + * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/bitops.h> +#include <asm/mipsregs.h> +#include <asm/system.h> +#include <asm/irq_cpu.h> +#include <asm/gt64120.h> + +extern asmlinkage void handle_IRQ(void); + +/** + * Initialize GT64120 Interrupt Controller + */ +void gt64120_init_pic(void) +{ + /* clear CPU Interrupt Cause Registers */ + GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21)); + GT_WRITE(GT_HINTRCAUSE_OFS, 0x00); + + /* Disable all interrupts from GT64120 bridge chip */ + GT_WRITE(GT_INTRMASK_OFS, 0x00); + GT_WRITE(GT_HINTRMASK_OFS, 0x00); + GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00); + GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00); +} + +void __init arch_init_irq(void) +{ + /* enable all CPU interrupt bits. */ + set_c0_status(ST0_IM); /* IE bit is still 0 */ + + /* Install MIPS Interrupt Trap Vector */ + set_except_vector(0, handle_IRQ); + + /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ + mips_cpu_irq_init(0); + + gt64120_init_pic(); +} diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/gt64120/wrppmc/pci.c new file mode 100644 index 000000000000..2fbe93467f78 --- /dev/null +++ b/arch/mips/gt64120/wrppmc/pci.c @@ -0,0 +1,53 @@ +/* + * pci.c: GT64120 PCI support. + * + * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <asm/gt64120.h> + +extern struct pci_ops gt64120_pci_ops; + +static struct resource pci0_io_resource = { + .name = "pci_0 io", + .start = GT_PCI_IO_BASE, + .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +static struct resource pci0_mem_resource = { + .name = "pci_0 memory", + .start = GT_PCI_MEM_BASE, + .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct pci_controller hose_0 = { + .pci_ops = >64120_pci_ops, + .io_resource = &pci0_io_resource, + .mem_resource = &pci0_mem_resource, +}; + +static int __init gt64120_pci_init(void) +{ + u32 tmp; + + tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ + tmp = GT_READ(GT_PCI0_BARE_OFS); + + /* reset the whole PCI I/O space range */ + ioport_resource.start = GT_PCI_IO_BASE; + ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; + + register_pci_controller(&hose_0); + return 0; +} + +arch_initcall(gt64120_pci_init); diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/gt64120/wrppmc/reset.c new file mode 100644 index 000000000000..b97039c6d3db --- /dev/null +++ b/arch/mips/gt64120/wrppmc/reset.c @@ -0,0 +1,50 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997 Ralf Baechle + */ +#include <linux/sched.h> +#include <linux/mm.h> +#include <asm/io.h> +#include <asm/pgtable.h> +#include <asm/processor.h> +#include <asm/reboot.h> +#include <asm/system.h> +#include <asm/cacheflush.h> + +void wrppmc_machine_restart(char *command) +{ + /* + * Ouch, we're still alive ... This time we take the silver bullet ... + * ... and find that we leave the hardware in a state in which the + * kernel in the flush locks up somewhen during of after the PCI + * detection stuff. + */ + local_irq_disable(); + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +} + +void wrppmc_machine_halt(void) +{ + local_irq_disable(); + + printk(KERN_NOTICE "You can safely turn off the power\n"); + while (1) { + __asm__( + ".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0" + ); + } +} + +void wrppmc_machine_power_off(void) +{ + wrppmc_machine_halt(); +} diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c new file mode 100644 index 000000000000..20c591e49dae --- /dev/null +++ b/arch/mips/gt64120/wrppmc/setup.c @@ -0,0 +1,173 @@ +/* + * setup.c: Setup pointers to hardware dependent routines. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com> + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/pm.h> + +#include <asm/io.h> +#include <asm/bootinfo.h> +#include <asm/reboot.h> +#include <asm/time.h> +#include <asm/gt64120.h> + +unsigned long gt64120_base = KSEG1ADDR(0x14000000); + +#ifdef WRPPMC_EARLY_DEBUG + +static volatile unsigned char * wrppmc_led = \ + (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE); + +/* + * PPMC LED control register: + * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON) + * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON) + * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON) + */ +void wrppmc_led_on(int mask) +{ + unsigned char value = *wrppmc_led; + + value &= (0xF8 | mask); + *wrppmc_led = value; +} + +/* If mask = 0, turn off all LEDs */ +void wrppmc_led_off(int mask) +{ + unsigned char value = *wrppmc_led; + + value |= (0x7 & mask); + *wrppmc_led = value; +} + +/* + * We assume that bootloader has initialized UART16550 correctly + */ +void __init wrppmc_early_putc(char ch) +{ + static volatile unsigned char *wrppmc_uart = \ + (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE); + unsigned char value; + + /* Wait until Transmit-Holding-Register is empty */ + while (1) { + value = *(wrppmc_uart + 5); + if (value & 0x20) + break; + } + + *wrppmc_uart = ch; +} + +void __init wrppmc_early_printk(const char *fmt, ...) +{ + static char pbuf[256] = {'\0', }; + char *ch = pbuf; + va_list args; + unsigned int i; + + memset(pbuf, 0, 256); + va_start(args, fmt); + i = vsprintf(pbuf, fmt, args); + va_end(args); + + /* Print the string */ + while (*ch != '\0') { + wrppmc_early_putc(*ch); + /* if print '\n', also print '\r' */ + if (*ch++ == '\n') + wrppmc_early_putc('\r'); + } +} +#endif /* WRPPMC_EARLY_DEBUG */ + +unsigned long __init prom_free_prom_memory(void) +{ + return 0; +} + +#ifdef CONFIG_SERIAL_8250 +static void wrppmc_setup_serial(void) +{ + struct uart_port up; + + memset(&up, 0x00, sizeof(struct uart_port)); + + /* + * A note about mapbase/membase + * -) mapbase is the physical address of the IO port. + * -) membase is an 'ioremapped' cookie. + */ + up.line = 0; + up.type = PORT_16550; + up.iotype = UPIO_MEM; + up.mapbase = WRPPMC_UART16550_BASE; + up.membase = ioremap(up.mapbase, 8); + up.irq = WRPPMC_UART16550_IRQ; + up.uartclk = WRPPMC_UART16550_CLOCK; + up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */; + up.regshift = 0; + + early_serial_setup(&up); +} +#endif + +void __init plat_setup(void) +{ + extern void wrppmc_time_init(void); + extern void wrppmc_timer_setup(struct irqaction *); + extern void wrppmc_machine_restart(char *command); + extern void wrppmc_machine_halt(void); + extern void wrppmc_machine_power_off(void); + + _machine_restart = wrppmc_machine_restart; + _machine_halt = wrppmc_machine_halt; + pm_power_off = wrppmc_machine_power_off; + + /* Use MIPS Count/Compare Timer */ + board_time_init = wrppmc_time_init; + board_timer_setup = wrppmc_timer_setup; + + /* This makes the operations of 'in/out[bwl]' to the + * physical address ( < KSEG0) can work via KSEG1 + */ + set_io_port_base(KSEG1); + +#ifdef CONFIG_SERIAL_8250 + wrppmc_setup_serial(); +#endif +} + +const char *get_system_type(void) +{ + return "Wind River PPMC (GT64120)"; +} + +/* + * Initializes basic routines and structures pointers, memory size (as + * given by the bios and saves the command line. + */ +void __init prom_init(void) +{ + mips_machgroup = MACH_GROUP_GALILEO; + mips_machtype = MACH_EV64120A; + + add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); + add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); + + wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n", + WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE)); +} diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c new file mode 100644 index 000000000000..175d22adb450 --- /dev/null +++ b/arch/mips/gt64120/wrppmc/time.c @@ -0,0 +1,57 @@ +/* + * time.c: MIPS CPU Count/Compare timer hookup + * + * Author: Mark.Zhan, <rongkai.zhan@windriver.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2006, Wind River System Inc. + */ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> +#include <linux/param.h> /* for HZ */ +#include <linux/irq.h> +#include <linux/timex.h> +#include <linux/interrupt.h> + +#include <asm/reboot.h> +#include <asm/time.h> +#include <asm/io.h> +#include <asm/bootinfo.h> +#include <asm/gt64120.h> + +#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */ + +void __init wrppmc_timer_setup(struct irqaction *irq) +{ + /* Install ISR for timer interrupt */ + setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq); + + /* to generate the first timer interrupt */ + write_c0_compare(mips_hpt_frequency/HZ); + write_c0_count(0); +} + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + * + * NOTE: We disable all GT64120 timers, and use MIPS processor internal + * timer as the source of kernel clock tick. + */ +void __init wrppmc_time_init(void) +{ + /* Disable GT64120 timers */ + GT_WRITE(GT_TC_CONTROL_OFS, 0x00); + GT_WRITE(GT_TC0_OFS, 0x00); + GT_WRITE(GT_TC1_OFS, 0x00); + GT_WRITE(GT_TC2_OFS, 0x00); + GT_WRITE(GT_TC3_OFS, 0x00); + + /* Use MIPS compare/count internal timer */ + mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ; +} diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c index fc73c8d69df7..da6ae0991199 100644 --- a/arch/mips/ite-boards/generic/it8172_setup.c +++ b/arch/mips/ite-boards/generic/it8172_setup.c @@ -72,11 +72,29 @@ struct { struct resource flash; struct resource boot; } it8172_resources = { - { "RAM", 0, 0, IORESOURCE_MEM }, /* to be initted */ - { "PCI Mem", 0x10000000, 0x13FFFFFF, IORESOURCE_MEM }, - { "PCI I/O", 0x14000000, 0x17FFFFFF }, - { "Flash", 0x08000000, 0x0CFFFFFF }, - { "Boot ROM", 0x1FC00000, 0x1FFFFFFF } + { + .start = 0, /* to be initted */ + .end = 0, + .name = "RAM", + .flags = IORESOURCE_MEM + }, { + .start = 0x10000000, + .end = 0x13FFFFFF, + .name = "PCI Mem", + .flags = IORESOURCE_MEM + }, { + .start = 0x14000000, + .end = 0x17FFFFFF + .name = "PCI I/O", + }, { + .start = 0x08000000, + .end = 0x0CFFFFFF + .name = "Flash", + }, { + .start = 0x1FC00000, + .end = 0x1FFFFFFF + .name = "Boot ROM", + } }; #else struct { @@ -89,14 +107,44 @@ struct { struct resource flash; struct resource boot; } it8172_resources = { - { "RAM", 0, 0, IORESOURCE_MEM }, /* to be initted */ - { "PCI Mem0", 0x0C000000, 0x0FFFFFFF, IORESOURCE_MEM }, - { "PCI Mem1", 0x10000000, 0x13FFFFFF, IORESOURCE_MEM }, - { "PCI I/O", 0x14000000, 0x17FFFFFF }, - { "PCI Mem2", 0x1A000000, 0x1BFFFFFF, IORESOURCE_MEM }, - { "PCI Mem3", 0x1C000000, 0x1FBFFFFF, IORESOURCE_MEM }, - { "Flash", 0x08000000, 0x0CFFFFFF }, - { "Boot ROM", 0x1FC00000, 0x1FFFFFFF } + { + .start = 0, /* to be initted */ + .end = 0, + .name = "RAM", + .flags = IORESOURCE_MEM + }, { + .start = 0x0C000000, + .end = 0x0FFFFFFF, + .name = "PCI Mem0", + .flags = IORESOURCE_MEM + }, { + .start = 0x10000000, + .end = 0x13FFFFFF, + .name = "PCI Mem1", + .flags = IORESOURCE_MEM + }, { + .start = 0x14000000, + .end = 0x17FFFFFF + .name = "PCI I/O", + }, { + .start = 0x1A000000, + .end = 0x1BFFFFFF, + .name = "PCI Mem2", + .flags = IORESOURCE_MEM + }, { + .start = 0x1C000000, + .end = 0x1FBFFFFF, + .name = "PCI Mem3", + .flags = IORESOURCE_MEM + }, { + .start = 0x08000000, + .end = 0x0CFFFFFF + .name = "Flash", + }, { + .start = 0x1FC00000, + .end = 0x1FFFFFFF + .name = "Boot ROM", + } }; #endif @@ -106,7 +154,7 @@ void __init it8172_init_ram_resource(unsigned long memsize) it8172_resources.ram.end = memsize; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { unsigned short dsr; char *argptr; diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 4036dc434551..c8d0df7d0c36 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -52,7 +52,7 @@ static struct resource jazz_io_resources[] = { { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, }; -void __init plat_setup(void) +void __init plat_mem_setup(void) { int i; diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c index 9359cc413494..308e6cdcd245 100644 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ b/arch/mips/jmr3927/rbhma3100/setup.c @@ -82,17 +82,54 @@ struct { struct resource sio0; struct resource sio1; } jmr3927_resources = { - { "RAM0", 0, 0x01FFFFFF, IORESOURCE_MEM }, - { "RAM1", 0x02000000, 0x03FFFFFF, IORESOURCE_MEM }, - { "PCIMEM", 0x08000000, 0x07FFFFFF, IORESOURCE_MEM }, - { "IOB", 0x10000000, 0x13FFFFFF }, - { "IOC", 0x14000000, 0x14FFFFFF }, - { "PCIIO", 0x15000000, 0x15FFFFFF }, - { "JMY1394", 0x1D000000, 0x1D3FFFFF }, - { "ROM1", 0x1E000000, 0x1E3FFFFF }, - { "ROM0", 0x1FC00000, 0x1FFFFFFF }, - { "SIO0", 0xFFFEF300, 0xFFFEF3FF }, - { "SIO1", 0xFFFEF400, 0xFFFEF4FF }, + { + .start = 0, + .end = 0x01FFFFFF, + .name = "RAM0", + .flags = IORESOURCE_MEM + }, { + .start = 0x02000000, + .end = 0x03FFFFFF, + .name = "RAM1", + .flags = IORESOURCE_MEM + }, { + .start = 0x08000000, + .end = 0x07FFFFFF, + .name = "PCIMEM", + .flags = IORESOURCE_MEM + }, { + .start = 0x10000000, + .end = 0x13FFFFFF, + .name = "IOB" + }, { + .start = 0x14000000, + .end = 0x14FFFFFF, + .name = "IOC" + }, { + .start = 0x15000000, + .end = 0x15FFFFFF, + .name = "PCIIO" + }, { + .start = 0x1D000000, + .end = 0x1D3FFFFF, + .name = "JMY1394" + }, { + .start = 0x1E000000, + .end = 0x1E3FFFFF, + .name = "ROM1" + }, { + .start = 0x1FC00000, + .end = 0x1FFFFFFF, + .name = "ROM0" + }, { + .start = 0xFFFEF300, + .end = 0xFFFEF3FF, + .name = "SIO0" + }, { + .start = 0xFFFEF400, + .end = 0xFFFEF4FF, + .name = "SIO1" + }, }; /* don't enable - see errata */ @@ -201,7 +238,7 @@ static void jmr3927_board_init(void); extern struct resource pci_io_resource; extern struct resource pci_mem_resource; -void __init plat_setup(void) +void __init plat_mem_setup(void) { char *argptr; diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 34e8a256765c..881c467c6982 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -13,6 +13,8 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ obj-$(CONFIG_MODULES) += mips_ksyms.o module.o +obj-$(CONFIG_APM) += apm.o + obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c new file mode 100644 index 000000000000..15f46b4471fd --- /dev/null +++ b/arch/mips/kernel/apm.c @@ -0,0 +1,605 @@ +/* + * bios-less APM driver for MIPS Linux + * Jamey Hicks <jamey@crl.dec.com> + * adapted from the APM BIOS driver for Linux by Stephen Rothwell (sfr@linuxcare.com) + * + * APM 1.2 Reference: + * Intel Corporation, Microsoft Corporation. Advanced Power Management + * (APM) BIOS Interface Specification, Revision 1.2, February 1996. + * + * [This document is available from Microsoft at: + * http://www.microsoft.com/hwdev/busbios/amp_12.htm] + */ +#include <linux/config.h> +#include <linux/module.h> +#include <linux/poll.h> +#include <linux/timer.h> +#include <linux/slab.h> +#include <linux/proc_fs.h> +#include <linux/miscdevice.h> +#include <linux/apm_bios.h> +#include <linux/capability.h> +#include <linux/sched.h> +#include <linux/pm.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/init.h> +#include <linux/completion.h> + +#include <asm/apm.h> /* apm_power_info */ +#include <asm/system.h> + +/* + * The apm_bios device is one of the misc char devices. + * This is its minor number. + */ +#define APM_MINOR_DEV 134 + +/* + * See Documentation/Config.help for the configuration options. + * + * Various options can be changed at boot time as follows: + * (We allow underscores for compatibility with the modules code) + * apm=on/off enable/disable APM + */ + +/* + * Maximum number of events stored + */ +#define APM_MAX_EVENTS 16 + +struct apm_queue { + unsigned int event_head; + unsigned int event_tail; + apm_event_t events[APM_MAX_EVENTS]; +}; + +/* + * The per-file APM data + */ +struct apm_user { + struct list_head list; + + unsigned int suser: 1; + unsigned int writer: 1; + unsigned int reader: 1; + + int suspend_result; + unsigned int suspend_state; +#define SUSPEND_NONE 0 /* no suspend pending */ +#define SUSPEND_PENDING 1 /* suspend pending read */ +#define SUSPEND_READ 2 /* suspend read, pending ack */ +#define SUSPEND_ACKED 3 /* suspend acked */ +#define SUSPEND_DONE 4 /* suspend completed */ + + struct apm_queue queue; +}; + +/* + * Local variables + */ +static int suspends_pending; +static int apm_disabled; +static int mips_apm_active; + +static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue); +static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue); + +/* + * This is a list of everyone who has opened /dev/apm_bios + */ +static DECLARE_RWSEM(user_list_lock); +static LIST_HEAD(apm_user_list); + +/* + * kapmd info. kapmd provides us a process context to handle + * "APM" events within - specifically necessary if we're going + * to be suspending the system. + */ +static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait); +static DECLARE_COMPLETION(kapmd_exit); +static DEFINE_SPINLOCK(kapmd_queue_lock); +static struct apm_queue kapmd_queue; + + +static const char driver_version[] = "1.13"; /* no spaces */ + + + +/* + * Compatibility cruft until the IPAQ people move over to the new + * interface. + */ +static void __apm_get_power_status(struct apm_power_info *info) +{ +} + +/* + * This allows machines to provide their own "apm get power status" function. + */ +void (*apm_get_power_status)(struct apm_power_info *) = __apm_get_power_status; +EXPORT_SYMBOL(apm_get_power_status); + + +/* + * APM event queue management. + */ +static inline int queue_empty(struct apm_queue *q) +{ + return q->event_head == q->event_tail; +} + +static inline apm_event_t queue_get_event(struct apm_queue *q) +{ + q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS; + return q->events[q->event_tail]; +} + +static void queue_add_event(struct apm_queue *q, apm_event_t event) +{ + q->event_head = (q->event_head + 1) % APM_MAX_EVENTS; + if (q->event_head == q->event_tail) { + static int notified; + + if (notified++ == 0) + printk(KERN_ERR "apm: an event queue overflowed\n"); + q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS; + } + q->events[q->event_head] = event; +} + +static void queue_event_one_user(struct apm_user *as, apm_event_t event) +{ + if (as->suser && as->writer) { + switch (event) { + case APM_SYS_SUSPEND: + case APM_USER_SUSPEND: + /* + * If this user already has a suspend pending, + * don't queue another one. + */ + if (as->suspend_state != SUSPEND_NONE) + return; + + as->suspend_state = SUSPEND_PENDING; + suspends_pending++; + break; + } + } + queue_add_event(&as->queue, event); +} + +static void queue_event(apm_event_t event, struct apm_user *sender) +{ + struct apm_user *as; + + down_read(&user_list_lock); + list_for_each_entry(as, &apm_user_list, list) { + if (as != sender && as->reader) + queue_event_one_user(as, event); + } + up_read(&user_list_lock); + wake_up_interruptible(&apm_waitqueue); +} + +static void apm_suspend(void) +{ + struct apm_user *as; + int err = pm_suspend(PM_SUSPEND_MEM); + + /* + * Anyone on the APM queues will think we're still suspended. + * Send a message so everyone knows we're now awake again. + */ + queue_event(APM_NORMAL_RESUME, NULL); + + /* + * Finally, wake up anyone who is sleeping on the suspend. + */ + down_read(&user_list_lock); + list_for_each_entry(as, &apm_user_list, list) { + as->suspend_result = err; + as->suspend_state = SUSPEND_DONE; + } + up_read(&user_list_lock); + + wake_up(&apm_suspend_waitqueue); +} + +static ssize_t apm_read(struct file *fp, char __user *buf, size_t count, loff_t *ppos) +{ + struct apm_user *as = fp->private_data; + apm_event_t event; + int i = count, ret = 0; + + if (count < sizeof(apm_event_t)) + return -EINVAL; + + if (queue_empty(&as->queue) && fp->f_flags & O_NONBLOCK) + return -EAGAIN; + + wait_event_interruptible(apm_waitqueue, !queue_empty(&as->queue)); + + while ((i >= sizeof(event)) && !queue_empty(&as->queue)) { + event = queue_get_event(&as->queue); + + ret = -EFAULT; + if (copy_to_user(buf, &event, sizeof(event))) + break; + + if (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND) + as->suspend_state = SUSPEND_READ; + + buf += sizeof(event); + i -= sizeof(event); + } + + if (i < count) + ret = count - i; + + return ret; +} + +static unsigned int apm_poll(struct file *fp, poll_table * wait) +{ + struct apm_user *as = fp->private_data; + + poll_wait(fp, &apm_waitqueue, wait); + return queue_empty(&as->queue) ? 0 : POLLIN | POLLRDNORM; +} + +/* + * apm_ioctl - handle APM ioctl + * + * APM_IOC_SUSPEND + * This IOCTL is overloaded, and performs two functions. It is used to: + * - initiate a suspend + * - acknowledge a suspend read from /dev/apm_bios. + * Only when everyone who has opened /dev/apm_bios with write permission + * has acknowledge does the actual suspend happen. + */ +static int +apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg) +{ + struct apm_user *as = filp->private_data; + unsigned long flags; + int err = -EINVAL; + + if (!as->suser || !as->writer) + return -EPERM; + + switch (cmd) { + case APM_IOC_SUSPEND: + as->suspend_result = -EINTR; + + if (as->suspend_state == SUSPEND_READ) { + /* + * If we read a suspend command from /dev/apm_bios, + * then the corresponding APM_IOC_SUSPEND ioctl is + * interpreted as an acknowledge. + */ + as->suspend_state = SUSPEND_ACKED; + suspends_pending--; + } else { + /* + * Otherwise it is a request to suspend the system. + * Queue an event for all readers, and expect an + * acknowledge from all writers who haven't already + * acknowledged. + */ + queue_event(APM_USER_SUSPEND, as); + } + + /* + * If there are no further acknowledges required, suspend + * the system. + */ + if (suspends_pending == 0) + apm_suspend(); + + /* + * Wait for the suspend/resume to complete. If there are + * pending acknowledges, we wait here for them. + * + * Note that we need to ensure that the PM subsystem does + * not kick us out of the wait when it suspends the threads. + */ + flags = current->flags; + current->flags |= PF_NOFREEZE; + + /* + * Note: do not allow a thread which is acking the suspend + * to escape until the resume is complete. + */ + if (as->suspend_state == SUSPEND_ACKED) + wait_event(apm_suspend_waitqueue, + as->suspend_state == SUSPEND_DONE); + else + wait_event_interruptible(apm_suspend_waitqueue, + as->suspend_state == SUSPEND_DONE); + + current->flags = flags; + err = as->suspend_result; + as->suspend_state = SUSPEND_NONE; + break; + } + + return err; +} + +static int apm_release(struct inode * inode, struct file * filp) +{ + struct apm_user *as = filp->private_data; + filp->private_data = NULL; + + down_write(&user_list_lock); + list_del(&as->list); + up_write(&user_list_lock); + + /* + * We are now unhooked from the chain. As far as new + * events are concerned, we no longer exist. However, we + * need to balance suspends_pending, which means the + * possibility of sleeping. + */ + if (as->suspend_state != SUSPEND_NONE) { + suspends_pending -= 1; + if (suspends_pending == 0) + apm_suspend(); + } + + kfree(as); + return 0; +} + +static int apm_open(struct inode * inode, struct file * filp) +{ + struct apm_user *as; + + as = (struct apm_user *)kzalloc(sizeof(*as), GFP_KERNEL); + if (as) { + /* + * XXX - this is a tiny bit broken, when we consider BSD + * process accounting. If the device is opened by root, we + * instantly flag that we used superuser privs. Who knows, + * we might close the device immediately without doing a + * privileged operation -- cevans + */ + as->suser = capable(CAP_SYS_ADMIN); + as->writer = (filp->f_mode & FMODE_WRITE) == FMODE_WRITE; + as->reader = (filp->f_mode & FMODE_READ) == FMODE_READ; + + down_write(&user_list_lock); + list_add(&as->list, &apm_user_list); + up_write(&user_list_lock); + + filp->private_data = as; + } + + return as ? 0 : -ENOMEM; +} + +static struct file_operations apm_bios_fops = { + .owner = THIS_MODULE, + .read = apm_read, + .poll = apm_poll, + .ioctl = apm_ioctl, + .open = apm_open, + .release = apm_release, +}; + +static struct miscdevice apm_device = { + .minor = APM_MINOR_DEV, + .name = "apm_bios", + .fops = &apm_bios_fops +}; + + +#ifdef CONFIG_PROC_FS +/* + * Arguments, with symbols from linux/apm_bios.h. + * + * 0) Linux driver version (this will change if format changes) + * 1) APM BIOS Version. Usually 1.0, 1.1 or 1.2. + * 2) APM flags from APM Installation Check (0x00): + * bit 0: APM_16_BIT_SUPPORT + * bit 1: APM_32_BIT_SUPPORT + * bit 2: APM_IDLE_SLOWS_CLOCK + * bit 3: APM_BIOS_DISABLED + * bit 4: APM_BIOS_DISENGAGED + * 3) AC line status + * 0x00: Off-line + * 0x01: On-line + * 0x02: On backup power (BIOS >= 1.1 only) + * 0xff: Unknown + * 4) Battery status + * 0x00: High + * 0x01: Low + * 0x02: Critical + * 0x03: Charging + * 0x04: Selected battery not present (BIOS >= 1.2 only) + * 0xff: Unknown + * 5) Battery flag + * bit 0: High + * bit 1: Low + * bit 2: Critical + * bit 3: Charging + * bit 7: No system battery + * 0xff: Unknown + * 6) Remaining battery life (percentage of charge): + * 0-100: valid + * -1: Unknown + * 7) Remaining battery life (time units): + * Number of remaining minutes or seconds + * -1: Unknown + * 8) min = minutes; sec = seconds + */ +static int apm_get_info(char *buf, char **start, off_t fpos, int length) +{ + struct apm_power_info info; + char *units; + int ret; + + info.ac_line_status = 0xff; + info.battery_status = 0xff; + info.battery_flag = 0xff; + info.battery_life = -1; + info.time = -1; + info.units = -1; + + if (apm_get_power_status) + apm_get_power_status(&info); + + switch (info.units) { + default: units = "?"; break; + case 0: units = "min"; break; + case 1: units = "sec"; break; + } + + ret = sprintf(buf, "%s 1.2 0x%02x 0x%02x 0x%02x 0x%02x %d%% %d %s\n", + driver_version, APM_32_BIT_SUPPORT, + info.ac_line_status, info.battery_status, + info.battery_flag, info.battery_life, + info.time, units); + + return ret; +} +#endif + +static int kapmd(void *arg) +{ + daemonize("kapmd"); + current->flags |= PF_NOFREEZE; + + do { + apm_event_t event; + + wait_event_interruptible(kapmd_wait, + !queue_empty(&kapmd_queue) || !mips_apm_active); + + if (!mips_apm_active) + break; + + spin_lock_irq(&kapmd_queue_lock); + event = 0; + if (!queue_empty(&kapmd_queue)) + event = queue_get_event(&kapmd_queue); + spin_unlock_irq(&kapmd_queue_lock); + + switch (event) { + case 0: + break; + + case APM_LOW_BATTERY: + case APM_POWER_STATUS_CHANGE: + queue_event(event, NULL); + break; + + case APM_USER_SUSPEND: + case APM_SYS_SUSPEND: + queue_event(event, NULL); + if (suspends_pending == 0) + apm_suspend(); + break; + + case APM_CRITICAL_SUSPEND: + apm_suspend(); + break; + } + } while (1); + + complete_and_exit(&kapmd_exit, 0); +} + +static int __init apm_init(void) +{ + int ret; + + if (apm_disabled) { + printk(KERN_NOTICE "apm: disabled on user request.\n"); + return -ENODEV; + } + + mips_apm_active = 1; + + ret = kernel_thread(kapmd, NULL, CLONE_KERNEL); + if (ret < 0) { + mips_apm_active = 0; + return ret; + } + +#ifdef CONFIG_PROC_FS + create_proc_info_entry("apm", 0, NULL, apm_get_info); +#endif + + ret = misc_register(&apm_device); + if (ret != 0) { + remove_proc_entry("apm", NULL); + + mips_apm_active = 0; + wake_up(&kapmd_wait); + wait_for_completion(&kapmd_exit); + } + + return ret; +} + +static void __exit apm_exit(void) +{ + misc_deregister(&apm_device); + remove_proc_entry("apm", NULL); + + mips_apm_active = 0; + wake_up(&kapmd_wait); + wait_for_completion(&kapmd_exit); +} + +module_init(apm_init); +module_exit(apm_exit); + +MODULE_AUTHOR("Stephen Rothwell"); +MODULE_DESCRIPTION("Advanced Power Management"); +MODULE_LICENSE("GPL"); + +#ifndef MODULE +static int __init apm_setup(char *str) +{ + while ((str != NULL) && (*str != '\0')) { + if (strncmp(str, "off", 3) == 0) + apm_disabled = 1; + if (strncmp(str, "on", 2) == 0) + apm_disabled = 0; + str = strchr(str, ','); + if (str != NULL) + str += strspn(str, ", \t"); + } + return 1; +} + +__setup("apm=", apm_setup); +#endif + +/** + * apm_queue_event - queue an APM event for kapmd + * @event: APM event + * + * Queue an APM event for kapmd to process and ultimately take the + * appropriate action. Only a subset of events are handled: + * %APM_LOW_BATTERY + * %APM_POWER_STATUS_CHANGE + * %APM_USER_SUSPEND + * %APM_SYS_SUSPEND + * %APM_CRITICAL_SUSPEND + */ +void apm_queue_event(apm_event_t event) +{ + unsigned long flags; + + spin_lock_irqsave(&kapmd_queue_lock, flags); + queue_add_event(&kapmd_queue, event); + spin_unlock_irqrestore(&kapmd_queue_lock, flags); + + wake_up_interruptible(&kapmd_wait); +} +EXPORT_SYMBOL(apm_queue_event); diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 0facfaf4e950..f1bb6a2dc5fc 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -141,72 +141,72 @@ void output_thread_defines(void) void output_thread_fpu_defines(void) { offset("#define THREAD_FPR0 ", - struct task_struct, thread.fpu.hard.fpr[0]); + struct task_struct, thread.fpu.fpr[0]); offset("#define THREAD_FPR1 ", - struct task_struct, thread.fpu.hard.fpr[1]); + struct task_struct, thread.fpu.fpr[1]); offset("#define THREAD_FPR2 ", - struct task_struct, thread.fpu.hard.fpr[2]); + struct task_struct, thread.fpu.fpr[2]); offset("#define THREAD_FPR3 ", - struct task_struct, thread.fpu.hard.fpr[3]); + struct task_struct, thread.fpu.fpr[3]); offset("#define THREAD_FPR4 ", - struct task_struct, thread.fpu.hard.fpr[4]); + struct task_struct, thread.fpu.fpr[4]); offset("#define THREAD_FPR5 ", - struct task_struct, thread.fpu.hard.fpr[5]); + struct task_struct, thread.fpu.fpr[5]); offset("#define THREAD_FPR6 ", - struct task_struct, thread.fpu.hard.fpr[6]); + struct task_struct, thread.fpu.fpr[6]); offset("#define THREAD_FPR7 ", - struct task_struct, thread.fpu.hard.fpr[7]); + struct task_struct, thread.fpu.fpr[7]); offset("#define THREAD_FPR8 ", - struct task_struct, thread.fpu.hard.fpr[8]); + struct task_struct, thread.fpu.fpr[8]); offset("#define THREAD_FPR9 ", - struct task_struct, thread.fpu.hard.fpr[9]); + struct task_struct, thread.fpu.fpr[9]); offset("#define THREAD_FPR10 ", - struct task_struct, thread.fpu.hard.fpr[10]); + struct task_struct, thread.fpu.fpr[10]); offset("#define THREAD_FPR11 ", - struct task_struct, thread.fpu.hard.fpr[11]); + struct task_struct, thread.fpu.fpr[11]); offset("#define THREAD_FPR12 ", - struct task_struct, thread.fpu.hard.fpr[12]); + struct task_struct, thread.fpu.fpr[12]); offset("#define THREAD_FPR13 ", - struct task_struct, thread.fpu.hard.fpr[13]); + struct task_struct, thread.fpu.fpr[13]); offset("#define THREAD_FPR14 ", - struct task_struct, thread.fpu.hard.fpr[14]); + struct task_struct, thread.fpu.fpr[14]); offset("#define THREAD_FPR15 ", - struct task_struct, thread.fpu.hard.fpr[15]); + struct task_struct, thread.fpu.fpr[15]); offset("#define THREAD_FPR16 ", - struct task_struct, thread.fpu.hard.fpr[16]); + struct task_struct, thread.fpu.fpr[16]); offset("#define THREAD_FPR17 ", - struct task_struct, thread.fpu.hard.fpr[17]); + struct task_struct, thread.fpu.fpr[17]); offset("#define THREAD_FPR18 ", - struct task_struct, thread.fpu.hard.fpr[18]); + struct task_struct, thread.fpu.fpr[18]); offset("#define THREAD_FPR19 ", - struct task_struct, thread.fpu.hard.fpr[19]); + struct task_struct, thread.fpu.fpr[19]); offset("#define THREAD_FPR20 ", - struct task_struct, thread.fpu.hard.fpr[20]); + struct task_struct, thread.fpu.fpr[20]); offset("#define THREAD_FPR21 ", - struct task_struct, thread.fpu.hard.fpr[21]); + struct task_struct, thread.fpu.fpr[21]); offset("#define THREAD_FPR22 ", - struct task_struct, thread.fpu.hard.fpr[22]); + struct task_struct, thread.fpu.fpr[22]); offset("#define THREAD_FPR23 ", - struct task_struct, thread.fpu.hard.fpr[23]); + struct task_struct, thread.fpu.fpr[23]); offset("#define THREAD_FPR24 ", - struct task_struct, thread.fpu.hard.fpr[24]); + struct task_struct, thread.fpu.fpr[24]); offset("#define THREAD_FPR25 ", - struct task_struct, thread.fpu.hard.fpr[25]); + struct task_struct, thread.fpu.fpr[25]); offset("#define THREAD_FPR26 ", - struct task_struct, thread.fpu.hard.fpr[26]); + struct task_struct, thread.fpu.fpr[26]); offset("#define THREAD_FPR27 ", - struct task_struct, thread.fpu.hard.fpr[27]); + struct task_struct, thread.fpu.fpr[27]); offset("#define THREAD_FPR28 ", - struct task_struct, thread.fpu.hard.fpr[28]); + struct task_struct, thread.fpu.fpr[28]); offset("#define THREAD_FPR29 ", - struct task_struct, thread.fpu.hard.fpr[29]); + struct task_struct, thread.fpu.fpr[29]); offset("#define THREAD_FPR30 ", - struct task_struct, thread.fpu.hard.fpr[30]); + struct task_struct, thread.fpu.fpr[30]); offset("#define THREAD_FPR31 ", - struct task_struct, thread.fpu.hard.fpr[31]); + struct task_struct, thread.fpu.fpr[31]); offset("#define THREAD_FCR31 ", - struct task_struct, thread.fpu.hard.fcr31); + struct task_struct, thread.fpu.fcr31); linefeed; } diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index b6232d9033cb..76fd3f22c766 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -178,7 +178,7 @@ int __compute_return_epc(struct pt_regs *regs) if (is_fpu_owner()) asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); else - fcr31 = current->thread.fpu.hard.fcr31; + fcr31 = current->thread.fpu.fcr31; preempt_enable(); bit = (insn.i_format.rt >> 2); diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 2125ba5f1d9b..0cb8ed5662f3 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -302,11 +302,11 @@ static struct irqaction irq2 = { }; static struct resource pic1_io_resource = { - "pic1", 0x20, 0x3f, IORESOURCE_BUSY + .name = "pic1", .start = 0x20, .end = 0x3f, .flags = IORESOURCE_BUSY }; static struct resource pic2_io_resource = { - "pic2", 0xa0, 0xbf, IORESOURCE_BUSY + .name = "pic2", .start = 0xa0, .end = 0xbf, .flags = IORESOURCE_BUSY }; /* diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c index 8150f071f80a..a9bf6cc3abd1 100644 --- a/arch/mips/kernel/irixsig.c +++ b/arch/mips/kernel/irixsig.c @@ -260,7 +260,7 @@ irix_sigreturn(struct pt_regs *regs) for(i = 0; i < 32; i++) error |= __get_user(fregs[i], &context->fpregs[i]); - error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); + error |= __get_user(current->thread.fpu.fcr31, &context->fpcsr); } /* XXX do sigstack crapola here... XXX */ diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 9b4733c12395..1d44025188d8 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -120,11 +120,11 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) __put_user ((__u64) -1, i + (__u64 __user *) data); } + __put_user (child->thread.fpu.fcr31, data + 64); + if (cpu_has_fpu) { unsigned int flags, tmp; - __put_user (child->thread.fpu.hard.fcr31, data + 64); - preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); @@ -142,7 +142,6 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) preempt_enable(); __put_user (tmp, data + 65); } else { - __put_user (child->thread.fpu.soft.fcr31, data + 64); __put_user ((__u32) 0, data + 65); } @@ -162,10 +161,7 @@ int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) for (i = 0; i < 32; i++) __get_user (fregs[i], i + (__u64 __user *) data); - if (cpu_has_fpu) - __get_user (child->thread.fpu.hard.fcr31, data + 64); - else - __get_user (child->thread.fpu.soft.fcr31, data + 64); + __get_user (child->thread.fpu.fcr31, data + 64); /* FIR may not be written. */ @@ -241,10 +237,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) tmp = regs->lo; break; case FPC_CSR: - if (cpu_has_fpu) - tmp = child->thread.fpu.hard.fcr31; - else - tmp = child->thread.fpu.soft.fcr31; + tmp = child->thread.fpu.fcr31; break; case FPC_EIR: { /* implementation / version register */ unsigned int flags; @@ -336,9 +329,9 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) if (!tsk_used_math(child)) { /* FP not yet used */ - memset(&child->thread.fpu.hard, ~0, - sizeof(child->thread.fpu.hard)); - child->thread.fpu.hard.fcr31 = 0; + memset(&child->thread.fpu, ~0, + sizeof(child->thread.fpu)); + child->thread.fpu.fcr31 = 0; } #ifdef CONFIG_32BIT /* @@ -369,10 +362,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) regs->lo = data; break; case FPC_CSR: - if (cpu_has_fpu) - child->thread.fpu.hard.fcr31 = data; - else - child->thread.fpu.soft.fcr31 = data; + child->thread.fpu.fcr31 = data; break; case DSP_BASE ... DSP_BASE + 5: { dspreg_t *dregs; diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index 8704dc0496ea..f40ecd8be05f 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -166,10 +166,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) tmp = regs->lo; break; case FPC_CSR: - if (cpu_has_fpu) - tmp = child->thread.fpu.hard.fcr31; - else - tmp = child->thread.fpu.soft.fcr31; + tmp = child->thread.fpu.fcr31; break; case FPC_EIR: { /* implementation / version register */ unsigned int flags; @@ -288,9 +285,9 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) if (!tsk_used_math(child)) { /* FP not yet used */ - memset(&child->thread.fpu.hard, ~0, - sizeof(child->thread.fpu.hard)); - child->thread.fpu.hard.fcr31 = 0; + memset(&child->thread.fpu, ~0, + sizeof(child->thread.fpu)); + child->thread.fpu.fcr31 = 0; } /* * The odd registers are actually the high order bits @@ -318,10 +315,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) regs->lo = data; break; case FPC_CSR: - if (cpu_has_fpu) - child->thread.fpu.hard.fcr31 = data; - else - child->thread.fpu.soft.fcr31 = data; + child->thread.fpu.fcr31 = data; break; case DSP_BASE ... DSP_BASE + 5: { dspreg_t *dregs; diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 0b1b54acee9f..db94e556fc97 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -75,8 +75,8 @@ and t0, t0, t1 LONG_S t0, ST_OFF(t3) - fpu_save_double a0 t1 t0 t2 # c0_status passed in t1 - # clobbers t0 and t2 + fpu_save_double a0 t0 t1 # c0_status passed in t0 + # clobbers t1 1: /* @@ -129,9 +129,9 @@ */ LEAF(_save_fp) #ifdef CONFIG_64BIT - mfc0 t1, CP0_STATUS + mfc0 t0, CP0_STATUS #endif - fpu_save_double a0 t1 t0 t2 # clobbers t1 + fpu_save_double a0 t0 t1 # clobbers t1 jr ra END(_save_fp) @@ -139,7 +139,10 @@ LEAF(_save_fp) * Restore a thread's fp context. */ LEAF(_restore_fp) - fpu_restore_double a0, t1 # clobbers t1 +#ifdef CONFIG_64BIT + mfc0 t0, CP0_STATUS +#endif + fpu_restore_double a0 t0 t1 # clobbers t1 jr ra END(_restore_fp) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 397a70e651b5..bfcec8d9bfe4 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -442,6 +442,48 @@ static inline void bootmem_init(void) #endif /* CONFIG_BLK_DEV_INITRD */ } +/* + * arch_mem_init - initialize memory managment subsystem + * + * o plat_mem_setup() detects the memory configuration and will record detected + * memory areas using add_memory_region. + * o parse_cmdline_early() parses the command line for mem= options which, + * iff detected, will override the results of the automatic detection. + * + * At this stage the memory configuration of the system is known to the + * kernel but generic memory managment system is still entirely uninitialized. + * + * o bootmem_init() + * o sparse_init() + * o paging_init() + * + * At this stage the bootmem allocator is ready to use. + * + * NOTE: historically plat_mem_setup did the entire platform initialization. + * This was rather impractical because it meant plat_mem_setup had to + * get away without any kind of memory allocator. To keep old code from + * breaking plat_setup was just renamed to plat_setup and a second platform + * initialization hook for anything else was introduced. + */ + +extern void plat_mem_setup(void); + +static void __init arch_mem_init(char **cmdline_p) +{ + /* call board setup routine */ + plat_mem_setup(); + + strlcpy(command_line, arcs_cmdline, sizeof(command_line)); + strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE); + + *cmdline_p = command_line; + + parse_cmdline_early(); + bootmem_init(); + sparse_init(); + paging_init(); +} + static inline void resource_init(void) { int i; @@ -495,8 +537,6 @@ static inline void resource_init(void) #undef MAXMEM #undef MAXMEM_PFN -extern void plat_setup(void); - void __init setup_arch(char **cmdline_p) { cpu_probe(); @@ -511,18 +551,8 @@ void __init setup_arch(char **cmdline_p) #endif #endif - /* call board setup routine */ - plat_setup(); + arch_mem_init(cmdline_p); - strlcpy(command_line, arcs_cmdline, sizeof(command_line)); - strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE); - - *cmdline_p = command_line; - - parse_cmdline_early(); - bootmem_init(); - sparse_init(); - paging_init(); resource_init(); #ifdef CONFIG_SMP plat_smp_setup(); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a7564b08eb4d..ad16eceb24dd 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -65,7 +65,7 @@ extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, - struct mips_fpu_soft_struct *ctx); + struct mips_fpu_struct *ctx); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); @@ -600,8 +600,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) preempt_enable(); /* Run the emulator */ - sig = fpu_emulator_cop1Handler (regs, - ¤t->thread.fpu.soft); + sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu); preempt_disable(); @@ -610,7 +609,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) * We can't allow the emulated instruction to leave any of * the cause bit set in $fcr31. */ - current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X; + current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; /* Restore the hardware register state */ restore_fp(current); @@ -755,7 +754,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) if (!cpu_has_fpu) { int sig = fpu_emulator_cop1Handler(regs, - ¤t->thread.fpu.soft); + ¤t->thread.fpu); if (sig) force_sig(sig, current); #ifdef CONFIG_MIPS_MT_FPAFF diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index bb70a8240e61..3f64277429e4 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -155,7 +155,7 @@ void __init serial_init(void) } #endif -void __init plat_setup(void) +void __init plat_mem_setup(void) { int i; lasat_misc = &lasat_misc_info[mips_machtype]; diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index cf12caf80774..b225543f5302 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -7,4 +7,7 @@ lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \ obj-y += iomap.o +# libgcc-style stuff needed in the kernel +lib-y += ashldi3.o ashrdi3.o lshrdi3.o + EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/lib/ashldi3.c b/arch/mips/lib/ashldi3.c new file mode 100644 index 000000000000..beb80f316095 --- /dev/null +++ b/arch/mips/lib/ashldi3.c @@ -0,0 +1,29 @@ +#include <linux/module.h> + +#include "libgcc.h" + +long long __ashldi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.low = 0; + w.s.high = (unsigned int) uu.s.low << -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.low >> bm; + + w.s.low = (unsigned int) uu.s.low << b; + w.s.high = ((unsigned int) uu.s.high << b) | carries; + } + + return w.ll; +} + +EXPORT_SYMBOL(__ashldi3); diff --git a/arch/mips/lib/ashrdi3.c b/arch/mips/lib/ashrdi3.c new file mode 100644 index 000000000000..c884a912b660 --- /dev/null +++ b/arch/mips/lib/ashrdi3.c @@ -0,0 +1,31 @@ +#include <linux/module.h> + +#include "libgcc.h" + +long long __ashrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >> 31; + w.s.low = uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} + +EXPORT_SYMBOL(__ashrdi3); diff --git a/arch/mips/lib/libgcc.h b/arch/mips/lib/libgcc.h new file mode 100644 index 000000000000..3f19d1c5d942 --- /dev/null +++ b/arch/mips/lib/libgcc.h @@ -0,0 +1,26 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { + int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { + int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union +{ + struct DWstruct s; + long long ll; +} DWunion; + +#endif /* __ASM_LIBGCC_H */ diff --git a/arch/mips/lib/lshrdi3.c b/arch/mips/lib/lshrdi3.c new file mode 100644 index 000000000000..dcf8d6810b7c --- /dev/null +++ b/arch/mips/lib/lshrdi3.c @@ -0,0 +1,29 @@ +#include <linux/module.h> + +#include "libgcc.h" + +long long __lshrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.high = 0; + w.s.low = (unsigned int) uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = (unsigned int) uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} + +EXPORT_SYMBOL(__lshrdi3); diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index aa5818a0d884..3f0d5d26d506 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -60,15 +60,15 @@ /* Function which emulates a floating point instruction. */ -static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *, +static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, mips_instruction); #if __mips >= 4 && __mips != 32 static int fpux_emu(struct pt_regs *, - struct mips_fpu_soft_struct *, mips_instruction); + struct mips_fpu_struct *, mips_instruction); #endif -/* Further private data for which no space exists in mips_fpu_soft_struct */ +/* Further private data for which no space exists in mips_fpu_struct */ struct mips_fpu_emulator_stats fpuemustats; @@ -203,7 +203,7 @@ static int isBranchInstr(mips_instruction * i) * Two instructions if the instruction is in a branch delay slot. */ -static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) +static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) { mips_instruction ir; void * emulpc, *contpc; @@ -595,7 +595,7 @@ DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,); DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); -static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, +static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, mips_instruction ir) { unsigned rcsr = 0; /* resulting csr */ @@ -759,7 +759,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, /* * Emulate a single COP1 arithmetic instruction. */ -static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, +static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, mips_instruction ir) { int rfmt; /* resulting format */ @@ -1233,8 +1233,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, return 0; } -int fpu_emulator_cop1Handler(struct pt_regs *xcp, - struct mips_fpu_soft_struct *ctx) +int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx) { unsigned long oldepc, prevepc; mips_instruction insn; diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h index 171f177c0f88..dd917332792c 100644 --- a/arch/mips/math-emu/ieee754.h +++ b/arch/mips/math-emu/ieee754.h @@ -329,7 +329,7 @@ struct _ieee754_csr { unsigned pad0:7; #endif }; -#define ieee754_csr (*(struct _ieee754_csr *)(¤t->thread.fpu.soft.fcr31)) +#define ieee754_csr (*(struct _ieee754_csr *)(¤t->thread.fpu.fcr31)) static inline unsigned ieee754_getrm(void) { diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c index d187ab71c2ff..56ca0c6a7178 100644 --- a/arch/mips/math-emu/kernel_linkage.c +++ b/arch/mips/math-emu/kernel_linkage.c @@ -39,9 +39,9 @@ void fpu_emulator_init_fpu(void) printk("Algorithmics/MIPS FPU Emulator v1.5\n"); } - current->thread.fpu.soft.fcr31 = 0; + current->thread.fpu.fcr31 = 0; for (i = 0; i < 32; i++) { - current->thread.fpu.soft.fpr[i] = SIGNALLING_NAN; + current->thread.fpu.fpr[i] = SIGNALLING_NAN; } } @@ -59,10 +59,9 @@ int fpu_emulator_save_context(struct sigcontext *sc) for (i = 0; i < 32; i++) { err |= - __put_user(current->thread.fpu.soft.fpr[i], - &sc->sc_fpregs[i]); + __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); } - err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); return err; } @@ -74,10 +73,9 @@ int fpu_emulator_restore_context(struct sigcontext *sc) for (i = 0; i < 32; i++) { err |= - __get_user(current->thread.fpu.soft.fpr[i], - &sc->sc_fpregs[i]); + __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); } - err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); return err; } @@ -94,10 +92,9 @@ int fpu_emulator_save_context32(struct sigcontext32 *sc) for (i = 0; i < 32; i+=2) { err |= - __put_user(current->thread.fpu.soft.fpr[i], - &sc->sc_fpregs[i]); + __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); } - err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); return err; } @@ -109,10 +106,9 @@ int fpu_emulator_restore_context32(struct sigcontext32 *sc) for (i = 0; i < 32; i+=2) { err |= - __get_user(current->thread.fpu.soft.fpr[i], - &sc->sc_fpregs[i]); + __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); } - err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); return err; } diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c index c20d401ecf80..8cc9effcb832 100644 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ b/arch/mips/mips-boards/atlas/atlas_setup.c @@ -50,7 +50,7 @@ const char *get_system_type(void) return "MIPS Atlas"; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { mips_pcibios_init(); diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c index bc4d093685bb..fd492562584a 100644 --- a/arch/mips/mips-boards/generic/memory.c +++ b/arch/mips/mips-boards/generic/memory.c @@ -76,6 +76,15 @@ struct prom_pmemblock * __init prom_getmdesc(void) memsize = simple_strtol(memsize_str, NULL, 0); } } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* + * SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + * word of physical memory + */ + memsize -= PAGE_SIZE; +#endif + memset(mdesc, 0, sizeof(mdesc)); mdesc[0].type = yamon_dontuse; diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index b8488aab6df1..0766e434b6bd 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -53,11 +53,11 @@ extern void kgdb_config(void); #endif struct resource standard_io_resources[] = { - { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, - { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, - { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, - { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, - { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, + { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY }, + { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY }, + { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY }, + { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY }, + { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY }, }; #ifdef CONFIG_MTD @@ -111,7 +111,7 @@ void __init fd_activate(void) } #endif -void __init plat_setup(void) +void __init plat_mem_setup(void) { unsigned int i; diff --git a/arch/mips/mips-boards/malta/malta_smp.c b/arch/mips/mips-boards/malta/malta_smp.c index 6c6c8eeedbce..cf967170fe29 100644 --- a/arch/mips/mips-boards/malta/malta_smp.c +++ b/arch/mips/mips-boards/malta/malta_smp.c @@ -34,25 +34,6 @@ void core_send_ipi(int cpu, unsigned int action) } /* - * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map - */ - -void __init prom_build_cpu_map(void) -{ - int nextslot; - - /* - * As of November, 2004, MIPSsim only simulates one core - * at a time. However, that core may be a MIPS MT core - * with multiple virtual processors and thread contexts. - */ - - if (read_c0_config3() & (1<<2)) { - nextslot = mipsmt_build_cpu_map(1); - } -} - -/* * Platform "CPU" startup hook */ diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c index 4266ce445174..6430f11f3a95 100644 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ b/arch/mips/mips-boards/sead/sead_setup.c @@ -45,7 +45,7 @@ const char *get_system_type(void) return "MIPS SEAD"; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { ioport_resource.end = 0x7fffffff; diff --git a/arch/mips/mips-boards/sim/sim_setup.c b/arch/mips/mips-boards/sim/sim_setup.c index a2fd62997ca3..15a5dac4ae19 100644 --- a/arch/mips/mips-boards/sim/sim_setup.c +++ b/arch/mips/mips-boards/sim/sim_setup.c @@ -50,7 +50,7 @@ const char *get_system_type(void) return "MIPSsim"; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { set_io_port_base(0xbfd00000); diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c index b7084e7c4bf9..004070956cca 100644 --- a/arch/mips/mips-boards/sim/sim_smp.c +++ b/arch/mips/mips-boards/sim/sim_smp.c @@ -51,27 +51,6 @@ void core_send_ipi(int cpu, unsigned int action) } /* - * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map - */ - -void __init prom_build_cpu_map(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - int nextslot; - - /* - * As of November, 2004, MIPSsim only simulates one core - * at a time. However, that core may be a MIPS MT core - * with multiple virtual processors and thread contexts. - */ - - if (read_c0_config3() & (1<<2)) { - nextslot = mipsmt_build_cpu_map(1); - } -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -/* * Platform "CPU" startup hook */ diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 9dca099ba16b..965cb4c4359d 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -413,7 +413,6 @@ out: return ret; } -extern void __init sanitize_tlb_entries(void); static void __init probe_tlb(unsigned long config) { struct cpuinfo_mips *c = ¤t_cpu_data; diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 1379c76845dc..df1485501ce6 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -359,7 +359,7 @@ static __init int __init ja_pci_init(void) arch_initcall(ja_pci_init); -void __init plat_setup(void) +void __init plat_mem_setup(void) { unsigned int tmpword; diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c index c69195234309..8c53490ba6f1 100644 --- a/arch/mips/momentum/ocelot_3/setup.c +++ b/arch/mips/momentum/ocelot_3/setup.c @@ -313,7 +313,7 @@ static __init int __init ja_pci_init(void) arch_initcall(ja_pci_init); -void __init plat_setup(void) +void __init plat_mem_setup(void) { unsigned int tmpword; diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index a3e6f5575592..257e1d1b72dd 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c @@ -231,7 +231,7 @@ void momenco_time_init(void) rtc_mips_set_time = m48t37y_set_time; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { unsigned int tmpword; diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c index fed4e8eee116..72143ab1e900 100644 --- a/arch/mips/momentum/ocelot_g/setup.c +++ b/arch/mips/momentum/ocelot_g/setup.c @@ -162,7 +162,7 @@ static void __init setup_l3cache(unsigned long size) printk("Done\n"); } -void __init plat_setup(void) +void __init plat_mem_setup(void) { void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); unsigned int tmpword; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 16205b587338..465778c5d816 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -18,12 +18,12 @@ obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o +obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o # # These are still pretty much in the old state, watch, go blind. # -obj-$(CONFIG_DDB5074) += fixup-ddb5074.o pci-ddb5074.o ops-ddb5074.o -obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o +obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o @@ -43,7 +43,7 @@ obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ pci-yosemite.o -obj-$(CONFIG_SGI_IP27) += pci-ip27.o +obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o @@ -57,3 +57,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o +obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c deleted file mode 100644 index 5a4a7c239c42..000000000000 --- a/arch/mips/pci/fixup-ddb5074.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * It's nice to have the LEDs on the GPIO pins available for debugging - */ -static void ddb5074_fixup(struct pci_dev *dev) -{ - extern struct pci_dev *pci_pmu; - u8 t8; - - pci_pmu = dev; /* for LEDs D2 and D3 */ - /* Program the lines for LEDs D2 and D3 to output */ - pci_read_config_byte(dev, 0x7d, &t8); - t8 |= 0xc0; - pci_write_config_byte(dev, 0x7d, t8); - /* Turn LEDs D2 and D3 off */ - pci_read_config_byte(dev, 0x7e, &t8); - t8 |= 0xc0; - pci_write_config_byte(dev, 0x7e, t8); -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, - ddb5074_fixup); diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c new file mode 100644 index 000000000000..3a34cd0efd6b --- /dev/null +++ b/arch/mips/pci/fixup-emma2rh.c @@ -0,0 +1,102 @@ +/* + * arch/mips/pci/fixup-emma2rh.c + * This file defines the PCI configration. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/pci.h> + +#include <asm/bootinfo.h> +#include <asm/debug.h> + +#include <asm/emma2rh/emma2rh.h> + +#define EMMA2RH_PCI_HOST_SLOT 0x09 +#define EMMA2RH_USB_SLOT 0x03 +#define PCI_DEVICE_ID_NEC_EMMA2RH 0x014b /* EMMA2RH PCI Host */ + +/* + * we fix up irqs based on the slot number. + * The first entry is at AD:11. + * Fortunately this works because, although we have two pci buses, + * they all have different slot numbers (except for rockhopper slot 20 + * which is handled below). + * + */ + +#define MAX_SLOT_NUM 10 +static unsigned char irq_map[][5] __initdata = { + [3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC, + MARKEINS_PCI_IRQ_INTD, 0,}, + [4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,}, + [5] = {0, 0, 0, 0, 0,}, + [6] = {0, MARKEINS_PCI_IRQ_INTC, MARKEINS_PCI_IRQ_INTD, + MARKEINS_PCI_IRQ_INTA, MARKEINS_PCI_IRQ_INTB,}, +}; + +static void __devinit nec_usb_controller_fixup(struct pci_dev *dev) +{ + if (PCI_SLOT(dev->devfn) == EMMA2RH_USB_SLOT) + /* on board USB controller configuration */ + pci_write_config_dword(dev, 0xe4, 1 << 5); +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, + nec_usb_controller_fixup); + +/* + * Prevent the PCI layer from seeing the resources allocated to this device + * if it is the host bridge by marking it as such. These resources are of + * no consequence to the PCI layer (they are handled elsewhere). + */ +static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev) +{ + int i; + + if (PCI_SLOT(dev->devfn) == EMMA2RH_PCI_HOST_SLOT) { + dev->class &= 0xff; + dev->class |= PCI_CLASS_BRIDGE_HOST << 8; + for (i = 0; i < PCI_NUM_RESOURCES; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH, + emma2rh_pci_host_fixup); + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return irq_map[slot][pin]; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c new file mode 100644 index 000000000000..1da696d43f00 --- /dev/null +++ b/arch/mips/pci/fixup-excite.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <excite.h> + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (pin == 0) + return -1; + + return USB_IRQ; /* USB controller is the only PCI device */ +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c new file mode 100644 index 000000000000..3357c1300bb1 --- /dev/null +++ b/arch/mips/pci/fixup-wrppmc.c @@ -0,0 +1,37 @@ +/* + * fixup-wrppmc.c: PPMC board specific PCI fixup + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com) + */ +#include <linux/init.h> +#include <linux/pci.h> +#include <asm/gt64120.h> + +/* PCI interrupt pins */ +#define PCI_INTA 1 +#define PCI_INTB 2 +#define PCI_INTC 3 +#define PCI_INTD 4 + +#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */ + +static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = { + /* 0 INTA INTB INTC INTD */ + [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */ + [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, +}; + +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return pci_irq_tab[slot][pin]; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c new file mode 100644 index 000000000000..1fa09929cd7a --- /dev/null +++ b/arch/mips/pci/ops-bridge.c @@ -0,0 +1,306 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include <linux/pci.h> +#include <asm/paccess.h> +#include <asm/pci/bridge.h> +#include <asm/sn/arch.h> +#include <asm/sn/intr.h> +#include <asm/sn/sn0/hub.h> + +/* + * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is + * not really documented, so right now I can't write code which uses it. + * Therefore we use type 0 accesses for now even though they won't work + * correcly for PCI-to-PCI bridges. + * + * The function is complicated by the ultimate brokeness of the IOC3 chip + * which is used in SGI systems. The IOC3 can only handle 32-bit PCI + * accesses and does only decode parts of it's address space. + */ + +static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * value) +{ + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); + bridge_t *bridge = bc->base; + int slot = PCI_SLOT(devfn); + int fn = PCI_FUNC(devfn); + volatile void *addr; + u32 cf, shift, mask; + int res; + + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to look at it for real ... + */ + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) + goto oh_my_gawd; + + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; + + if (size == 1) + res = get_dbe(*value, (u8 *) addr); + else if (size == 2) + res = get_dbe(*value, (u16 *) addr); + else + res = get_dbe(*value, (u32 *) addr); + + return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; + +oh_my_gawd: + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to look at the wrong register. + */ + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { + *value = 0; + return PCIBIOS_SUCCESSFUL; + } + + /* + * IOC3 is fucked fucked beyond believe ... Don't try to access + * anything but 32-bit words ... + */ + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; + + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + shift = ((where & 3) << 3); + mask = (0xffffffffU >> ((4 - size) << 3)); + *value = (cf >> shift) & mask; + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * value) +{ + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); + bridge_t *bridge = bc->base; + int busno = bus->number; + int slot = PCI_SLOT(devfn); + int fn = PCI_FUNC(devfn); + volatile void *addr; + u32 cf, shift, mask; + int res; + + bridge->b_pci_cfg = (busno << 16) | (slot << 11); + addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to look at it for real ... + */ + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) + goto oh_my_gawd; + + bridge->b_pci_cfg = (busno << 16) | (slot << 11); + addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; + + if (size == 1) + res = get_dbe(*value, (u8 *) addr); + else if (size == 2) + res = get_dbe(*value, (u16 *) addr); + else + res = get_dbe(*value, (u32 *) addr); + + return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; + +oh_my_gawd: + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to look at the wrong register. + */ + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { + *value = 0; + return PCIBIOS_SUCCESSFUL; + } + + /* + * IOC3 is fucked fucked beyond believe ... Don't try to access + * anything but 32-bit words ... + */ + bridge->b_pci_cfg = (busno << 16) | (slot << 11); + addr = &bridge->b_type1_cfg.c[(fn << 8) | where]; + + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + shift = ((where & 3) << 3); + mask = (0xffffffffU >> ((4 - size) << 3)); + *value = (cf >> shift) & mask; + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * value) +{ + if (bus->number > 0) + return pci_conf1_read_config(bus, devfn, where, size, value); + + return pci_conf0_read_config(bus, devfn, where, size, value); +} + +static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); + bridge_t *bridge = bc->base; + int slot = PCI_SLOT(devfn); + int fn = PCI_FUNC(devfn); + volatile void *addr; + u32 cf, shift, mask, smask; + int res; + + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to look at it for real ... + */ + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) + goto oh_my_gawd; + + addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; + + if (size == 1) { + res = put_dbe(value, (u8 *) addr); + } else if (size == 2) { + res = put_dbe(value, (u16 *) addr); + } else { + res = put_dbe(value, (u32 *) addr); + } + + if (res) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; + +oh_my_gawd: + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to touch the wrong register. + */ + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) + return PCIBIOS_SUCCESSFUL; + + /* + * IOC3 is fucked fucked beyond believe ... Don't try to access + * anything but 32-bit words ... + */ + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; + + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + shift = ((where & 3) << 3); + mask = (0xffffffffU >> ((4 - size) << 3)); + smask = mask << shift; + + cf = (cf & ~smask) | ((value & mask) << shift); + if (put_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); + bridge_t *bridge = bc->base; + int slot = PCI_SLOT(devfn); + int fn = PCI_FUNC(devfn); + int busno = bus->number; + volatile void *addr; + u32 cf, shift, mask, smask; + int res; + + bridge->b_pci_cfg = (busno << 16) | (slot << 11); + addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to look at it for real ... + */ + if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) + goto oh_my_gawd; + + addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; + + if (size == 1) { + res = put_dbe(value, (u8 *) addr); + } else if (size == 2) { + res = put_dbe(value, (u16 *) addr); + } else { + res = put_dbe(value, (u32 *) addr); + } + + if (res) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; + +oh_my_gawd: + + /* + * IOC3 is fucked fucked beyond believe ... Don't even give the + * generic PCI code a chance to touch the wrong register. + */ + if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) + return PCIBIOS_SUCCESSFUL; + + /* + * IOC3 is fucked fucked beyond believe ... Don't try to access + * anything but 32-bit words ... + */ + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; + + if (get_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + shift = ((where & 3) << 3); + mask = (0xffffffffU >> ((4 - size) << 3)); + smask = mask << shift; + + cf = (cf & ~smask) | ((value & mask) << shift); + if (put_dbe(cf, (u32 *) addr)) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + if (bus->number > 0) + return pci_conf1_write_config(bus, devfn, where, size, value); + + return pci_conf0_write_config(bus, devfn, where, size, value); +} + +struct pci_ops bridge_pci_ops = { + .read = pci_read_config, + .write = pci_write_config, +}; diff --git a/arch/mips/pci/ops-ddb5074.c b/arch/mips/pci/ops-ddb5074.c deleted file mode 100644 index 89f97bef4fc4..000000000000 --- a/arch/mips/pci/ops-ddb5074.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5476/pci_ops.c - * Define the pci_ops for DB5477. - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven <geert@sonycom.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include <asm/addrspace.h> -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -/* - * config_swap structure records what set of pdar/pmr are used - * to access pci config space. It also provides a place hold the - * original values for future restoring. - */ -struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; -}; - -/* - * On DDB5476, we have one set of swap registers - */ -struct pci_config_swap ext_pci_swap = { - DDB_PCIW0, - DDB_PCIINIT0, - DDB_PCI_CONFIG_BASE, - DDB_PCI_CONFIG_SIZE -}; - -static int pci_config_workaround = 1; - -/* - * access config space - */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ - u32 slot_num) -{ - u32 pci_addr = 0; - u32 pciinit_offset = 0; - u32 virt_addr = swap->config_base; - u32 option; - - if (pci_config_workaround) { - if (slot_num == 5) - slot_num = 14; - } else { - if (slot_num == 5) - return DDB_BASE + DDB_PCI_BASE; - } - - /* minimum pdar (window) size is 2MB */ - db_assert(swap->config_size >= (2 << 20)); - - db_assert(slot_num < (1 << 5)); - db_assert(bus < (1 << 8)); - - /* backup registers */ - swap->pdar_backup = ddb_in32(swap->pdar); - swap->pmr_backup = ddb_in32(swap->pmr); - - /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ - 0, /* not on local memory bus */ - 0); /* not visible from PCI bus (N/A) */ - - /* - * calcuate the absolute pci config addr; - * according to the spec, we start scanning from adr:11 (0x800) - */ - if (bus == 0) { - /* type 0 config */ - pci_addr = 0x00040000 << slot_num; - } else { - /* type 1 config */ - pci_addr = 0x00040000 << slot_num; - panic - ("ddb_access_config_base: we don't support type 1 config Yet"); - } - - /* - * if pci_addr is less than pci config window size, we set - * pciinit_offset to 0 and adjust the virt_address. - * Otherwise we will try to adjust pciinit_offset. - */ - if (pci_addr < swap->config_size) { - virt_addr = KSEG1ADDR(swap->config_base + pci_addr); - pciinit_offset = 0; - } else { - db_assert((pci_addr & (swap->config_size - 1)) == 0); - virt_addr = KSEG1ADDR(swap->config_base); - pciinit_offset = pci_addr; - } - - /* set the pmr register */ - option = DDB_PCI_ACCESS_32; - if (bus != 0) - option |= DDB_PCI_CFGTYPE1; - ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); - - return virt_addr; -} - -static inline void ddb_close_config_base(struct pci_config_swap *swap) -{ - ddb_out32(swap->pdar, swap->pdar_backup); - ddb_out32(swap->pmr, swap->pmr_backup); -} - -static int read_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u32 * val) -{ - u32 bus, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; - } - - slot_num = PCI_SLOT(dev->devfn); - func_num = PCI_FUNC(dev->devfn); - base = ddb_access_config_base(swap, bus, slot_num); - *val = *(volatile u32 *) (base + (func_num << 8) + where); - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int read_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u16 * val) -{ - int status; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 2) - result >>= 16; - *val = result & 0xffff; - return status; -} - -static int read_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u8 * val) -{ - int status; - u32 result; - - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 1) - result >>= 8; - if (where & 2) - result >>= 16; - *val = result & 0xff; - return status; -} - -static int write_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u32 val) -{ - u32 bus, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; - } - - slot_num = PCI_SLOT(dev->devfn); - func_num = PCI_FUNC(dev->devfn); - base = ddb_access_config_base(swap, bus, slot_num); - *(volatile u32 *) (base + (func_num << 8) + where) = val; - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u16 val) -{ - int status, shift = 0; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); -} - -static int write_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u8 val) -{ - int status, shift = 0; - u32 result; - - status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); -} - -#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ -static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \ -{ \ - return rw##_config_##unitname(pciswap, \ - dev, \ - where, \ - val); \ -} - -MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap) - MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) - MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) - - MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) - MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) - MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) - -struct pci_ops ddb5476_ext_pci_ops = { - extpci_read_config_byte, - extpci_read_config_word, - extpci_read_config_dword, - extpci_write_config_byte, - extpci_write_config_word, - extpci_write_config_dword -}; diff --git a/arch/mips/pci/ops-ddb5476.c b/arch/mips/pci/ops-ddb5476.c deleted file mode 100644 index 12da58e75ec7..000000000000 --- a/arch/mips/pci/ops-ddb5476.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5476/pci_ops.c - * Define the pci_ops for DB5477. - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven <geert@sonycom.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include <asm/addrspace.h> -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -/* - * config_swap structure records what set of pdar/pmr are used - * to access pci config space. It also provides a place hold the - * original values for future restoring. - */ -struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; -}; - -/* - * On DDB5476, we have one set of swap registers - */ -struct pci_config_swap ext_pci_swap = { - DDB_PCIW0, - DDB_PCIINIT0, - DDB_PCI_CONFIG_BASE, - DDB_PCI_CONFIG_SIZE -}; - -static int pci_config_workaround = 1; - -/* - * access config space - */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ - u32 slot_num) -{ - u32 pci_addr = 0; - u32 pciinit_offset = 0; - u32 virt_addr = swap->config_base; - u32 option; - - if (pci_config_workaround) { - /* [jsun] work around Vrc5476 controller itself, returnning - * slot 0 essentially makes vrc5476 invisible - */ - if (slot_num == 12) - slot_num = 0; - -#if 0 - /* BUG : skip P2P bridge for now */ - if (slot_num == 5) - slot_num = 0; -#endif - - } else { - /* now we have to be hornest, returning the true - * PCI config headers for vrc5476 - */ - if (slot_num == 12) { - swap->pdar_backup = ddb_in32(swap->pdar); - swap->pmr_backup = ddb_in32(swap->pmr); - return DDB_BASE + DDB_PCI_BASE; - } - } - - /* minimum pdar (window) size is 2MB */ - db_assert(swap->config_size >= (2 << 20)); - - db_assert(slot_num < (1 << 5)); - db_assert(bus < (1 << 8)); - - /* backup registers */ - swap->pdar_backup = ddb_in32(swap->pdar); - swap->pmr_backup = ddb_in32(swap->pmr); - - /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ - 0, /* not on local memory bus */ - 0); /* not visible from PCI bus (N/A) */ - - /* - * calcuate the absolute pci config addr; - * according to the spec, we start scanning from adr:11 (0x800) - */ - if (bus == 0) { - /* type 0 config */ - pci_addr = 0x800 << slot_num; - } else { - /* type 1 config */ - pci_addr = (bus << 16) | (slot_num << 11); - /* panic("ddb_access_config_base: we don't support type 1 config Yet"); */ - } - - /* - * if pci_addr is less than pci config window size, we set - * pciinit_offset to 0 and adjust the virt_address. - * Otherwise we will try to adjust pciinit_offset. - */ - if (pci_addr < swap->config_size) { - virt_addr = KSEG1ADDR(swap->config_base + pci_addr); - pciinit_offset = 0; - } else { - db_assert((pci_addr & (swap->config_size - 1)) == 0); - virt_addr = KSEG1ADDR(swap->config_base); - pciinit_offset = pci_addr; - } - - /* set the pmr register */ - option = DDB_PCI_ACCESS_32; - if (bus != 0) - option |= DDB_PCI_CFGTYPE1; - ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); - - return virt_addr; -} - -static inline void ddb_close_config_base(struct pci_config_swap *swap) -{ - ddb_out32(swap->pdar, swap->pdar_backup); - ddb_out32(swap->pmr, swap->pmr_backup); -} - -static int read_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u32 * val) -{ - u32 bus, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; - } - - slot_num = PCI_SLOT(dev->devfn); - func_num = PCI_FUNC(dev->devfn); - base = ddb_access_config_base(swap, bus, slot_num); - *val = *(volatile u32 *) (base + (func_num << 8) + where); - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int read_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u16 * val) -{ - int status; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 2) - result >>= 16; - *val = result & 0xffff; - return status; -} - -static int read_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u8 * val) -{ - int status; - u32 result; - - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 1) - result >>= 8; - if (where & 2) - result >>= 16; - *val = result & 0xff; - return status; -} - -static int write_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u32 val) -{ - u32 bus, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (dev->bus->parent != NULL) { - bus = dev->bus->number; - db_assert(bus != 0); - } else { - bus = 0; - } - - slot_num = PCI_SLOT(dev->devfn); - func_num = PCI_FUNC(dev->devfn); - base = ddb_access_config_base(swap, bus, slot_num); - *(volatile u32 *) (base + (func_num << 8) + where) = val; - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u16 val) -{ - int status, shift = 0; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); -} - -static int write_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, u32 where, u8 val) -{ - int status, shift = 0; - u32 result; - - status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); -} - -#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ -static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \ -{ \ - return rw##_config_##unitname(pciswap, \ - dev, \ - where, \ - val); \ -} - -MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap) - MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) - MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) - - MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) - MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) - MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) - -struct pci_ops ddb5476_ext_pci_ops = { - extpci_read_config_byte, - extpci_read_config_word, - extpci_read_config_dword, - extpci_write_config_byte, - extpci_write_config_word, - extpci_write_config_dword -}; diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c new file mode 100644 index 000000000000..e21b11bf66bc --- /dev/null +++ b/arch/mips/pci/ops-emma2rh.c @@ -0,0 +1,186 @@ +/* + * arch/mips/pci/ops-emma2rh.c + * This file defines the PCI operation for EMMA2RH. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/pci/ops-vr41xx.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/types.h> + +#include <asm/addrspace.h> +#include <asm/debug.h> + +#include <asm/emma2rh/emma2rh.h> + +#define RTABORT (0x1<<9) +#define RMABORT (0x1<<10) +#define EMMA2RH_PCI_SLOT_NUM 9 /* 0000:09.0 is final PCI device */ + +/* + * access config space + */ + +static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num) +{ + /* check if the bus is top-level */ + if (bus->parent != NULL) { + *bus_num = bus->number; + db_assert(bus_num != 0); + } else + *bus_num = 0; + + if (*bus_num == 0) { + /* Type 0 */ + if (PCI_SLOT(devfn) >= 10) + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + /* Type 1 */ + if ((*bus_num >= 64) || (PCI_SLOT(devfn) >= 16)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + return 0; +} + +static inline int set_pci_configuration_address(unsigned char bus_num, + unsigned int devfn, int where) +{ + u32 config_win0; + + emma2rh_out32(EMMA2RH_PCI_INT, ~RMABORT); + if (bus_num == 0) + /* + * Type 0 configuration + */ + config_win0 = (1 << (22 + PCI_SLOT(devfn))) | (5 << 9); + else + /* + * Type 1 configuration + */ + config_win0 = (bus_num << 26) | (PCI_SLOT(devfn) << 22) | + (1 << 15) | (5 << 9); + + emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, config_win0); + + return 0; +} + +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t * val) +{ + u32 bus_num; + u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE); + u32 backup_win0; + u32 data; + + *val = 0xffffffffU; + + if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND) + return PCIBIOS_DEVICE_NOT_FOUND; + + backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR); + + if (set_pci_configuration_address(bus_num, devfn, where) < 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + data = + *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) + + (where & 0xfffffffc)); + + switch (size) { + case 1: + *val = (data >> ((where & 3) << 3)) & 0xffU; + break; + case 2: + *val = (data >> ((where & 2) << 3)) & 0xffffU; + break; + case 4: + *val = data; + break; + default: + emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0); + return PCIBIOS_FUNC_NOT_SUPPORTED; + } + + emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0); + + if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + u32 bus_num; + u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE); + u32 backup_win0; + u32 data; + int shift; + + if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND) + return PCIBIOS_DEVICE_NOT_FOUND; + + backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR); + + if (set_pci_configuration_address(bus_num, devfn, where) < 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* read modify write */ + data = + *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) + + (where & 0xfffffffc)); + + switch (size) { + case 1: + shift = (where & 3) << 3; + data &= ~(0xffU << shift); + data |= ((val & 0xffU) << shift); + break; + case 2: + shift = (where & 2) << 3; + data &= ~(0xffffU << shift); + data |= ((val & 0xffffU) << shift); + break; + case 4: + data = val; + break; + default: + emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0); + return PCIBIOS_FUNC_NOT_SUPPORTED; + } + *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) + + (where & 0xfffffffc)) = data; + + emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0); + if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT) + return PCIBIOS_DEVICE_NOT_FOUND; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops emma2rh_pci_ops = { + .read = pci_config_read, + .write = pci_config_write, +}; diff --git a/arch/mips/pci/ops-it8172.c b/arch/mips/pci/ops-it8172.c index b7a8b9a6f9db..ba8328505a0a 100644 --- a/arch/mips/pci/ops-it8172.c +++ b/arch/mips/pci/ops-it8172.c @@ -50,30 +50,28 @@ static struct resource pci_mem_resource_1; static struct resource pci_io_resource = { - "io pci IO space", - 0x14018000, - 0x17FFFFFF, - IORESOURCE_IO + .start = 0x14018000, + .end = 0x17FFFFFF, + .name = "io pci IO space", + .flags = IORESOURCE_IO }; static struct resource pci_mem_resource_0 = { - "ext pci memory space 0/1", - 0x10101000, - 0x13FFFFFF, - IORESOURCE_MEM, - &pci_mem_resource_0, - NULL, - &pci_mem_resource_1 + .start = 0x10101000, + .end = 0x13FFFFFF, + .name = "ext pci memory space 0/1", + .flags = IORESOURCE_MEM, + .parent = &pci_mem_resource_0, + .sibling = NULL, + .child = &pci_mem_resource_1 }; static struct resource pci_mem_resource_1 = { - "ext pci memory space 2/3", - 0x1A000000, - 0x1FBFFFFF, - IORESOURCE_MEM, - &pci_mem_resource_0, - NULL, - NULL + .start = 0x1A000000, + .end = 0x1FBFFFFF, + .name = "ext pci memory space 2/3", + .flags = IORESOURCE_MEM, + .parent = &pci_mem_resource_0 }; extern struct pci_ops it8172_pci_ops; diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c index 62bdd19c7f8e..2b0ccd6d9dcd 100644 --- a/arch/mips/pci/ops-sni.c +++ b/arch/mips/pci/ops-sni.c @@ -47,13 +47,13 @@ static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg, switch (size) { case 1: - *val = *(volatile u8 *) (PCIMT_CONFIG_DATA + (reg & 3)); + *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: - *val = *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)); + *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: - *val = *(volatile u32 *) PCIMT_CONFIG_DATA; + *val = inl(PCIMT_CONFIG_DATA); break; } @@ -70,13 +70,13 @@ static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg, switch (size) { case 1: - *(volatile u8 *) (PCIMT_CONFIG_DATA + (reg & 3)) = val; + outb (val, PCIMT_CONFIG_DATA + (reg & 3)); break; case 2: - *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)) = val; + outw (val, PCIMT_CONFIG_DATA + (reg & 2)); break; case 4: - *(volatile u32 *) PCIMT_CONFIG_DATA = val; + outl (val, PCIMT_CONFIG_DATA); break; } diff --git a/arch/mips/pci/ops-titan.c b/arch/mips/pci/ops-titan.c index 233ec6f2054d..ebf8fc40e9b2 100644 --- a/arch/mips/pci/ops-titan.c +++ b/arch/mips/pci/ops-titan.c @@ -26,8 +26,19 @@ #include <linux/pci.h> #include <linux/kernel.h> -#include <asm/titan_dep.h> +#include <asm/pci.h> +#include <asm/io.h> +#include <asm/rm9k-ocd.h> +/* + * PCI specific defines + */ +#define TITAN_PCI_0_CONFIG_ADDRESS 0x780 +#define TITAN_PCI_0_CONFIG_DATA 0x784 + +/* + * Titan PCI Config Read Byte + */ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 * val) { @@ -43,8 +54,8 @@ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg, /* start the configuration cycle */ - TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address); - tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3); + ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS); + tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3); switch (size) { case 1: @@ -71,20 +82,20 @@ static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg, (reg & 0xfc) | 0x80000000; /* start the configuration cycle */ - TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address); + ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS); /* write the data */ switch (size) { case 1: - TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val); + ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3)); break; case 2: - TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val); + ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2)); break; case 4: - TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val); + ocd_writel(val, TITAN_PCI_0_CONFIG_DATA); break; } diff --git a/arch/mips/pci/pci-ddb5074.c b/arch/mips/pci/pci-ddb5074.c deleted file mode 100644 index 73f9ceeb2f55..000000000000 --- a/arch/mips/pci/pci-ddb5074.c +++ /dev/null @@ -1,79 +0,0 @@ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/types.h> -#include <linux/pci.h> - -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -static struct resource extpci_io_resource = { - "pci IO space", - 0x1000, /* leave some room for ISA bus */ - DDB_PCI_IO_SIZE - 1, - IORESOURCE_IO -}; - -static struct resource extpci_mem_resource = { - "pci memory space", - DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ - DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, - IORESOURCE_MEM -}; - -extern struct pci_ops ddb5476_ext_pci_ops; - -struct pci_controller ddb5476_controller = { - .pci_ops = &ddb5476_ext_pci_ops, - .io_resource = &extpci_io_resource, - .mem_resource = &extpci_mem_resource, -}; - -#define PCI_EXT_INTA 8 -#define PCI_EXT_INTB 9 -#define PCI_EXT_INTC 10 -#define PCI_EXT_INTD 11 -#define PCI_EXT_INTE 12 - -#define MAX_SLOT_NUM 14 - -static unsigned char irq_map[MAX_SLOT_NUM] = { - [ 0] = nile4_to_irq(PCI_EXT_INTE), - [ 1] = nile4_to_irq(PCI_EXT_INTA), - [ 2] = nile4_to_irq(PCI_EXT_INTA), - [ 3] = nile4_to_irq(PCI_EXT_INTB), - [ 4] = nile4_to_irq(PCI_EXT_INTC), - [ 5] = nile4_to_irq(NILE4_INT_UART), - [10] = nile4_to_irq(PCI_EXT_INTE), - [13] = nile4_to_irq(PCI_EXT_INTE), -}; - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_map[slot]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -void __init ddb_pci_reset_bus(void) -{ - u32 temp; - - /* - * I am not sure about the "official" procedure, the following - * steps work as far as I know: - * We first set PCI cold reset bit (bit 31) in PCICTRL-H. - * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. - * The same is true for both PCI channels. - */ - temp = ddb_in32(DDB_PCICTRL + 4); - temp |= 0x80000000; - ddb_out32(DDB_PCICTRL + 4, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTRL + 4, temp); - -} diff --git a/arch/mips/pci/pci-ddb5476.c b/arch/mips/pci/pci-ddb5476.c deleted file mode 100644 index 90dd49509800..000000000000 --- a/arch/mips/pci/pci-ddb5476.c +++ /dev/null @@ -1,93 +0,0 @@ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/types.h> -#include <linux/pci.h> - -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -static struct resource extpci_io_resource = { - "pci IO space", - 0x1000, /* leave some room for ISA bus */ - DDB_PCI_IO_SIZE - 1, - IORESOURCE_IO -}; - -static struct resource extpci_mem_resource = { - "pci memory space", - DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ - DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, - IORESOURCE_MEM -}; - -extern struct pci_ops ddb5476_ext_pci_ops; - -struct pci_controller ddb5476_controller = { - .pci_ops = &ddb5476_ext_pci_ops, - .io_resource = &extpci_io_resource, - .mem_resource = &extpci_mem_resource -}; - - -/* - * we fix up irqs based on the slot number. - * The first entry is at AD:11. - * - * This does not work for devices on sub-buses yet. - */ - -/* - * temporary - */ - -#define PCI_EXT_INTA 8 -#define PCI_EXT_INTB 9 -#define PCI_EXT_INTC 10 -#define PCI_EXT_INTD 11 -#define PCI_EXT_INTE 12 - -/* - * based on ddb5477 manual page 11 - */ -#define MAX_SLOT_NUM 21 -static unsigned char irq_map[MAX_SLOT_NUM] = { - [ 2] = 9, /* AD:13 USB */ - [ 3] = 10, /* AD:14 PMU */ - [ 5] = 0, /* AD:16 P2P bridge */ - [ 6] = nile4_to_irq(PCI_EXT_INTB), /* AD:17 */ - [ 7] = nile4_to_irq(PCI_EXT_INTC), /* AD:18 */ - [ 8] = nile4_to_irq(PCI_EXT_INTD), /* AD:19 */ - [ 9] = nile4_to_irq(PCI_EXT_INTA), /* AD:20 */ - [13] = 14, /* AD:24 HD controller, M5229 */ -}; - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_map[slot]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -void __init ddb_pci_reset_bus(void) -{ - u32 temp; - - /* - * I am not sure about the "official" procedure, the following - * steps work as far as I know: - * We first set PCI cold reset bit (bit 31) in PCICTRL-H. - * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. - * The same is true for both PCI channels. - */ - temp = ddb_in32(DDB_PCICTRL + 4); - temp |= 0x80000000; - ddb_out32(DDB_PCICTRL + 4, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTRL + 4, temp); - -} diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c index 826d653184e5..d071bc375b11 100644 --- a/arch/mips/pci/pci-ddb5477.c +++ b/arch/mips/pci/pci-ddb5477.c @@ -22,31 +22,31 @@ #include <asm/ddb5xxx/ddb5xxx.h> static struct resource extpci_io_resource = { - "ext pci IO space", - DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, - DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, - IORESOURCE_IO + .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, + .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, + .name = "ext pci IO space", + .flags = IORESOURCE_IO }; static struct resource extpci_mem_resource = { - "ext pci memory space", - DDB_PCI0_MEM_BASE + 0x100000, - DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, - IORESOURCE_MEM + .start = DDB_PCI0_MEM_BASE + 0x100000, + .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, + .name = "ext pci memory space", + .flags = IORESOURCE_MEM }; static struct resource iopci_io_resource = { - "io pci IO space", - DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, - DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, - IORESOURCE_IO + .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, + .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, + .name = "io pci IO space", + .flags = IORESOURCE_IO }; static struct resource iopci_mem_resource = { - "ext pci memory space", - DDB_PCI1_MEM_BASE, - DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, - IORESOURCE_MEM + .start = DDB_PCI1_MEM_BASE, + .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, + .name = "ext pci memory space", + .flags = IORESOURCE_MEM }; extern struct pci_ops ddb5477_ext_pci_ops; diff --git a/arch/mips/pci/pci-emma2rh.c b/arch/mips/pci/pci-emma2rh.c new file mode 100644 index 000000000000..0f8b230057d3 --- /dev/null +++ b/arch/mips/pci/pci-emma2rh.c @@ -0,0 +1,90 @@ +/* + * arch/mips/pci/pci-emma2rh.c + * This file defines the PCI configration. + * + * Copyright (C) NEC Electronics Corporation 2004-2006 + * + * This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/pci.h> + +#include <asm/bootinfo.h> +#include <asm/debug.h> + +#include <asm/emma2rh/emma2rh.h> + +static struct resource pci_io_resource = { + .name = "pci IO space", + .start = EMMA2RH_PCI_IO_BASE, + .end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +static struct resource pci_mem_resource = { + .name = "pci memory space", + .start = EMMA2RH_PCI_MEM_BASE, + .end = EMMA2RH_PCI_MEM_BASE + EMMA2RH_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +extern struct pci_ops emma2rh_pci_ops; + +static struct pci_controller emma2rh_pci_controller = { + .pci_ops = &emma2rh_pci_ops, + .mem_resource = &pci_mem_resource, + .io_resource = &pci_io_resource, + .mem_offset = -0x04000000, + .io_offset = 0, +}; + +static void __init emma2rh_pci_init(void) +{ + /* setup PCI interface */ + emma2rh_out32(EMMA2RH_PCI_ARBIT_CTR, 0x70f); + + emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x80000a18); + emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_COMMAND, + PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_CAP_LIST | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000); + emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_1, 0x00000000); + + emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x12000000 | 0x218); + emma2rh_out32(EMMA2RH_PCI_IWIN1_CTR, 0x18000000 | 0x600); + emma2rh_out32(EMMA2RH_PCI_INIT_ESWP, 0x00000200); + + emma2rh_out32(EMMA2RH_PCI_TWIN_CTR, 0x00009200); + emma2rh_out32(EMMA2RH_PCI_TWIN_BADR, 0x00000000); + emma2rh_out32(EMMA2RH_PCI_TWIN0_DADR, 0x00000000); + emma2rh_out32(EMMA2RH_PCI_TWIN1_DADR, 0x00000000); +} + +static int __init emma2rh_pci_setup(void) +{ + emma2rh_pci_init(); + register_pci_controller(&emma2rh_pci_controller); + return 0; +} + +arch_initcall(emma2rh_pci_setup); diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c new file mode 100644 index 000000000000..3c86c77cb74f --- /dev/null +++ b/arch/mips/pci/pci-excite.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * Based on the PMC-Sierra Yosemite board support by Ralf Baechle. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/bitops.h> +#include <asm/rm9k-ocd.h> +#include <excite.h> + + +extern struct pci_ops titan_pci_ops; + + +static struct resource + mem_resource = { + .name = "PCI memory", + .start = EXCITE_PHYS_PCI_MEM, + .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1, + .flags = IORESOURCE_MEM + }, + io_resource = { + .name = "PCI I/O", + .start = EXCITE_PHYS_PCI_IO, + .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1, + .flags = IORESOURCE_IO + }; + + +static struct pci_controller bx_controller = { + .pci_ops = &titan_pci_ops, + .mem_resource = &mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &io_resource, + .io_offset = 0x00000000UL +}; + + +static char + iopage_failed[] __initdata = "Cannot allocate PCI I/O page", + modebits_no_pci[] __initdata = "PCI is not configured in mode bits"; + +#define RM9000x2_OCD_HTSC 0x0604 +#define RM9000x2_OCD_HTBHL 0x060c +#define RM9000x2_OCD_PCIHRST 0x078c + +#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */ +#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */ + +#define PCISC_FB2B 0x00000200 +#define PCISC_MWICG 0x00000010 +#define PCISC_EMC 0x00000004 +#define PCISC_ERMA 0x00000002 + + + +static int __init basler_excite_pci_setup(void) +{ + const unsigned int fullbars = memsize / (256 << 20); + unsigned int i; + + /* Check modebits to see if PCI is really enabled. */ + if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1)) + panic(modebits_no_pci); + + if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO, + "Memory-mapped PCI I/O page")) + panic(iopage_failed); + + /* Enable PCI 0 as master for config cycles */ + ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC); + + + /* Set up latency timer */ + ocd_writel(0x8008, RM9000x2_OCD_HTBHL); + + /* Setup host IO and Memory space */ + ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7); + ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7); + ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8); + ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8); + + /* Set up PCI BARs to map all installed memory */ + for (i = 0; i < 6; i++) { + const unsigned int bar = 0x610 + i * 4; + + if (i < fullbars) { + ocd_writel(0x10000000 * i, bar); + ocd_writel(0x01000000 * i, bar + 0x140); + ocd_writel(0x0ffff029, bar + 0x100); + continue; + } + + if (i == fullbars) { + int o; + u32 mask; + + const unsigned long rem = memsize - i * 0x10000000; + if (!rem) { + ocd_writel(0x00000000, bar + 0x100); + continue; + } + + o = ffs(rem) - 1; + if (rem & ~(0x1 << o)) + o++; + mask = ((0x1 << o) & 0x0ffff000) - 0x1000; + ocd_writel(0x10000000 * i, bar); + ocd_writel(0x01000000 * i, bar + 0x140); + ocd_writel(0x00000029 | mask, bar + 0x100); + continue; + } + + ocd_writel(0x00000000, bar + 0x100); + } + + /* Finally, enable the PCI interupt */ +#if USB_IRQ > 7 + set_c0_intcontrol(1 << USB_IRQ); +#else + set_c0_status(1 << (USB_IRQ + 8)); +#endif + + ioport_resource.start = EXCITE_PHYS_PCI_IO; + ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1; + set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO)); + register_pci_controller(&bx_controller); + return 0; +} + + +arch_initcall(basler_excite_pci_setup); diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 6002d2a6a262..80eb9af9ecdf 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -40,297 +40,7 @@ static struct bridge_controller bridges[MAX_PCI_BUSSES]; struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; -/* - * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is - * not really documented, so right now I can't write code which uses it. - * Therefore we use type 0 accesses for now even though they won't work - * correcly for PCI-to-PCI bridges. - * - * The function is complicated by the ultimate brokeness of the IOC3 chip - * which is used in SGI systems. The IOC3 can only handle 32-bit PCI - * accesses and does only decode parts of it's address space. - */ - -static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * value) -{ - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); - bridge_t *bridge = bc->base; - int slot = PCI_SLOT(devfn); - int fn = PCI_FUNC(devfn); - volatile void *addr; - u32 cf, shift, mask; - int res; - - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to look at it for real ... - */ - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) - goto oh_my_gawd; - - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; - - if (size == 1) - res = get_dbe(*value, (u8 *) addr); - else if (size == 2) - res = get_dbe(*value, (u16 *) addr); - else - res = get_dbe(*value, (u32 *) addr); - - return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; - -oh_my_gawd: - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to look at the wrong register. - */ - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { - *value = 0; - return PCIBIOS_SUCCESSFUL; - } - - /* - * IOC3 is fucked fucked beyond believe ... Don't try to access - * anything but 32-bit words ... - */ - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; - - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - shift = ((where & 3) << 3); - mask = (0xffffffffU >> ((4 - size) << 3)); - *value = (cf >> shift) & mask; - - return PCIBIOS_SUCCESSFUL; -} - -static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * value) -{ - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); - bridge_t *bridge = bc->base; - int busno = bus->number; - int slot = PCI_SLOT(devfn); - int fn = PCI_FUNC(devfn); - volatile void *addr; - u32 cf, shift, mask; - int res; - - bridge->b_pci_cfg = (busno << 16) | (slot << 11); - addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to look at it for real ... - */ - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) - goto oh_my_gawd; - - bridge->b_pci_cfg = (busno << 16) | (slot << 11); - addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; - - if (size == 1) - res = get_dbe(*value, (u8 *) addr); - else if (size == 2) - res = get_dbe(*value, (u16 *) addr); - else - res = get_dbe(*value, (u32 *) addr); - - return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; - -oh_my_gawd: - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to look at the wrong register. - */ - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { - *value = 0; - return PCIBIOS_SUCCESSFUL; - } - - /* - * IOC3 is fucked fucked beyond believe ... Don't try to access - * anything but 32-bit words ... - */ - bridge->b_pci_cfg = (busno << 16) | (slot << 11); - addr = &bridge->b_type1_cfg.c[(fn << 8) | where]; - - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - shift = ((where & 3) << 3); - mask = (0xffffffffU >> ((4 - size) << 3)); - *value = (cf >> shift) & mask; - - return PCIBIOS_SUCCESSFUL; -} - -static int pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * value) -{ - if (bus->number > 0) - return pci_conf1_read_config(bus, devfn, where, size, value); - - return pci_conf0_read_config(bus, devfn, where, size, value); -} - -static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) -{ - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); - bridge_t *bridge = bc->base; - int slot = PCI_SLOT(devfn); - int fn = PCI_FUNC(devfn); - volatile void *addr; - u32 cf, shift, mask, smask; - int res; - - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to look at it for real ... - */ - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) - goto oh_my_gawd; - - addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; - - if (size == 1) { - res = put_dbe(value, (u8 *) addr); - } else if (size == 2) { - res = put_dbe(value, (u16 *) addr); - } else { - res = put_dbe(value, (u32 *) addr); - } - - if (res) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; - -oh_my_gawd: - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to touch the wrong register. - */ - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) - return PCIBIOS_SUCCESSFUL; - - /* - * IOC3 is fucked fucked beyond believe ... Don't try to access - * anything but 32-bit words ... - */ - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; - - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - shift = ((where & 3) << 3); - mask = (0xffffffffU >> ((4 - size) << 3)); - smask = mask << shift; - - cf = (cf & ~smask) | ((value & mask) << shift); - if (put_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; -} - -static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) -{ - struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); - bridge_t *bridge = bc->base; - int slot = PCI_SLOT(devfn); - int fn = PCI_FUNC(devfn); - int busno = bus->number; - volatile void *addr; - u32 cf, shift, mask, smask; - int res; - - bridge->b_pci_cfg = (busno << 16) | (slot << 11); - addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to look at it for real ... - */ - if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) - goto oh_my_gawd; - - addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; - - if (size == 1) { - res = put_dbe(value, (u8 *) addr); - } else if (size == 2) { - res = put_dbe(value, (u16 *) addr); - } else { - res = put_dbe(value, (u32 *) addr); - } - - if (res) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; - -oh_my_gawd: - - /* - * IOC3 is fucked fucked beyond believe ... Don't even give the - * generic PCI code a chance to touch the wrong register. - */ - if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) - return PCIBIOS_SUCCESSFUL; - - /* - * IOC3 is fucked fucked beyond believe ... Don't try to access - * anything but 32-bit words ... - */ - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; - - if (get_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - shift = ((where & 3) << 3); - mask = (0xffffffffU >> ((4 - size) << 3)); - smask = mask << shift; - - cf = (cf & ~smask) | ((value & mask) << shift); - if (put_dbe(cf, (u32 *) addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; -} - -static int pci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) -{ - if (bus->number > 0) - return pci_conf1_write_config(bus, devfn, where, size, value); - - return pci_conf0_write_config(bus, devfn, where, size, value); -} - -static struct pci_ops bridge_pci_ops = { - .read = pci_read_config, - .write = pci_write_config, -}; +extern struct pci_ops bridge_pci_ops; int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid) { @@ -370,8 +80,7 @@ int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid) bc->widget_id = widget_id; bc->nasid = nasid; - bc->baddr = (u64)masterwid << 60; - bc->baddr |= (1UL << 56); /* Barrier set */ + bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR; /* * point to this bridge diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c index f02ef6e36b02..cb84f4e8ccae 100644 --- a/arch/mips/pci/pci-jmr3927.c +++ b/arch/mips/pci/pci-jmr3927.c @@ -35,17 +35,17 @@ #include <asm/debug.h> struct resource pci_io_resource = { - "IO MEM", - 0x1000, /* reserve regacy I/O space */ - 0x1000 + JMR3927_PCIIO_SIZE - 1, - IORESOURCE_IO + .name = "IO MEM", + .start = 0x1000, /* reserve regacy I/O space */ + .end = 0x1000 + JMR3927_PCIIO_SIZE - 1, + .flags = IORESOURCE_IO }; struct resource pci_mem_resource = { - "PCI MEM", - JMR3927_PCIMEM, - JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, - IORESOURCE_MEM + .name = "PCI MEM", + .start = JMR3927_PCIMEM, + .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, + .flags = IORESOURCE_MEM }; extern struct pci_ops jmr3927_pci_ops; diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c index 3da8a4ee6baa..2b9495dce6ba 100644 --- a/arch/mips/pci/pci-ocelot.c +++ b/arch/mips/pci/pci-ocelot.c @@ -71,13 +71,13 @@ static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data) } static struct resource ocelot_mem_resource = { - iomem_resource.start = GT_PCI_MEM_BASE; - iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; + start = GT_PCI_MEM_BASE; + end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; }; static struct resource ocelot_io_resource = { - ioport_resource.start = GT_PCI_IO_BASE; - ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; + start = GT_PCI_IO_BASE; + end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; }; static struct pci_controller ocelot_pci_controller = { diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c index dac9ed4b0ccf..0357946f30e6 100644 --- a/arch/mips/pci/pci-yosemite.c +++ b/arch/mips/pci/pci-yosemite.c @@ -14,7 +14,10 @@ extern struct pci_ops titan_pci_ops; static struct resource py_mem_resource = { - "Titan PCI MEM", 0xe0000000UL, 0xe3ffffffUL, IORESOURCE_MEM + .start = 0xe0000000UL, + .end = 0xe3ffffffUL, + .name = "Titan PCI MEM", + .flags = IORESOURCE_MEM }; /* @@ -26,7 +29,10 @@ static struct resource py_mem_resource = { #define TITAN_IO_BASE 0xe8000000UL static struct resource py_io_resource = { - "Titan IO MEM", 0x00001000UL, TITAN_IO_SIZE - 1, IORESOURCE_IO, + .start = 0x00001000UL, + .end = TITAN_IO_SIZE - 1, + .name = "Titan IO MEM", + .flags = IORESOURCE_IO, }; static struct pci_controller py_controller = { diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 21402ffd7c98..4dfce154d4af 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -76,11 +76,6 @@ pcibios_align_resource(void *data, struct resource *res, res->start = start; } -struct pci_controller * __init alloc_pci_controller(void) -{ - return alloc_bootmem(sizeof(struct pci_controller)); -} - void __init register_pci_controller(struct pci_controller *hose) { *hose_tail = hose; diff --git a/arch/mips/philips/pnx8550/common/pci.c b/arch/mips/philips/pnx8550/common/pci.c index baa6905f649f..eee4f3dfc410 100644 --- a/arch/mips/philips/pnx8550/common/pci.c +++ b/arch/mips/philips/pnx8550/common/pci.c @@ -27,17 +27,17 @@ #include <nand.h> static struct resource pci_io_resource = { - "pci IO space", - (u32)(PNX8550_PCIIO + 0x1000), /* reserve regacy I/O space */ - (u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE), - IORESOURCE_IO + .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */ + .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE, + .name = "pci IO space", + .flags = IORESOURCE_IO }; static struct resource pci_mem_resource = { - "pci memory space", - (u32)(PNX8550_PCIMEM), - (u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1), - IORESOURCE_MEM + .start = PNX8550_PCIMEM, + .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1, + .name = "pci memory space", + .flags = IORESOURCE_MEM }; extern struct pci_ops pnx8550_pci_ops; diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c index 0d8a77619391..0e791f4f6ea3 100644 --- a/arch/mips/philips/pnx8550/common/setup.c +++ b/arch/mips/philips/pnx8550/common/setup.c @@ -58,10 +58,27 @@ extern void prom_printf(char *fmt, ...); extern char *prom_getcmdline(void); struct resource standard_io_resources[] = { - {"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, - {"timer", 0x40, 0x5f, IORESOURCE_BUSY}, - {"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, - {"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}, + { + .start = .0x00, + .end = 0x1f, + .name = "dma1", + .flags = IORESOURCE_BUSY + }, { + .start = 0x40, + .end = 0x5f, + .name = "timer", + .flags = IORESOURCE_BUSY + }, { + .start = 0x80, + .end = 0x8f, + .name = "dma page reg", + .flags = IORESOURCE_BUSY + }, { + .start = 0xc0, + .end = 0xdf, + .name = "dma2", + .flags = IORESOURCE_BUSY + }, }; #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) @@ -82,7 +99,7 @@ unsigned long get_system_mem_size(void) int pnx8550_console_port = -1; -void __init plat_setup(void) +void __init plat_mem_setup(void) { int i; char* argptr; diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 3f724d661bdb..aa0d6ff3c6ec 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -218,7 +218,7 @@ static void __init py_late_time_init(void) py_rtc_setup(); } -void __init plat_setup(void) +void __init plat_mem_setup(void) { board_time_init = yosemite_time_init; late_time_init = py_late_time_init; diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile index 730f459f3e99..078cd3029c9f 100644 --- a/arch/mips/qemu/Makefile +++ b/arch/mips/qemu/Makefile @@ -2,6 +2,6 @@ # Makefile for Qemu specific kernel interface routines under Linux. # -obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o +obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o obj-$(CONFIG_SMP) += q-smp.o diff --git a/arch/mips/qemu/q-reset.c b/arch/mips/qemu/q-reset.c new file mode 100644 index 000000000000..c04ebcfc7843 --- /dev/null +++ b/arch/mips/qemu/q-reset.c @@ -0,0 +1,34 @@ +#include <linux/config.h> + +#include <asm/io.h> +#include <asm/reboot.h> +#include <asm/cacheflush.h> +#include <asm/qemu.h> + +static void qemu_machine_restart(char *command) +{ + volatile unsigned int *reg = (unsigned int *)QEMU_RESTART_REG; + + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + *reg = 42; + while (1) + cpu_wait(); +} + +static void qemu_machine_halt(void) +{ + volatile unsigned int *reg = (unsigned int *)QEMU_HALT_REG; + + *reg = 42; + while (1) + cpu_wait(); +} + +void qemu_reboot_setup(void) +{ + _machine_restart = qemu_machine_restart; + _machine_halt = qemu_machine_halt; +} diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c index 022eb1af6db1..e100d6072e31 100644 --- a/arch/mips/qemu/q-setup.c +++ b/arch/mips/qemu/q-setup.c @@ -2,6 +2,8 @@ #include <asm/io.h> #include <asm/time.h> +extern void qemu_reboot_setup(void); + #define QEMU_PORT_BASE 0xb4000000 const char *get_system_type(void) @@ -18,8 +20,10 @@ static void __init qemu_timer_setup(struct irqaction *irq) setup_irq(0, irq); } -void __init plat_setup(void) +void __init plat_mem_setup(void) { set_io_port_base(QEMU_PORT_BASE); board_timer_setup = qemu_timer_setup; + + qemu_reboot_setup(); } diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 7018e1833e85..d7138906eb10 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -53,7 +53,7 @@ EXPORT_SYMBOL(ip22_do_break); extern void ip22_be_init(void) __init; extern void ip22_time_init(void) __init; -void __init plat_setup(void) +void __init plat_mem_setup(void) { char *ctype; char *cserial; diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig index 7b0bc4437243..f14ef38646d0 100644 --- a/arch/mips/sgi-ip27/Kconfig +++ b/arch/mips/sgi-ip27/Kconfig @@ -4,31 +4,29 @@ # This options adds support for userspace processes upto 16TB size. # Normally the limit is just .5TB. -config SGI_SN0_N_MODE - bool "IP27 N-Mode" +choice + prompt "Node addressing mode" depends on SGI_IP27 - help - The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be - configured in either N-Modes which allows for more nodes or M-Mode - which allows for more memory. Your system is most probably - running in M-Mode, so you should say N here. + default SGI_SN_M_MODE -config ARCH_DISCONTIGMEM_ENABLE - bool - default y if SGI_IP27 +config SGI_SN_M_MODE + bool "IP27 M-Mode" help - Say Y to upport efficient handling of discontiguous physical memory, - for architectures which are either NUMA (Non-Uniform Memory Access) - or have huge holes in the physical address space for other reasons. - See <file:Documentation/vm/numa> for more. + The nodes of Origin, Onyx, Fuel and Tezro systems can be configured + in either N-Modes which allows for more nodes or M-Mode which allows + for more memory. Your hardware is almost certainly running in + M-Mode, so choose M-mode here. -config NUMA - bool "NUMA Support" - depends on SGI_IP27 +config SGI_SN_N_MODE + bool "IP27 N-Mode" + depends on EXPERIMENTAL help - Say Y to compile the kernel to support NUMA (Non-Uniform Memory - Access). This option is for configuring high-end multiprocessor - server machines. If in doubt, say N. + The nodes of Origin, Onyx, Fuel and Tezro systems can be configured + in either N-Modes which allows for more nodes or M-Mode which allows + for more memory. Your hardware is almost certainly running in + M-Mode, so choose M-mode here. + +endchoice config MAPPED_KERNEL bool "Mapped kernel support" diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index 8651a0e75404..a6b490e99709 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -196,7 +196,7 @@ extern void ip27_setup_console(void); extern void ip27_time_init(void); extern void ip27_reboot_setup(void); -void __init plat_setup(void) +void __init plat_mem_setup(void) { hubreg_t p, e, n_mode; nasid_t nid; @@ -228,7 +228,7 @@ void __init plat_setup(void) */ n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK; printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M'); -#ifdef CONFIG_SGI_SN0_N_MODE +#ifdef CONFIG_SGI_SN_N_MODE if (!n_mode) panic("Kernel compiled for M mode."); #else diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 2e643d2f51cb..0b61a39ce2bb 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -360,7 +360,7 @@ static struct hw_interrupt_type bridge_irq_type = { static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; -static int allocate_irqno(void) +int allocate_irqno(void) { int irq; diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 36b662e27b6e..1fb860c7ac6d 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -89,11 +89,13 @@ static int set_rtc_mmss(unsigned long nowtime) } #endif +static unsigned int rt_timer_irq; + void ip27_rt_timer_interrupt(struct pt_regs *regs) { int cpu = smp_processor_id(); int cpuA = cputoslice(cpu) == 0; - int irq = 9; /* XXX Assign number */ + unsigned int irq = rt_timer_irq; irq_enter(); write_seqlock(&xtime_lock); @@ -179,13 +181,68 @@ static __init unsigned long get_m48t35_time(void) return mktime(year, month, date, hour, min, sec); } +static void startup_rt_irq(unsigned int irq) +{ +} + +static void shutdown_rt_irq(unsigned int irq) +{ +} + +static void enable_rt_irq(unsigned int irq) +{ +} + +static void disable_rt_irq(unsigned int irq) +{ +} + +static void mask_and_ack_rt(unsigned int irq) +{ +} + +static void end_rt_irq(unsigned int irq) +{ +} + +static struct hw_interrupt_type rt_irq_type = { + .typename = "SN HUB RT timer", + .startup = startup_rt_irq, + .shutdown = shutdown_rt_irq, + .enable = enable_rt_irq, + .disable = disable_rt_irq, + .ack = mask_and_ack_rt, + .end = end_rt_irq, +}; + +static struct irqaction rt_irqaction = { + .handler = ip27_rt_timer_interrupt, + .flags = SA_INTERRUPT, + .mask = CPU_MASK_NONE, + .name = "timer" +}; + +extern int allocate_irqno(void); + static void ip27_timer_setup(struct irqaction *irq) { + int irqno = allocate_irqno(); + + if (irqno < 0) + panic("Can't allocate interrupt number for timer interrupt"); + + irq_desc[irqno].status = IRQ_DISABLED; + irq_desc[irqno].action = NULL; + irq_desc[irqno].depth = 1; + irq_desc[irqno].handler = &rt_irq_type; + /* over-write the handler, we use our own way */ irq->handler = no_action; /* setup irqaction */ -// setup_irq(IP27_TIMER_IRQ, irq); /* XXX Can't do this yet. */ + irq_desc[irqno].status |= IRQ_PER_CPU; + + rt_timer_irq = irqno; } void __init ip27_time_init(void) diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c index a2dd8ae1ea8f..acbdad06fac1 100644 --- a/arch/mips/sgi-ip32/ip32-setup.c +++ b/arch/mips/sgi-ip32/ip32-setup.c @@ -87,7 +87,7 @@ void __init ip32_timer_setup(struct irqaction *irq) setup_irq(IP32_R4K_TIMER_IRQ, irq); } -void __init plat_setup(void) +void __init plat_mem_setup(void) { board_be_init = ip32_be_init; diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c index e545752695a1..efaf83efd2e4 100644 --- a/arch/mips/sibyte/bcm1480/time.c +++ b/arch/mips/sibyte/bcm1480/time.c @@ -110,17 +110,18 @@ void bcm1480_timer_interrupt(struct pt_regs *regs) __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); - /* - * CPU 0 handles the global timer interrupt job - */ if (cpu == 0) { + /* + * CPU 0 handles the global timer interrupt job + */ ll_timer_interrupt(irq, regs); } - - /* - * every CPU should do profiling and process accouting - */ - ll_local_timer_interrupt(irq, regs); + else { + /* + * other CPUs should just do profiling and process accounting + */ + ll_local_timer_interrupt(irq, regs); + } } /* diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 0f6e54db4888..f853c32f60a0 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -435,13 +435,17 @@ static inline int dclz(unsigned long long x) return lz; } +extern void sb1250_timer_interrupt(struct pt_regs *regs); +extern void sb1250_mailbox_interrupt(struct pt_regs *regs); +extern void sb1250_kgdb_interrupt(struct pt_regs *regs); + asmlinkage void plat_irq_dispatch(struct pt_regs *regs) { unsigned int pending; #ifdef CONFIG_SIBYTE_SB1250_PROF /* Set compare to count to silence count/compare timer interrupts */ - write_c0_count(read_c0_count()); + write_c0_compare(read_c0_count()); #endif /* @@ -482,7 +486,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs) * Default...we've hit an IP[2] interrupt, which means we've * got to check the 1250 interrupt registers to figure out what * to do. Need to detect which CPU we're on, now that - ~ smp_affinity is supported. + * smp_affinity is supported. */ mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), R_IMR_INTERRUPT_STATUS_BASE))); diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 4b5f74ff3edd..f9e694988cdf 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -72,8 +72,10 @@ const char *get_system_type(void) void __init swarm_time_init(void) { +#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) /* Setup HPT */ sb1250_hpt_setup(); +#endif } void __init swarm_timer_setup(struct irqaction *irq) @@ -103,7 +105,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); } -void __init plat_setup(void) +void __init plat_mem_setup(void) { #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) bcm1480_setup(); diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile index 9c7eaa5fb210..a5eb0adb87c7 100644 --- a/arch/mips/sni/Makefile +++ b/arch/mips/sni/Makefile @@ -3,5 +3,6 @@ # obj-y += irq.o pcimt_scache.o reset.o setup.o +obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 01ba6c581e3d..a050bb6ae704 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -21,8 +21,11 @@ #include <linux/fb.h> #include <linux/tty.h> +#ifdef CONFIG_ARC #include <asm/arc/types.h> #include <asm/sgialib.h> +#endif + #include <asm/bcache.h> #include <asm/bootinfo.h> #include <asm/io.h> @@ -72,8 +75,7 @@ static inline void sni_pcimt_detect(void) static void __init sni_display_setup(void) { -#ifdef CONFIG_VT -#if defined(CONFIG_VGA_CONSOLE) +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC) struct screen_info *si = &screen_info; DISPLAY_STATUS *di; @@ -88,24 +90,54 @@ static void __init sni_display_setup(void) si->orig_video_points = 16; } #endif -#endif } static struct resource sni_io_resource = { - "PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO, + .start = 0x00001000UL, + .end = 0x03bfffffUL, + .name = "PCIMT IO MEM", + .flags = IORESOURCE_IO, }; static struct resource pcimt_io_resources[] = { - { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, - { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, - { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, - { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, - { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, - { "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY } + { + .start = 0x00, + .end = 0x1f, + .name = "dma1", + .flags = IORESOURCE_BUSY + }, { + .start = 0x40, + .end = 0x5f, + .name = "timer", + .flags = IORESOURCE_BUSY + }, { + .start = 0x60, + .end = 0x6f, + .name = "keyboard", + .flags = IORESOURCE_BUSY + }, { + .start = 0x80, + .end = 0x8f, + .name = "dma page reg", + .flags = IORESOURCE_BUSY + }, { + .start = 0xc0, + .end = 0xdf, + .name = "dma2", + .flags = IORESOURCE_BUSY + }, { + .start = 0xcfc, + .end = 0xcff, + .name = "PCI config data", + .flags = IORESOURCE_BUSY + } }; static struct resource sni_mem_resource = { - "PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM + .start = 0x10000000UL, + .end = 0xffffffffUL, + .name = "PCIMT PCI MEM", + .flags = IORESOURCE_MEM }; /* @@ -122,19 +154,72 @@ static struct resource sni_mem_resource = { * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory */ static struct resource pcimt_mem_resources[] = { - { "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY }, - { "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY }, - { "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY }, - { "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY}, - { "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY }, - { "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY}, - { "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY}, - { "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY}, - { "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY}, - { "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY}, - { "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY}, - { "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY}, - { "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY} + { + .start = 0x100a0000, + .end = 0x100bffff, + .name = "Video RAM area", + .flags = IORESOURCE_BUSY + }, { + .start = 0x100c0000, + .end = 0x100fffff, + .name = "ISA Reserved", + .flags = IORESOURCE_BUSY + }, { + .start = 0x14000000, + .end = 0x17bfffff, + .name = "PCI IO", + .flags = IORESOURCE_BUSY + }, { + .start = 0x17c00000, + .end = 0x17ffffff, + .name = "Cache Replacement Area", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1a000000, + .end = 0x1a000003, + .name = "PCI INT Acknowledge", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1fc00000, + .end = 0x1fc7ffff, + .name = "Boot PROM", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1fc80000, + .end = 0x1fcfffff, + .name = "Diag PROM", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1fd00000, + .end = 0x1fdfffff, + .name = "X-Bus", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1fe00000, + .end = 0x1fefffff, + .name = "BIOS map", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1ff00000, + .end = 0x1ff7ffff, + .name = "NVRAM / EEPROM", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1fff0000, + .end = 0x1fffefff, + .name = "ASIC PCI", + .flags = IORESOURCE_BUSY + }, { + .start = 0x1ffff000, + .end = 0x1fffffff, + .name = "MP Agent", + .flags = IORESOURCE_BUSY + }, { + .start = 0x20000000, + .end = 0x9fffffff, + .name = "Main Memory", + .flags = IORESOURCE_BUSY + } }; static void __init sni_resource_init(void) @@ -168,7 +253,7 @@ static inline void sni_pcimt_time_init(void) rtc_mips_set_time = mc146818_set_rtc_mmss; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { sni_pcimt_detect(); sni_pcimt_sc_init(); diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c new file mode 100644 index 000000000000..d1d0f1f493b4 --- /dev/null +++ b/arch/mips/sni/sniprom.c @@ -0,0 +1,158 @@ +/* + * Big Endian PROM code for SNI RM machines + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org) + * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/string.h> + +#include <asm/addrspace.h> +#include <asm/sni.h> +#include <asm/mipsprom.h> +#include <asm/bootinfo.h> + +/* special SNI prom calls */ +/* + * This does not exist in all proms - SINIX compares + * the prom env variable "version" against "2.0008" + * or greater. If lesser it tries to probe interesting + * registers + */ +#define PROM_GET_MEMCONF 58 + +#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000) +#define PROM_ENTRY(x) (PROM_VEC + (x)) + + +#undef DEBUG +#ifdef DEBUG +#define DBG_PRINTF(x...) prom_printf(x) +#else +#define DBG_PRINTF(x...) +#endif + +static int *(*__prom_putchar)(int) = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR); +static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV); +static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF); + +char *prom_getenv (char *s) +{ + return __prom_getenv(s); +} + +void prom_printf(char *fmt, ...) +{ + va_list args; + char ppbuf[1024]; + char *bptr; + + va_start(args, fmt); + vsprintf(ppbuf, fmt, args); + + bptr = ppbuf; + + while (*bptr != 0) { + if (*bptr == '\n') + __prom_putchar('\r'); + + __prom_putchar(*bptr++); + } + va_end(args); +} + +unsigned long prom_free_prom_memory(void) +{ + return 0; +} + +/* + * /proc/cpuinfo system type + * + */ +static const char *systype = "Unknown"; +const char *get_system_type(void) +{ + return systype; +} + +#define SNI_IDPROM_BASE 0xbff00000 +#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE+0x28) /* Memsize in 16MB quantities */ +#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE+0x29) /* Board Type */ +#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE+0x30) /* CPU Type */ + +#define SNI_IDPROM_SIZE 0x1000 + +#ifdef DEBUG +static void sni_idprom_dump(void) +{ + int i; + + prom_printf("SNI IDProm dump (first 128byte):\n"); + for(i=0;i<128;i++) { + if (i%16 == 0) + prom_printf("%04x ", i); + + prom_printf("%02x ", *(unsigned char *) (SNI_IDPROM_BASE+i)); + + if (i%16 == 15) + prom_printf("\n"); + } +} +#endif + +static void sni_mem_init(void ) +{ + int i, memsize; + struct membank { + u32 size; + u32 base; + u32 size2; + u32 pad1; + u32 pad2; + } memconf[8]; + + /* MemSIZE from prom in 16MByte chunks */ + memsize=*((unsigned char *) SNI_IDPROM_MEMSIZE) * 16; + + DBG_PRINTF("IDProm memsize: %lu MByte\n", memsize); + + /* get memory bank layout from prom */ + __prom_get_memconf(&memconf); + + DBG_PRINTF("prom_get_mem_conf memory configuration:\n"); + for(i=0;i<8 && memconf[i].size;i++) { + prom_printf("Bank%d: %08x @ %08x\n", i, + memconf[i].size, memconf[i].base); + add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM); + } +} + +void __init prom_init(void) +{ + int argc = fw_arg0; + char **argv = (void *)fw_arg1; + unsigned int sni_brd_type = *(unsigned char *) SNI_IDPROM_BRDTYPE; + int i; + + DBG_PRINTF("Found SNI brdtype %02x\n", sni_brd_type); + +#ifdef DEBUG + sni_idprom_dump(); +#endif + sni_mem_init(); + + /* copy prom cmdline parameters to kernel cmdline */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } +} + diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index 77c3b66fb959..81a5acfe8c42 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -64,7 +64,7 @@ static void tx4927_write_buffer_flush(void) } -void __init plat_setup(void) +void __init plat_mem_setup(void) { board_time_init = tx4927_time_init; board_timer_setup = tx4927_timer_setup; diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c index fc992953bf95..ef59a5cffc69 100644 --- a/arch/mips/tx4938/common/setup.c +++ b/arch/mips/tx4938/common/setup.c @@ -61,7 +61,7 @@ tx4938_write_buffer_flush(void) } void __init -plat_setup(void) +plat_mem_setup(void) { board_time_init = tx4938_time_init; board_timer_setup = tx4938_timer_setup; diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index 9166cd4557eb..96e833cd4c14 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -664,7 +664,10 @@ static struct resource rbtx4938_fpga_resource; static char pcode_str[8]; static struct resource tx4938_reg_resource = { - pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM + .start = TX4938_REG_BASE, + .end = TX4938_REG_BASE + TX4938_REG_SIZE, + .name = pcode_str, + .flags = IORESOURCE_MEM }; void __init tx4938_board_setup(void) diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig index 055a2cdfc841..6046ef23b2bf 100644 --- a/arch/mips/vr41xx/Kconfig +++ b/arch/mips/vr41xx/Kconfig @@ -4,7 +4,6 @@ config CASIO_E55 select DMA_NONCOHERENT select IRQ_CPU select ISA - select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN @@ -14,18 +13,15 @@ config IBM_WORKPAD select DMA_NONCOHERENT select IRQ_CPU select ISA - select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN config NEC_CMBVR4133 bool "Support for NEC CMB-VR4133" depends on MACH_VR41XX - select CPU_VR41XX select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI - select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN @@ -41,7 +37,6 @@ config TANBAC_TB022X select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU - select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN help @@ -74,7 +69,6 @@ config VICTOR_MPC30X select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU - select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN @@ -84,7 +78,6 @@ config ZAO_CAPCELLA select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU - select SYS_HAS_CPU_VR41XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index 707bd0933eed..915bfa5c0719 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -58,7 +58,7 @@ static void __init timer_init(void) board_timer_setup = setup_timer_irq; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { vr41xx_calculate_clock_frequency(); diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c index 41e9ab40cd54..f70bd090dacd 100644 --- a/arch/powerpc/kernel/prom_init.c +++ b/arch/powerpc/kernel/prom_init.c @@ -822,6 +822,7 @@ static void __init prom_send_capabilities(void) /* try calling the ibm,client-architecture-support method */ if (call_prom_ret("call-method", 3, 2, &ret, ADDR("ibm,client-architecture-support"), + root, ADDR(ibm_architecture_vec)) == 0) { /* the call exists... */ if (ret) @@ -1622,6 +1623,15 @@ static int __init prom_find_machine_type(void) if (strstr(p, RELOC("Power Macintosh")) || strstr(p, RELOC("MacRISC"))) return PLATFORM_POWERMAC; +#ifdef CONFIG_PPC64 + /* We must make sure we don't detect the IBM Cell + * blades as pSeries due to some firmware issues, + * so we do it here. + */ + if (strstr(p, RELOC("IBM,CBEA")) || + strstr(p, RELOC("IBM,CPBW-1.0"))) + return PLATFORM_GENERIC; +#endif /* CONFIG_PPC64 */ i += sl + 1; } } diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index 01e3c08cb550..8fdeca2d4597 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -803,10 +803,13 @@ static int do_setcontext(struct ucontext __user *ucp, struct pt_regs *regs, int if (__get_user(cmcp, &ucp->uc_regs)) return -EFAULT; mcp = (struct mcontext __user *)(u64)cmcp; + /* no need to check access_ok(mcp), since mcp < 4GB */ } #else if (__get_user(mcp, &ucp->uc_regs)) return -EFAULT; + if (!access_ok(VERIFY_READ, mcp, sizeof(*mcp))) + return -EFAULT; #endif restore_sigmask(&set); if (restore_user_regs(regs, mcp, sig)) @@ -908,13 +911,14 @@ int sys_debug_setcontext(struct ucontext __user *ctx, { struct sig_dbg_op op; int i; + unsigned char tmp; unsigned long new_msr = regs->msr; #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) unsigned long new_dbcr0 = current->thread.dbcr0; #endif for (i=0; i<ndbg; i++) { - if (__copy_from_user(&op, dbg, sizeof(op))) + if (copy_from_user(&op, dbg + i, sizeof(op))) return -EFAULT; switch (op.dbg_type) { case SIG_DBG_SINGLE_STEPPING: @@ -959,6 +963,11 @@ int sys_debug_setcontext(struct ucontext __user *ctx, current->thread.dbcr0 = new_dbcr0; #endif + if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx)) + || __get_user(tmp, (u8 __user *) ctx) + || __get_user(tmp, (u8 __user *) (ctx + 1) - 1)) + return -EFAULT; + /* * If we get a fault copying the context into the kernel's * image of the user's registers, we can't just return -EFAULT diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index 27f65b95184d..c2db642f4cdd 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -182,6 +182,8 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig, err |= __get_user(msr, &sc->gp_regs[PT_MSR]); if (err) return err; + if (v_regs && !access_ok(VERIFY_READ, v_regs, 34 * sizeof(vector128))) + return -EFAULT; /* Copy 33 vec registers (vr0..31 and vscr) from the stack */ if (v_regs != 0 && (msr & MSR_VEC) != 0) err |= __copy_from_user(current->thread.vr, v_regs, diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c index 33654d1b1b43..994856e55b7c 100644 --- a/arch/powerpc/mm/hash_native_64.c +++ b/arch/powerpc/mm/hash_native_64.c @@ -52,7 +52,7 @@ static inline void __tlbie(unsigned long va, unsigned int psize) default: penc = mmu_psize_defs[psize].penc; va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); - va |= (0x7f >> (8 - penc)) << 12; + va |= penc << 12; asm volatile("tlbie %0,1" : : "r" (va) : "memory"); break; } @@ -74,7 +74,7 @@ static inline void __tlbiel(unsigned long va, unsigned int psize) default: penc = mmu_psize_defs[psize].penc; va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); - va |= (0x7f >> (8 - penc)) << 12; + va |= penc << 12; asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" : : "r"(va) : "memory"); break; diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c index 6574b22b3cf3..fd3e5609e3e0 100644 --- a/arch/powerpc/platforms/cell/setup.c +++ b/arch/powerpc/platforms/cell/setup.c @@ -125,14 +125,13 @@ static void __init cell_init_early(void) static int __init cell_probe(void) { - /* XXX This is temporary, the Cell maintainer will come up with - * more appropriate detection logic - */ unsigned long root = of_get_flat_dt_root(); - if (!of_flat_dt_is_compatible(root, "IBM,CPBW-1.0")) - return 0; - return 1; + if (of_flat_dt_is_compatible(root, "IBM,CBEA") || + of_flat_dt_is_compatible(root, "IBM,CPBW-1.0")) + return 1; + + return 0; } /* diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 5f79f01c44f2..3ba87835757e 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -389,6 +389,7 @@ static int __init pSeries_probe_hypertas(unsigned long node, static int __init pSeries_probe(void) { + unsigned long root = of_get_flat_dt_root(); char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), "device_type", NULL); if (dtype == NULL) @@ -396,6 +397,13 @@ static int __init pSeries_probe(void) if (strcmp(dtype, "chrp")) return 0; + /* Cell blades firmware claims to be chrp while it's not. Until this + * is fixed, we need to avoid those here. + */ + if (of_flat_dt_is_compatible(root, "IBM,CPBW-1.0") || + of_flat_dt_is_compatible(root, "IBM,CBEA")) + return 0; + DBG("pSeries detected, looking for LPAR capability...\n"); /* Now try to figure out if we are running on LPAR */ diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c index a93f5da6855d..40b42c88e6a7 100644 --- a/arch/sparc/kernel/smp.c +++ b/arch/sparc/kernel/smp.c @@ -69,6 +69,17 @@ void __init smp_store_cpu_info(int id) "clock-frequency", 0); cpu_data(id).prom_node = cpu_node; cpu_data(id).mid = cpu_get_hwmid(cpu_node); + + /* this is required to tune the scheduler correctly */ + /* is it possible to have CPUs with different cache sizes? */ + if (id == boot_cpu_id) { + int cache_line,cache_nlines; + cache_line = 0x20; + cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line); + cache_nlines = 0x8000; + cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines); + max_cache_size = cache_line * cache_nlines; + } if (cpu_data(id).mid < 0) panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); } diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c index 2b7a1f316a93..0c0895202970 100644 --- a/arch/sparc64/kernel/pci_sun4v.c +++ b/arch/sparc64/kernel/pci_sun4v.c @@ -599,18 +599,128 @@ struct pci_iommu_ops pci_sun4v_iommu_ops = { /* SUN4V PCI configuration space accessors. */ -static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func) +struct pdev_entry { + struct pdev_entry *next; + u32 devhandle; + unsigned int bus; + unsigned int device; + unsigned int func; +}; + +#define PDEV_HTAB_SIZE 16 +#define PDEV_HTAB_MASK (PDEV_HTAB_SIZE - 1) +static struct pdev_entry *pdev_htab[PDEV_HTAB_SIZE]; + +static inline unsigned int pdev_hashfn(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func) { - if (bus == pbm->pci_first_busno) { - if (device == 0 && func == 0) - return 0; - return 1; + unsigned int val; + + val = (devhandle ^ (devhandle >> 4)); + val ^= bus; + val ^= device; + val ^= func; + + return val & PDEV_HTAB_MASK; +} + +static int pdev_htab_add(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func) +{ + struct pdev_entry *p = kmalloc(sizeof(*p), GFP_KERNEL); + struct pdev_entry **slot; + + if (!p) + return -ENOMEM; + + slot = &pdev_htab[pdev_hashfn(devhandle, bus, device, func)]; + p->next = *slot; + *slot = p; + + p->devhandle = devhandle; + p->bus = bus; + p->device = device; + p->func = func; + + return 0; +} + +/* Recursively descend into the OBP device tree, rooted at toplevel_node, + * looking for a PCI device matching bus and devfn. + */ +static int obp_find(struct linux_prom_pci_registers *pregs, int toplevel_node, unsigned int bus, unsigned int devfn) +{ + toplevel_node = prom_getchild(toplevel_node); + + while (toplevel_node != 0) { + int ret = obp_find(pregs, toplevel_node, bus, devfn); + + if (ret != 0) + return ret; + + ret = prom_getproperty(toplevel_node, "reg", (char *) pregs, + sizeof(*pregs) * PROMREG_MAX); + if (ret == 0 || ret == -1) + goto next_sibling; + + if (((pregs[0].phys_hi >> 16) & 0xff) == bus && + ((pregs[0].phys_hi >> 8) & 0xff) == devfn) + break; + + next_sibling: + toplevel_node = prom_getsibling(toplevel_node); + } + + return toplevel_node; +} + +static int pdev_htab_populate(struct pci_pbm_info *pbm) +{ + struct linux_prom_pci_registers pr[PROMREG_MAX]; + u32 devhandle = pbm->devhandle; + unsigned int bus; + + for (bus = pbm->pci_first_busno; bus <= pbm->pci_last_busno; bus++) { + unsigned int devfn; + + for (devfn = 0; devfn < 256; devfn++) { + unsigned int device = PCI_SLOT(devfn); + unsigned int func = PCI_FUNC(devfn); + + if (obp_find(pr, pbm->prom_node, bus, devfn)) { + int err = pdev_htab_add(devhandle, bus, + device, func); + if (err) + return err; + } + } + } + + return 0; +} + +static struct pdev_entry *pdev_find(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func) +{ + struct pdev_entry *p; + + p = pdev_htab[pdev_hashfn(devhandle, bus, device, func)]; + while (p) { + if (p->devhandle == devhandle && + p->bus == bus && + p->device == device && + p->func == func) + break; + + p = p->next; } + return p; +} + +static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func) +{ if (bus < pbm->pci_first_busno || bus > pbm->pci_last_busno) return 1; - return 0; + return pdev_find(pbm->devhandle, bus, device, func) == NULL; } static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, @@ -1063,6 +1173,8 @@ static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node, u32 pci_sun4v_get_bus_range(pbm); pci_sun4v_iommu_init(pbm); + + pdev_htab_populate(pbm); } void sun4v_pci_init(int node, char *model_name) diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c index 4e8cd79156e0..f03d52d0b88d 100644 --- a/arch/sparc64/kernel/smp.c +++ b/arch/sparc64/kernel/smp.c @@ -1287,6 +1287,40 @@ int setup_profiling_timer(unsigned int multiplier) return 0; } +static void __init smp_tune_scheduling(void) +{ + int instance, node; + unsigned int def, smallest = ~0U; + + def = ((tlb_type == hypervisor) ? + (3 * 1024 * 1024) : + (4 * 1024 * 1024)); + + instance = 0; + while (!cpu_find_by_instance(instance, &node, NULL)) { + unsigned int val; + + val = prom_getintdefault(node, "ecache-size", def); + if (val < smallest) + smallest = val; + + instance++; + } + + /* Any value less than 256K is nonsense. */ + if (smallest < (256U * 1024U)) + smallest = 256 * 1024; + + max_cache_size = smallest; + + if (smallest < 1U * 1024U * 1024U) + printk(KERN_INFO "Using max_cache_size of %uKB\n", + smallest / 1024U); + else + printk(KERN_INFO "Using max_cache_size of %uMB\n", + smallest / 1024U / 1024U); +} + /* Constrain the number of cpus to max_cpus. */ void __init smp_prepare_cpus(unsigned int max_cpus) { @@ -1322,6 +1356,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } smp_store_cpu_info(boot_cpu_id); + smp_tune_scheduling(); } /* Set this up early so that things like the scheduler can init diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c index 62d8a99271ea..38e569f786dd 100644 --- a/arch/sparc64/kernel/sparc64_ksyms.c +++ b/arch/sparc64/kernel/sparc64_ksyms.c @@ -297,7 +297,6 @@ EXPORT_SYMBOL(svr4_getcontext); EXPORT_SYMBOL(svr4_setcontext); EXPORT_SYMBOL(compat_sys_ioctl); EXPORT_SYMBOL(sparc32_open); -EXPORT_SYMBOL(sys_close); #endif /* Special internal versions of library functions. */ diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c index 2793a5d82380..563db528e031 100644 --- a/arch/sparc64/kernel/traps.c +++ b/arch/sparc64/kernel/traps.c @@ -1797,7 +1797,9 @@ static const char *sun4v_err_type_to_str(u32 type) }; } -static void sun4v_log_error(struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt) +extern void __show_regs(struct pt_regs * regs); + +static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt) { int cnt; @@ -1830,6 +1832,8 @@ static void sun4v_log_error(struct sun4v_error_entry *ent, int cpu, const char * pfx, ent->err_raddr, ent->err_size, ent->err_cpu); + __show_regs(regs); + if ((cnt = atomic_read(ocnt)) != 0) { atomic_set(ocnt, 0); wmb(); @@ -1862,7 +1866,7 @@ void sun4v_resum_error(struct pt_regs *regs, unsigned long offset) put_cpu(); - sun4v_log_error(&local_copy, cpu, + sun4v_log_error(regs, &local_copy, cpu, KERN_ERR "RESUMABLE ERROR", &sun4v_resum_oflow_cnt); } @@ -1910,7 +1914,7 @@ void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset) } #endif - sun4v_log_error(&local_copy, cpu, + sun4v_log_error(regs, &local_copy, cpu, KERN_EMERG "NON-RESUMABLE ERROR", &sun4v_nonresum_oflow_cnt); @@ -2200,7 +2204,6 @@ static inline struct reg_window *kernel_stack_up(struct reg_window *rw) void die_if_kernel(char *str, struct pt_regs *regs) { static int die_counter; - extern void __show_regs(struct pt_regs * regs); extern void smp_report_regs(void); int count = 0; |
