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-rw-r--r--arch/sh/kernel/cpu/sh2/clock-sh7619.c4
-rw-r--r--arch/sh/kernel/cpu/sh2/entry.S12
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c32
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c62
4 files changed, 52 insertions, 58 deletions
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index d0440b269702..d2c157917999 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -18,8 +18,8 @@
#include <asm/freq.h>
#include <asm/io.h>
-const static int pll1rate[]={1,2};
-const static int pfc_divisors[]={1,2,0,4};
+static const int pll1rate[] = {1,2};
+static const int pfc_divisors[] = {1,2,0,4};
#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
#define PLL2 (4)
diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S
index d51fa5e9904a..7f7d292f36ec 100644
--- a/arch/sh/kernel/cpu/sh2/entry.S
+++ b/arch/sh/kernel/cpu/sh2/entry.S
@@ -178,12 +178,10 @@ interrupt_entry:
8: .long do_exception_error
trap_entry:
- /* verbose BUG trapa entry check */
- mov #0x3e,r8
- cmp/ge r8,r9
- bf/s 1f
- add #-0x10,r9
- add #0x10,r9
+ mov #0x30,r8
+ cmp/ge r8,r9 ! vector 0x20-0x2f is systemcall
+ bt 1f
+ add #-0x10,r9 ! convert SH2 to SH3/4 ABI
1:
shll2 r9 ! TRA
mov #OFF_TRA,r8
@@ -206,7 +204,7 @@ trap_entry:
#if defined(CONFIG_SH_STANDARD_BIOS)
/* Unwind the stack and jmp to the debug entry */
-debug_kernel_fw:
+ENTRY(sh_bios_handler)
mov r15,r0
add #(22-4)*4-4,r0
ldc.l @r0+,gbr
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index ba527d9b5024..108e81b682ed 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -18,27 +18,27 @@
int __init detect_cpu_and_cache_system(void)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7604)
- cpu_data->type = CPU_SH7604;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1<<10);
- cpu_data->dcache.sets = 64;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.type = CPU_SH7604;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1<<10);
+ current_cpu_data.dcache.sets = 64;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
- cpu_data->type = CPU_SH7619;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1<<12);
- cpu_data->dcache.sets = 256;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.type = CPU_SH7619;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1<<12);
+ current_cpu_data.dcache.sets = 256;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
#endif
/*
* SH-2 doesn't have separate caches
*/
- cpu_data->dcache.flags |= SH_CACHE_COMBINED;
- cpu_data->icache = cpu_data->dcache;
+ current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+ current_cpu_data.icache = current_cpu_data.dcache;
return 0;
}
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 79283e6c1d8f..f83ff8a68f35 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -52,42 +52,38 @@ static int __init sh7619_devices_setup(void)
}
__initcall(sh7619_devices_setup);
-#define INTC_IPRC 0xf8080000UL
-#define INTC_IPRD 0xf8080002UL
-
-#define CMI0_IRQ 86
-
-#define SCIF0_ERI_IRQ 88
-#define SCIF0_RXI_IRQ 89
-#define SCIF0_BRI_IRQ 90
-#define SCIF0_TXI_IRQ 91
-
-#define SCIF1_ERI_IRQ 92
-#define SCIF1_RXI_IRQ 93
-#define SCIF1_BRI_IRQ 94
-#define SCIF1_TXI_IRQ 95
-
-#define SCIF2_BRI_IRQ 96
-#define SCIF2_ERI_IRQ 97
-#define SCIF2_RXI_IRQ 98
-#define SCIF2_TXI_IRQ 99
-
static struct ipr_data sh7619_ipr_map[] = {
- { CMI0_IRQ, INTC_IPRC, 1, 2 },
- { SCIF0_ERI_IRQ, INTC_IPRD, 3, 3 },
- { SCIF0_RXI_IRQ, INTC_IPRD, 3, 3 },
- { SCIF0_BRI_IRQ, INTC_IPRD, 3, 3 },
- { SCIF0_TXI_IRQ, INTC_IPRD, 3, 3 },
- { SCIF1_ERI_IRQ, INTC_IPRD, 2, 3 },
- { SCIF1_RXI_IRQ, INTC_IPRD, 2, 3 },
- { SCIF1_BRI_IRQ, INTC_IPRD, 2, 3 },
- { SCIF1_TXI_IRQ, INTC_IPRD, 2, 3 },
- { SCIF2_ERI_IRQ, INTC_IPRD, 1, 3 },
- { SCIF2_RXI_IRQ, INTC_IPRD, 1, 3 },
- { SCIF2_BRI_IRQ, INTC_IPRD, 1, 3 },
- { SCIF2_TXI_IRQ, INTC_IPRD, 1, 3 },
+ { 86, 0, 4, 2 }, /* CMI0 */
+ { 88, 1, 12, 3 }, /* SCIF0_ERI */
+ { 89, 1, 12, 3 }, /* SCIF0_RXI */
+ { 90, 1, 12, 3 }, /* SCIF0_BRI */
+ { 91, 1, 12, 3 }, /* SCIF0_TXI */
+ { 92, 1, 8, 3 }, /* SCIF1_ERI */
+ { 93, 1, 8, 3 }, /* SCIF1_RXI */
+ { 94, 1, 8, 3 }, /* SCIF1_BRI */
+ { 95, 1, 8, 3 }, /* SCIF1_TXI */
+ { 96, 1, 4, 3 }, /* SCIF2_ERI */
+ { 97, 1, 4, 3 }, /* SCIF2_RXI */
+ { 98, 1, 4, 3 }, /* SCIF2_BRI */
+ { 99, 1, 4, 3 }, /* SCIF2_TXI */
};
+static unsigned int ipr_offsets[] = {
+ 0xf8080000, /* IPRC */
+ 0xf8080002, /* IPRD */
+ 0xf8080004, /* IPRE */
+ 0xf8080006, /* IPRF */
+ 0xf8080008, /* IPRG */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+ if (unlikely(idx >= ARRAY_SIZE(ipr_offsets)))
+ return 0;
+ return ipr_offsets[idx];
+}
+
void __init init_IRQ_ipr(void)
{
make_ipr_irq(sh7619_ipr_map, ARRAY_SIZE(sh7619_ipr_map));
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