diff options
Diffstat (limited to 'arch/ppc/syslib')
28 files changed, 44 insertions, 4204 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 543795be58c8..52ddebe6c6d1 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -87,20 +87,6 @@ endif obj-$(CONFIG_BOOTX_TEXT) += btext.o obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o ppc_sys.o obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o -obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \ - ppc_sys.o mpc85xx_sys.o \ - mpc85xx_devices.o -ifeq ($(CONFIG_85xx),y) -obj-$(CONFIG_PCI) += pci_auto.o -endif -obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o -obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \ - mpc83xx_sys.o mpc83xx_devices.o ipic.o -ifeq ($(CONFIG_83xx),y) -obj-$(CONFIG_PCI) += pci_auto.o -endif -obj-$(CONFIG_MPC8548_CDS) += todc_time.o -obj-$(CONFIG_MPC8555_CDS) += todc_time.o obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o ifeq ($(CONFIG_PPC_MPC52xx),y) diff --git a/arch/ppc/syslib/gt64260_pic.c b/arch/ppc/syslib/gt64260_pic.c index e84d432c0657..3b4fcca5d1e1 100644 --- a/arch/ppc/syslib/gt64260_pic.c +++ b/arch/ppc/syslib/gt64260_pic.c @@ -35,7 +35,6 @@ #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/signal.h> -#include <linux/stddef.h> #include <linux/delay.h> #include <linux/irq.h> diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c deleted file mode 100644 index 9192777d0f78..000000000000 --- a/arch/ppc/syslib/ipic.c +++ /dev/null @@ -1,646 +0,0 @@ -/* - * arch/ppc/syslib/ipic.c - * - * IPIC routines implementations. - * - * Copyright 2005 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/reboot.h> -#include <linux/slab.h> -#include <linux/stddef.h> -#include <linux/sched.h> -#include <linux/signal.h> -#include <linux/sysdev.h> -#include <asm/irq.h> -#include <asm/io.h> -#include <asm/ipic.h> -#include <asm/mpc83xx.h> - -#include "ipic.h" - -static struct ipic p_ipic; -static struct ipic * primary_ipic; - -static struct ipic_info ipic_info[] = { - [9] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 24, - .prio_mask = 0, - }, - [10] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 25, - .prio_mask = 1, - }, - [11] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 26, - .prio_mask = 2, - }, - [14] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 29, - .prio_mask = 5, - }, - [15] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 30, - .prio_mask = 6, - }, - [16] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 31, - .prio_mask = 7, - }, - [17] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 1, - .prio_mask = 5, - }, - [18] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 2, - .prio_mask = 6, - }, - [19] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 3, - .prio_mask = 7, - }, - [20] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 4, - .prio_mask = 4, - }, - [21] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 5, - .prio_mask = 5, - }, - [22] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 6, - .prio_mask = 6, - }, - [23] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 7, - .prio_mask = 7, - }, - [32] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 0, - .prio_mask = 0, - }, - [33] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 1, - .prio_mask = 1, - }, - [34] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 2, - .prio_mask = 2, - }, - [35] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 3, - .prio_mask = 3, - }, - [36] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 4, - .prio_mask = 4, - }, - [37] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 5, - .prio_mask = 5, - }, - [38] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 6, - .prio_mask = 6, - }, - [39] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 7, - .prio_mask = 7, - }, - [48] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 0, - .prio_mask = 4, - }, - [64] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 0, - .prio_mask = 0, - }, - [65] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 1, - .prio_mask = 1, - }, - [66] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 2, - .prio_mask = 2, - }, - [67] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 3, - .prio_mask = 3, - }, - [68] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 4, - .prio_mask = 0, - }, - [69] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 5, - .prio_mask = 1, - }, - [70] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 6, - .prio_mask = 2, - }, - [71] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 7, - .prio_mask = 3, - }, - [72] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 8, - }, - [73] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 9, - }, - [74] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 10, - }, - [75] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 11, - }, - [76] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 12, - }, - [77] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 13, - }, - [78] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 14, - }, - [79] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 15, - }, - [80] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 16, - }, - [84] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 20, - }, - [85] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 21, - }, - [90] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 26, - }, - [91] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 27, - }, -}; - -static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg) -{ - return in_be32(base + (reg >> 2)); -} - -static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value) -{ - out_be32(base + (reg >> 2), value); -} - -static inline struct ipic * ipic_from_irq(unsigned int irq) -{ - return primary_ipic; -} - -static void ipic_enable_irq(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - temp = ipic_read(ipic->regs, ipic_info[src].mask); - temp |= (1 << (31 - ipic_info[src].bit)); - ipic_write(ipic->regs, ipic_info[src].mask, temp); -} - -static void ipic_disable_irq(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - temp = ipic_read(ipic->regs, ipic_info[src].mask); - temp &= ~(1 << (31 - ipic_info[src].bit)); - ipic_write(ipic->regs, ipic_info[src].mask, temp); -} - -static void ipic_disable_irq_and_ack(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - ipic_disable_irq(irq); - - temp = ipic_read(ipic->regs, ipic_info[src].pend); - temp |= (1 << (31 - ipic_info[src].bit)); - ipic_write(ipic->regs, ipic_info[src].pend, temp); -} - -static void ipic_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - ipic_enable_irq(irq); -} - -struct hw_interrupt_type ipic = { - .typename = " IPIC ", - .enable = ipic_enable_irq, - .disable = ipic_disable_irq, - .ack = ipic_disable_irq_and_ack, - .end = ipic_end_irq, -}; - -void __init ipic_init(phys_addr_t phys_addr, - unsigned int flags, - unsigned int irq_offset, - unsigned char *senses, - unsigned int senses_count) -{ - u32 i, temp = 0; - - primary_ipic = &p_ipic; - primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE); - - primary_ipic->irq_offset = irq_offset; - - ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0); - - /* default priority scheme is grouped. If spread mode is required - * configure SICFR accordingly */ - if (flags & IPIC_SPREADMODE_GRP_A) - temp |= SICFR_IPSA; - if (flags & IPIC_SPREADMODE_GRP_D) - temp |= SICFR_IPSD; - if (flags & IPIC_SPREADMODE_MIX_A) - temp |= SICFR_MPSA; - if (flags & IPIC_SPREADMODE_MIX_B) - temp |= SICFR_MPSB; - - ipic_write(primary_ipic->regs, IPIC_SICNR, temp); - - /* handle MCP route */ - temp = 0; - if (flags & IPIC_DISABLE_MCP_OUT) - temp = SERCR_MCPR; - ipic_write(primary_ipic->regs, IPIC_SERCR, temp); - - /* handle routing of IRQ0 to MCP */ - temp = ipic_read(primary_ipic->regs, IPIC_SEMSR); - - if (flags & IPIC_IRQ0_MCP) - temp |= SEMSR_SIRQ0; - else - temp &= ~SEMSR_SIRQ0; - - ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); - - for (i = 0 ; i < NR_IPIC_INTS ; i++) { - irq_desc[i+irq_offset].chip = &ipic; - irq_desc[i+irq_offset].status = IRQ_LEVEL; - } - - temp = 0; - for (i = 0 ; i < senses_count ; i++) { - if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) { - temp |= 1 << (15 - i); - if (i != 0) - irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0; - else - irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0; - } - } - ipic_write(primary_ipic->regs, IPIC_SECNR, temp); - - printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS, - senses_count, primary_ipic->regs); -} - -int ipic_set_priority(unsigned int irq, unsigned int priority) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - if (priority > 7) - return -EINVAL; - if (src > 127) - return -EINVAL; - if (ipic_info[src].prio == 0) - return -EINVAL; - - temp = ipic_read(ipic->regs, ipic_info[src].prio); - - if (priority < 4) { - temp &= ~(0x7 << (20 + (3 - priority) * 3)); - temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3); - } else { - temp &= ~(0x7 << (4 + (7 - priority) * 3)); - temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3); - } - - ipic_write(ipic->regs, ipic_info[src].prio, temp); - - return 0; -} - -void ipic_set_highest_priority(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - temp = ipic_read(ipic->regs, IPIC_SICFR); - - /* clear and set HPI */ - temp &= 0x7f000000; - temp |= (src & 0x7f) << 24; - - ipic_write(ipic->regs, IPIC_SICFR, temp); -} - -void ipic_set_default_priority(void) -{ - ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0); - ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1); - ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2); - ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3); - ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4); - ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5); - ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6); - ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7); - - ipic_set_priority(MPC83xx_IRQ_UART1, 0); - ipic_set_priority(MPC83xx_IRQ_UART2, 1); - ipic_set_priority(MPC83xx_IRQ_SEC2, 2); - ipic_set_priority(MPC83xx_IRQ_IIC1, 5); - ipic_set_priority(MPC83xx_IRQ_IIC2, 6); - ipic_set_priority(MPC83xx_IRQ_SPI, 7); - ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0); - ipic_set_priority(MPC83xx_IRQ_PIT, 1); - ipic_set_priority(MPC83xx_IRQ_PCI1, 2); - ipic_set_priority(MPC83xx_IRQ_PCI2, 3); - ipic_set_priority(MPC83xx_IRQ_EXT0, 4); - ipic_set_priority(MPC83xx_IRQ_EXT1, 5); - ipic_set_priority(MPC83xx_IRQ_EXT2, 6); - ipic_set_priority(MPC83xx_IRQ_EXT3, 7); - ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0); - ipic_set_priority(MPC83xx_IRQ_MU, 1); - ipic_set_priority(MPC83xx_IRQ_SBA, 2); - ipic_set_priority(MPC83xx_IRQ_DMA, 3); - ipic_set_priority(MPC83xx_IRQ_EXT4, 4); - ipic_set_priority(MPC83xx_IRQ_EXT5, 5); - ipic_set_priority(MPC83xx_IRQ_EXT6, 6); - ipic_set_priority(MPC83xx_IRQ_EXT7, 7); -} - -void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) -{ - struct ipic *ipic = primary_ipic; - u32 temp; - - temp = ipic_read(ipic->regs, IPIC_SERMR); - temp |= (1 << (31 - mcp_irq)); - ipic_write(ipic->regs, IPIC_SERMR, temp); -} - -void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq) -{ - struct ipic *ipic = primary_ipic; - u32 temp; - - temp = ipic_read(ipic->regs, IPIC_SERMR); - temp &= (1 << (31 - mcp_irq)); - ipic_write(ipic->regs, IPIC_SERMR, temp); -} - -u32 ipic_get_mcp_status(void) -{ - return ipic_read(primary_ipic->regs, IPIC_SERMR); -} - -void ipic_clear_mcp_status(u32 mask) -{ - ipic_write(primary_ipic->regs, IPIC_SERMR, mask); -} - -/* Return an interrupt vector or -1 if no interrupt is pending. */ -int ipic_get_irq(void) -{ - int irq; - - irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f; - - if (irq == 0) /* 0 --> no irq is pending */ - irq = -1; - - return irq; -} - -static struct sysdev_class ipic_sysclass = { - set_kset_name("ipic"), -}; - -static struct sys_device device_ipic = { - .id = 0, - .cls = &ipic_sysclass, -}; - -static int __init init_ipic_sysfs(void) -{ - int rc; - - if (!primary_ipic->regs) - return -ENODEV; - printk(KERN_DEBUG "Registering ipic with sysfs...\n"); - - rc = sysdev_class_register(&ipic_sysclass); - if (rc) { - printk(KERN_ERR "Failed registering ipic sys class\n"); - return -ENODEV; - } - rc = sysdev_register(&device_ipic); - if (rc) { - printk(KERN_ERR "Failed registering ipic sys device\n"); - return -ENODEV; - } - return 0; -} - -subsys_initcall(init_ipic_sysfs); diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h deleted file mode 100644 index a60c9d18bb7f..000000000000 --- a/arch/ppc/syslib/ipic.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * IPIC private definitions and structure. - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef __IPIC_H__ -#define __IPIC_H__ - -#include <asm/ipic.h> - -#define MPC83xx_IPIC_SIZE (0x00100) - -/* System Global Interrupt Configuration Register */ -#define SICFR_IPSA 0x00010000 -#define SICFR_IPSD 0x00080000 -#define SICFR_MPSA 0x00200000 -#define SICFR_MPSB 0x00400000 - -/* System External Interrupt Mask Register */ -#define SEMSR_SIRQ0 0x00008000 - -/* System Error Control Register */ -#define SERCR_MCPR 0x00000001 - -struct ipic { - volatile u32 __iomem *regs; - unsigned int irq_offset; -}; - -struct ipic_info { - u8 pend; /* pending register offset from base */ - u8 mask; /* mask register offset from base */ - u8 prio; /* priority register offset from base */ - u8 force; /* force register offset from base */ - u8 bit; /* register bit position (as per doc) - bit mask = 1 << (31 - bit) */ - u8 prio_mask; /* priority mask value */ -}; - -#endif /* __IPIC_H__ */ diff --git a/arch/ppc/syslib/mpc52xx_pic.c b/arch/ppc/syslib/mpc52xx_pic.c index af35a316544a..f58149c03b0f 100644 --- a/arch/ppc/syslib/mpc52xx_pic.c +++ b/arch/ppc/syslib/mpc52xx_pic.c @@ -20,7 +20,6 @@ #include <linux/init.h> #include <linux/sched.h> #include <linux/signal.h> -#include <linux/stddef.h> #include <linux/delay.h> #include <linux/irq.h> diff --git a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c index ecfa2c0f8ba3..9f504fc7693e 100644 --- a/arch/ppc/syslib/mpc52xx_setup.c +++ b/arch/ppc/syslib/mpc52xx_setup.c @@ -16,6 +16,7 @@ */ +#include <linux/spinlock.h> #include <asm/io.h> #include <asm/time.h> #include <asm/mpc52xx.h> @@ -275,3 +276,38 @@ int mpc52xx_match_psc_function(int psc_idx, const char *func) return 0; } + +int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv) +{ + static spinlock_t lock = SPIN_LOCK_UNLOCKED; + struct mpc52xx_cdm __iomem *cdm; + unsigned long flags; + u16 mclken_div; + u16 __iomem *reg; + u32 mask; + + cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE); + if (!cdm) { + printk(KERN_ERR __FILE__ ": Error mapping CDM\n"); + return -ENODEV; + } + + mclken_div = 0x8000 | (clkdiv & 0x1FF); + switch (psc_id) { + case 1: reg = &cdm->mclken_div_psc1; mask = 0x20; break; + case 2: reg = &cdm->mclken_div_psc2; mask = 0x40; break; + case 3: reg = &cdm->mclken_div_psc3; mask = 0x80; break; + case 6: reg = &cdm->mclken_div_psc6; mask = 0x10; break; + default: + return -ENODEV; + } + + /* Set the rate and enable the clock */ + spin_lock_irqsave(&lock, flags); + out_be16(reg, mclken_div); + out_be32(&cdm->clk_enables, in_be32(&cdm->clk_enables) | mask); + spin_unlock_irqrestore(&lock, flags); + + iounmap(cdm); + return 0; +} diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c deleted file mode 100644 index 5c4932ca8e9b..000000000000 --- a/arch/ppc/syslib/mpc83xx_devices.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * MPC83xx Device descriptions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/device.h> -#include <linux/serial_8250.h> -#include <linux/fsl_devices.h> -#include <asm/mpc83xx.h> -#include <asm/irq.h> -#include <asm/ppc_sys.h> -#include <asm/machdep.h> - -/* We use offsets for IORESOURCE_MEM since we do not know at compile time - * what IMMRBAR is, will get fixed up by mach_mpc83xx_fixup - */ - -struct gianfar_mdio_data mpc83xx_mdio_pdata = { -}; - -static struct gianfar_platform_data mpc83xx_tsec1_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR, -}; - -static struct gianfar_platform_data mpc83xx_tsec2_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR, -}; - -static struct fsl_i2c_platform_data mpc83xx_fsl_i2c1_pdata = { - .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, -}; - -static struct fsl_i2c_platform_data mpc83xx_fsl_i2c2_pdata = { - .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, -}; - -static struct plat_serial8250_port serial_platform_data[] = { - [0] = { - .mapbase = 0x4500, - .irq = MPC83xx_IRQ_UART1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - [1] = { - .mapbase = 0x4600, - .irq = MPC83xx_IRQ_UART2, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; - -struct platform_device ppc_sys_platform_devices[] = { - [MPC83xx_TSEC1] = { - .name = "fsl-gianfar", - .id = 1, - .dev.platform_data = &mpc83xx_tsec1_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = 0x24000, - .end = 0x24fff, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC83xx_IRQ_TSEC1_TX, - .end = MPC83xx_IRQ_TSEC1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC83xx_IRQ_TSEC1_RX, - .end = MPC83xx_IRQ_TSEC1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC83xx_IRQ_TSEC1_ERROR, - .end = MPC83xx_IRQ_TSEC1_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_TSEC2] = { - .name = "fsl-gianfar", - .id = 2, - .dev.platform_data = &mpc83xx_tsec2_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = 0x25000, - .end = 0x25fff, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC83xx_IRQ_TSEC2_TX, - .end = MPC83xx_IRQ_TSEC2_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC83xx_IRQ_TSEC2_RX, - .end = MPC83xx_IRQ_TSEC2_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC83xx_IRQ_TSEC2_ERROR, - .end = MPC83xx_IRQ_TSEC2_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_IIC1] = { - .name = "fsl-i2c", - .id = 1, - .dev.platform_data = &mpc83xx_fsl_i2c1_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3000, - .end = 0x30ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_IIC1, - .end = MPC83xx_IRQ_IIC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_IIC2] = { - .name = "fsl-i2c", - .id = 2, - .dev.platform_data = &mpc83xx_fsl_i2c2_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3100, - .end = 0x31ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_IIC2, - .end = MPC83xx_IRQ_IIC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_DUART] = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = serial_platform_data, - }, - [MPC83xx_SEC2] = { - .name = "fsl-sec2", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x30000, - .end = 0x3ffff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_SEC2, - .end = MPC83xx_IRQ_SEC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_USB2_DR] = { - .name = "fsl-ehci", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x23000, - .end = 0x23fff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_USB2_DR, - .end = MPC83xx_IRQ_USB2_DR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_USB2_MPH] = { - .name = "fsl-ehci", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x22000, - .end = 0x22fff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_USB2_MPH, - .end = MPC83xx_IRQ_USB2_MPH, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_MDIO] = { - .name = "fsl-gianfar_mdio", - .id = 0, - .dev.platform_data = &mpc83xx_mdio_pdata, - .num_resources = 1, - .resource = (struct resource[]) { - { - .start = 0x24520, - .end = 0x2453f, - .flags = IORESOURCE_MEM, - }, - }, - }, -}; - -static int __init mach_mpc83xx_fixup(struct platform_device *pdev) -{ - ppc_sys_fixup_mem_resource(pdev, immrbar); - return 0; -} - -static int __init mach_mpc83xx_init(void) -{ - if (ppc_md.progress) - ppc_md.progress("mach_mpc83xx_init:enter", 0); - ppc_sys_device_fixup = mach_mpc83xx_fixup; - return 0; -} - -postcore_initcall(mach_mpc83xx_init); diff --git a/arch/ppc/syslib/mpc83xx_sys.c b/arch/ppc/syslib/mpc83xx_sys.c deleted file mode 100644 index 0498ae7e01e3..000000000000 --- a/arch/ppc/syslib/mpc83xx_sys.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * MPC83xx System descriptions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/device.h> -#include <asm/ppc_sys.h> - -struct ppc_sys_spec *cur_ppc_sys_spec; -struct ppc_sys_spec ppc_sys_specs[] = { - { - .ppc_sys_name = "8349E", - .mask = 0xFFFF0000, - .value = 0x80500000, - .num_devices = 9, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8349", - .mask = 0xFFFF0000, - .value = 0x80510000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347E", - .mask = 0xFFFF0000, - .value = 0x80520000, - .num_devices = 9, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347", - .mask = 0xFFFF0000, - .value = 0x80530000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347E", - .mask = 0xFFFF0000, - .value = 0x80540000, - .num_devices = 9, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347", - .mask = 0xFFFF0000, - .value = 0x80550000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8343E", - .mask = 0xFFFF0000, - .value = 0x80560000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8343", - .mask = 0xFFFF0000, - .value = 0x80570000, - .num_devices = 7, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_MDIO - }, - }, - { /* default match */ - .ppc_sys_name = "", - .mask = 0x00000000, - .value = 0x00000000, - }, -}; diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c deleted file mode 100644 index 325136e5aee0..000000000000 --- a/arch/ppc/syslib/mpc85xx_devices.c +++ /dev/null @@ -1,826 +0,0 @@ -/* - * MPC85xx Device descriptions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/device.h> -#include <linux/serial_8250.h> -#include <linux/fsl_devices.h> -#include <linux/fs_enet_pd.h> -#include <asm/mpc85xx.h> -#include <asm/irq.h> -#include <asm/ppc_sys.h> -#include <asm/cpm2.h> - -/* We use offsets for IORESOURCE_MEM since we do not know at compile time - * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup - */ -struct gianfar_mdio_data mpc85xx_mdio_pdata = { -}; - -static struct gianfar_platform_data mpc85xx_tsec1_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR, -}; - -static struct gianfar_platform_data mpc85xx_tsec2_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR, -}; - -static struct gianfar_platform_data mpc85xx_etsec1_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR | - FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | - FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, -}; - -static struct gianfar_platform_data mpc85xx_etsec2_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR | - FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | - FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, -}; - -static struct gianfar_platform_data mpc85xx_etsec3_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR | - FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | - FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, -}; - -static struct gianfar_platform_data mpc85xx_etsec4_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR | - FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | - FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, -}; - -static struct gianfar_platform_data mpc85xx_fec_pdata = { - .device_flags = 0, -}; - -static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = { - .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, -}; - -static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = { - .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, -}; - -static struct fs_platform_info mpc85xx_fcc1_pdata = { - .fs_no = fsid_fcc1, - .cp_page = CPM_CR_FCC1_PAGE, - .cp_block = CPM_CR_FCC1_SBLOCK, - - .rx_ring = 32, - .tx_ring = 32, - .rx_copybreak = 240, - .use_napi = 0, - .napi_weight = 17, - - .clk_mask = CMX1_CLK_MASK, - .clk_route = CMX1_CLK_ROUTE, - .clk_trx = (PC_F1RXCLK | PC_F1TXCLK), - - .mem_offset = FCC1_MEM_OFFSET, -}; - -static struct fs_platform_info mpc85xx_fcc2_pdata = { - .fs_no = fsid_fcc2, - .cp_page = CPM_CR_FCC2_PAGE, - .cp_block = CPM_CR_FCC2_SBLOCK, - - .rx_ring = 32, - .tx_ring = 32, - .rx_copybreak = 240, - .use_napi = 0, - .napi_weight = 17, - - .clk_mask = CMX2_CLK_MASK, - .clk_route = CMX2_CLK_ROUTE, - .clk_trx = (PC_F2RXCLK | PC_F2TXCLK), - - .mem_offset = FCC2_MEM_OFFSET, -}; - -static struct fs_platform_info mpc85xx_fcc3_pdata = { - .fs_no = fsid_fcc3, - .cp_page = CPM_CR_FCC3_PAGE, - .cp_block = CPM_CR_FCC3_SBLOCK, - - .rx_ring = 32, - .tx_ring = 32, - .rx_copybreak = 240, - .use_napi = 0, - .napi_weight = 17, - - .clk_mask = CMX3_CLK_MASK, - .clk_route = CMX3_CLK_ROUTE, - .clk_trx = (PC_F3RXCLK | PC_F3TXCLK), - - .mem_offset = FCC3_MEM_OFFSET, -}; - -static struct plat_serial8250_port serial_platform_data[] = { - [0] = { - .mapbase = 0x4500, - .irq = MPC85xx_IRQ_DUART, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ, - }, - [1] = { - .mapbase = 0x4600, - .irq = MPC85xx_IRQ_DUART, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ, - }, - { }, -}; - -struct platform_device ppc_sys_platform_devices[] = { - [MPC85xx_TSEC1] = { - .name = "fsl-gianfar", - .id = 1, - .dev.platform_data = &mpc85xx_tsec1_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = MPC85xx_ENET1_OFFSET, - .end = MPC85xx_ENET1_OFFSET + - MPC85xx_ENET1_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC85xx_IRQ_TSEC1_TX, - .end = MPC85xx_IRQ_TSEC1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC85xx_IRQ_TSEC1_RX, - .end = MPC85xx_IRQ_TSEC1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC85xx_IRQ_TSEC1_ERROR, - .end = MPC85xx_IRQ_TSEC1_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_TSEC2] = { - .name = "fsl-gianfar", - .id = 2, - .dev.platform_data = &mpc85xx_tsec2_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = MPC85xx_ENET2_OFFSET, - .end = MPC85xx_ENET2_OFFSET + - MPC85xx_ENET2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC85xx_IRQ_TSEC2_TX, - .end = MPC85xx_IRQ_TSEC2_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC85xx_IRQ_TSEC2_RX, - .end = MPC85xx_IRQ_TSEC2_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC85xx_IRQ_TSEC2_ERROR, - .end = MPC85xx_IRQ_TSEC2_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_FEC] = { - .name = "fsl-gianfar", - .id = 3, - .dev.platform_data = &mpc85xx_fec_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_ENET3_OFFSET, - .end = MPC85xx_ENET3_OFFSET + - MPC85xx_ENET3_SIZE - 1, - .flags = IORESOURCE_MEM, - - }, - { - .start = MPC85xx_IRQ_FEC, - .end = MPC85xx_IRQ_FEC, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_IIC1] = { - .name = "fsl-i2c", - .id = 1, - .dev.platform_data = &mpc85xx_fsl_i2c_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_IIC1_OFFSET, - .end = MPC85xx_IIC1_OFFSET + - MPC85xx_IIC1_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_IIC1, - .end = MPC85xx_IRQ_IIC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_DMA0] = { - .name = "fsl-dma", - .id = 0, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_DMA0_OFFSET, - .end = MPC85xx_DMA0_OFFSET + - MPC85xx_DMA0_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_DMA0, - .end = MPC85xx_IRQ_DMA0, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_DMA1] = { - .name = "fsl-dma", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_DMA1_OFFSET, - .end = MPC85xx_DMA1_OFFSET + - MPC85xx_DMA1_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_DMA1, - .end = MPC85xx_IRQ_DMA1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_DMA2] = { - .name = "fsl-dma", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_DMA2_OFFSET, - .end = MPC85xx_DMA2_OFFSET + - MPC85xx_DMA2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_DMA2, - .end = MPC85xx_IRQ_DMA2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_DMA3] = { - .name = "fsl-dma", - .id = 3, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_DMA3_OFFSET, - .end = MPC85xx_DMA3_OFFSET + - MPC85xx_DMA3_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_DMA3, - .end = MPC85xx_IRQ_DMA3, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_DUART] = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = serial_platform_data, - }, - [MPC85xx_PERFMON] = { - .name = "fsl-perfmon", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_PERFMON_OFFSET, - .end = MPC85xx_PERFMON_OFFSET + - MPC85xx_PERFMON_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_PERFMON, - .end = MPC85xx_IRQ_PERFMON, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_SEC2] = { - .name = "fsl-sec2", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = MPC85xx_SEC2_OFFSET, - .end = MPC85xx_SEC2_OFFSET + - MPC85xx_SEC2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_SEC2, - .end = MPC85xx_IRQ_SEC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_FCC1] = { - .name = "fsl-cpm-fcc", - .id = 1, - .num_resources = 4, - .dev.platform_data = &mpc85xx_fcc1_pdata, - .resource = (struct resource[]) { - { - .name = "fcc_regs", - .start = 0x91300, - .end = 0x9131F, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_regs_c", - .start = 0x91380, - .end = 0x9139F, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_pram", - .start = 0x88400, - .end = 0x884ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_FCC1, - .end = SIU_INT_FCC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_FCC2] = { - .name = "fsl-cpm-fcc", - .id = 2, - .num_resources = 4, - .dev.platform_data = &mpc85xx_fcc2_pdata, - .resource = (struct resource[]) { - { - .name = "fcc_regs", - .start = 0x91320, - .end = 0x9133F, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_regs_c", - .start = 0x913A0, - .end = 0x913CF, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_pram", - .start = 0x88500, - .end = 0x885ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_FCC2, - .end = SIU_INT_FCC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_FCC3] = { - .name = "fsl-cpm-fcc", - .id = 3, - .num_resources = 4, - .dev.platform_data = &mpc85xx_fcc3_pdata, - .resource = (struct resource[]) { - { - .name = "fcc_regs", - .start = 0x91340, - .end = 0x9135F, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_regs_c", - .start = 0x913D0, - .end = 0x913FF, - .flags = IORESOURCE_MEM, - }, - { - .name = "fcc_pram", - .start = 0x88600, - .end = 0x886ff, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_FCC3, - .end = SIU_INT_FCC3, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_I2C] = { - .name = "fsl-cpm-i2c", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91860, - .end = 0x918BF, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_I2C, - .end = SIU_INT_I2C, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_SCC1] = { - .name = "fsl-cpm-scc", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91A00, - .end = 0x91A1F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC1, - .end = SIU_INT_SCC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_SCC2] = { - .name = "fsl-cpm-scc", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91A20, - .end = 0x91A3F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC2, - .end = SIU_INT_SCC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_SCC3] = { - .name = "fsl-cpm-scc", - .id = 3, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91A40, - .end = 0x91A5F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC3, - .end = SIU_INT_SCC3, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_SCC4] = { - .name = "fsl-cpm-scc", - .id = 4, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91A60, - .end = 0x91A7F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SCC4, - .end = SIU_INT_SCC4, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_SPI] = { - .name = "fsl-cpm-spi", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91AA0, - .end = 0x91AFF, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SPI, - .end = SIU_INT_SPI, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_MCC1] = { - .name = "fsl-cpm-mcc", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91B30, - .end = 0x91B3F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_MCC1, - .end = SIU_INT_MCC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_MCC2] = { - .name = "fsl-cpm-mcc", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91B50, - .end = 0x91B5F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_MCC2, - .end = SIU_INT_MCC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_SMC1] = { - .name = "fsl-cpm-smc", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91A80, - .end = 0x91A8F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SMC1, - .end = SIU_INT_SMC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_SMC2] = { - .name = "fsl-cpm-smc", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91A90, - .end = 0x91A9F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_SMC2, - .end = SIU_INT_SMC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_CPM_USB] = { - .name = "fsl-cpm-usb", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x91B60, - .end = 0x91B7F, - .flags = IORESOURCE_MEM, - }, - { - .start = SIU_INT_USB, - .end = SIU_INT_USB, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_eTSEC1] = { - .name = "fsl-gianfar", - .id = 1, - .dev.platform_data = &mpc85xx_etsec1_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = MPC85xx_ENET1_OFFSET, - .end = MPC85xx_ENET1_OFFSET + - MPC85xx_ENET1_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC85xx_IRQ_TSEC1_TX, - .end = MPC85xx_IRQ_TSEC1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC85xx_IRQ_TSEC1_RX, - .end = MPC85xx_IRQ_TSEC1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC85xx_IRQ_TSEC1_ERROR, - .end = MPC85xx_IRQ_TSEC1_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_eTSEC2] = { - .name = "fsl-gianfar", - .id = 2, - .dev.platform_data = &mpc85xx_etsec2_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = MPC85xx_ENET2_OFFSET, - .end = MPC85xx_ENET2_OFFSET + - MPC85xx_ENET2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC85xx_IRQ_TSEC2_TX, - .end = MPC85xx_IRQ_TSEC2_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC85xx_IRQ_TSEC2_RX, - .end = MPC85xx_IRQ_TSEC2_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC85xx_IRQ_TSEC2_ERROR, - .end = MPC85xx_IRQ_TSEC2_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_eTSEC3] = { - .name = "fsl-gianfar", - .id = 3, - .dev.platform_data = &mpc85xx_etsec3_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = MPC85xx_ENET3_OFFSET, - .end = MPC85xx_ENET3_OFFSET + - MPC85xx_ENET3_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC85xx_IRQ_TSEC3_TX, - .end = MPC85xx_IRQ_TSEC3_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC85xx_IRQ_TSEC3_RX, - .end = MPC85xx_IRQ_TSEC3_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC85xx_IRQ_TSEC3_ERROR, - .end = MPC85xx_IRQ_TSEC3_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_eTSEC4] = { - .name = "fsl-gianfar", - .id = 4, - .dev.platform_data = &mpc85xx_etsec4_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = 0x27000, - .end = 0x27fff, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC85xx_IRQ_TSEC4_TX, - .end = MPC85xx_IRQ_TSEC4_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC85xx_IRQ_TSEC4_RX, - .end = MPC85xx_IRQ_TSEC4_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC85xx_IRQ_TSEC4_ERROR, - .end = MPC85xx_IRQ_TSEC4_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_IIC2] = { - .name = "fsl-i2c", - .id = 2, - .dev.platform_data = &mpc85xx_fsl_i2c2_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x03100, - .end = 0x031ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC85xx_IRQ_IIC1, - .end = MPC85xx_IRQ_IIC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC85xx_MDIO] = { - .name = "fsl-gianfar_mdio", - .id = 0, - .dev.platform_data = &mpc85xx_mdio_pdata, - .num_resources = 1, - .resource = (struct resource[]) { - { - .start = 0x24520, - .end = 0x2453f, - .flags = IORESOURCE_MEM, - }, - }, - }, -}; - -static int __init mach_mpc85xx_fixup(struct platform_device *pdev) -{ - ppc_sys_fixup_mem_resource(pdev, CCSRBAR); - return 0; -} - -static int __init mach_mpc85xx_init(void) -{ - ppc_sys_device_fixup = mach_mpc85xx_fixup; - return 0; -} - -postcore_initcall(mach_mpc85xx_init); diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c deleted file mode 100644 index d96a93dbcb5a..000000000000 --- a/arch/ppc/syslib/mpc85xx_sys.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * MPC85xx System descriptions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/device.h> -#include <asm/ppc_sys.h> - -struct ppc_sys_spec *cur_ppc_sys_spec; -struct ppc_sys_spec ppc_sys_specs[] = { - { - .ppc_sys_name = "8540", - .mask = 0xFFFF0000, - .value = 0x80300000, - .num_devices = 11, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8560", - .mask = 0xFFFF0000, - .value = 0x80700000, - .num_devices = 20, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, - MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1, - MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4, - MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3, - MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2, MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8541", - .mask = 0xFFFF0000, - .value = 0x80720000, - .num_devices = 14, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, - MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, - MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8541E", - .mask = 0xFFFF0000, - .value = 0x807A0000, - .num_devices = 15, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, - MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, - MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8555", - .mask = 0xFFFF0000, - .value = 0x80710000, - .num_devices = 20, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, - MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1, - MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, - MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, - MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2, - MPC85xx_CPM_USB, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8555E", - .mask = 0xFFFF0000, - .value = 0x80790000, - .num_devices = 21, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, - MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1, - MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, - MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, - MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2, - MPC85xx_CPM_USB, - MPC85xx_MDIO, - }, - }, - /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */ - { - .ppc_sys_name = "8548E", - .mask = 0xFFFF00F0, - .value = 0x80390010, - .num_devices = 14, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, - MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8548", - .mask = 0xFFFF00F0, - .value = 0x80310010, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, - MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8547E", - .mask = 0xFFFF00F0, - .value = 0x80390010, - .num_devices = 14, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, - MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8547", - .mask = 0xFFFF00F0, - .value = 0x80310010, - .num_devices = 13, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, - MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8545E", - .mask = 0xFFFF00F0, - .value = 0x80390010, - .num_devices = 12, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, - MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8545", - .mask = 0xFFFF00F0, - .value = 0x80310010, - .num_devices = 11, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, - MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8543E", - .mask = 0xFFFF00F0, - .value = 0x803A0010, - .num_devices = 12, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, - MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, - MPC85xx_MDIO, - }, - }, - { - .ppc_sys_name = "8543", - .mask = 0xFFFF00F0, - .value = 0x80320010, - .num_devices = 11, - .device_list = (enum ppc_sys_devices[]) - { - MPC85xx_eTSEC1, MPC85xx_eTSEC2, - MPC85xx_IIC1, MPC85xx_IIC2, - MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, - MPC85xx_PERFMON, MPC85xx_DUART, - MPC85xx_MDIO, - }, - }, - { /* default match */ - .ppc_sys_name = "", - .mask = 0x00000000, - .value = 0x00000000, - }, -}; diff --git a/arch/ppc/syslib/mpc8xx_devices.c b/arch/ppc/syslib/mpc8xx_devices.c index c05ac87ece4c..80804eee5795 100644 --- a/arch/ppc/syslib/mpc8xx_devices.c +++ b/arch/ppc/syslib/mpc8xx_devices.c @@ -16,7 +16,7 @@ #include <linux/device.h> #include <linux/serial_8250.h> #include <linux/mii.h> -#include <asm/commproc.h> +#include <asm/cpm1.h> #include <asm/mpc8xx.h> #include <asm/irq.h> #include <asm/ppc_sys.h> diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c index 4b7a3338e122..2dd2dc5cd404 100644 --- a/arch/ppc/syslib/mv64360_pic.c +++ b/arch/ppc/syslib/mv64360_pic.c @@ -36,7 +36,6 @@ #include <linux/init.h> #include <linux/sched.h> #include <linux/signal.h> -#include <linux/stddef.h> #include <linux/delay.h> #include <linux/irq.h> #include <linux/interrupt.h> diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c index 2744b8a6f66a..90fe904d3614 100644 --- a/arch/ppc/syslib/mv64x60.c +++ b/arch/ppc/syslib/mv64x60.c @@ -411,7 +411,6 @@ static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = { .freq_m = 8, .freq_n = 3, .timeout = 1000, /* Default timeout of 1 second */ - .retries = 1, }; static struct resource mv64xxx_i2c_resources[] = { diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c index 3f5be2c5ce99..ac80370ed2f7 100644 --- a/arch/ppc/syslib/ocp.c +++ b/arch/ppc/syslib/ocp.c @@ -20,7 +20,7 @@ * of peripherals are found on embedded SoC (System On a Chip) * processors or highly integrated system controllers that have * a host bridge and many peripherals. Common examples where - * this is already used include the PPC4xx, PPC85xx, MPC52xx, + * this is already used include the PPC4xx, MPC52xx, * and MV64xxx parts. * * This subsystem creates a standard OCP bus type within the @@ -376,7 +376,7 @@ ocp_remove_one_device(unsigned int vendor, unsigned int function, int index) down_write(&ocp_devices_sem); dev = __ocp_find_device(vendor, function, index); - list_del((struct list_head *)dev); + list_del(&dev->link); up_write(&ocp_devices_sem); DBG(("ocp: ocp_remove_one_device(vendor: %x, function: %x, index: %d)... done.\n", vendor, function, index)); diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c index 18ec94733293..67dffe27b5c3 100644 --- a/arch/ppc/syslib/open_pic.c +++ b/arch/ppc/syslib/open_pic.c @@ -24,7 +24,7 @@ #include "open_pic_defs.h" -#if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx) +#if defined(CONFIG_PRPMC800) #define OPENPIC_BIG_ENDIAN #endif @@ -1043,7 +1043,7 @@ int openpic_resume(struct sys_device *sysdev) #endif /* CONFIG_PM */ static struct sysdev_class openpic_sysclass = { - set_kset_name("openpic"), + .name = "openpic", }; static struct sys_device device_openpic = { diff --git a/arch/ppc/syslib/open_pic2.c b/arch/ppc/syslib/open_pic2.c index d585207f9f77..449075a04798 100644 --- a/arch/ppc/syslib/open_pic2.c +++ b/arch/ppc/syslib/open_pic2.c @@ -666,7 +666,7 @@ int openpic2_resume(struct sys_device *sysdev) /* HACK ALERT */ static struct sysdev_class openpic2_sysclass = { - set_kset_name("openpic2"), + .name = "openpic2", }; static struct sys_device device_openpic2 = { diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h deleted file mode 100644 index ec691640f6be..000000000000 --- a/arch/ppc/syslib/ppc83xx_pci.h +++ /dev/null @@ -1,151 +0,0 @@ -/* Created by Tony Li <tony.li@freescale.com> - * Copyright (c) 2005 freescale semiconductor - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __PPC_SYSLIB_PPC83XX_PCI_H -#define __PPC_SYSLIB_PPC83XX_PCI_H - -typedef struct immr_clk { - u32 spmr; /* system PLL mode Register */ - u32 occr; /* output clock control Register */ - u32 sccr; /* system clock control Register */ - u8 res0[0xF4]; -} immr_clk_t; - -/* - * Sequencer - */ -typedef struct immr_ios { - u32 potar0; - u8 res0[4]; - u32 pobar0; - u8 res1[4]; - u32 pocmr0; - u8 res2[4]; - u32 potar1; - u8 res3[4]; - u32 pobar1; - u8 res4[4]; - u32 pocmr1; - u8 res5[4]; - u32 potar2; - u8 res6[4]; - u32 pobar2; - u8 res7[4]; - u32 pocmr2; - u8 res8[4]; - u32 potar3; - u8 res9[4]; - u32 pobar3; - u8 res10[4]; - u32 pocmr3; - u8 res11[4]; - u32 potar4; - u8 res12[4]; - u32 pobar4; - u8 res13[4]; - u32 pocmr4; - u8 res14[4]; - u32 potar5; - u8 res15[4]; - u32 pobar5; - u8 res16[4]; - u32 pocmr5; - u8 res17[4]; - u8 res18[0x60]; - u32 pmcr; - u8 res19[4]; - u32 dtcr; - u8 res20[4]; -} immr_ios_t; -#define POTAR_TA_MASK 0x000fffff -#define POBAR_BA_MASK 0x000fffff -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ -#define POCMR_SE 0x20000000 /* streaming enable */ -#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ -#define POCMR_CM_MASK 0x000fffff - -/* - * PCI Controller Control and Status Registers - */ -typedef struct immr_pcictrl { - u32 esr; - u32 ecdr; - u32 eer; - u32 eatcr; - u32 eacr; - u32 eeacr; - u32 edlcr; - u32 edhcr; - u32 gcr; - u32 ecr; - u32 gsr; - u8 res0[12]; - u32 pitar2; - u8 res1[4]; - u32 pibar2; - u32 piebar2; - u32 piwar2; - u8 res2[4]; - u32 pitar1; - u8 res3[4]; - u32 pibar1; - u32 piebar1; - u32 piwar1; - u8 res4[4]; - u32 pitar0; - u8 res5[4]; - u32 pibar0; - u8 res6[4]; - u32 piwar0; - u8 res7[132]; -} immr_pcictrl_t; -#define PITAR_TA_MASK 0x000fffff -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 -#define PIWAR_IWS_MASK 0x0000003F -#define PIWAR_IWS_4K 0x0000000B -#define PIWAR_IWS_8K 0x0000000C -#define PIWAR_IWS_16K 0x0000000D -#define PIWAR_IWS_32K 0x0000000E -#define PIWAR_IWS_64K 0x0000000F -#define PIWAR_IWS_128K 0x00000010 -#define PIWAR_IWS_256K 0x00000011 -#define PIWAR_IWS_512K 0x00000012 -#define PIWAR_IWS_1M 0x00000013 -#define PIWAR_IWS_2M 0x00000014 -#define PIWAR_IWS_4M 0x00000015 -#define PIWAR_IWS_8M 0x00000016 -#define PIWAR_IWS_16M 0x00000017 -#define PIWAR_IWS_32M 0x00000018 -#define PIWAR_IWS_64M 0x00000019 -#define PIWAR_IWS_128M 0x0000001A -#define PIWAR_IWS_256M 0x0000001B -#define PIWAR_IWS_512M 0x0000001C -#define PIWAR_IWS_1G 0x0000001D -#define PIWAR_IWS_2G 0x0000001E - -#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */ diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c deleted file mode 100644 index ec466db52114..000000000000 --- a/arch/ppc/syslib/ppc83xx_setup.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * MPC83XX common board code - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Added PCI support -- Tony Li <tony.li@freescale.com> - */ - -#include <linux/types.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/serial.h> -#include <linux/tty.h> /* for linux/serial_core.h */ -#include <linux/serial_core.h> -#include <linux/serial_8250.h> - -#include <asm/time.h> -#include <asm/mpc83xx.h> -#include <asm/mmu.h> -#include <asm/ppc_sys.h> -#include <asm/kgdb.h> -#include <asm/delay.h> -#include <asm/machdep.h> - -#include <syslib/ppc83xx_setup.h> -#if defined(CONFIG_PCI) -#include <asm/delay.h> -#include <syslib/ppc83xx_pci.h> -#endif - -phys_addr_t immrbar; - -/* Return the amount of memory */ -unsigned long __init -mpc83xx_find_end_of_memory(void) -{ - bd_t *binfo; - - binfo = (bd_t *) __res; - - return binfo->bi_memsize; -} - -long __init -mpc83xx_time_init(void) -{ -#define SPCR_OFFS 0x00000110 -#define SPCR_TBEN 0x00400000 - - bd_t *binfo = (bd_t *)__res; - u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4); - - *spcr |= SPCR_TBEN; - - iounmap(spcr); - - return 0; -} - -/* The decrementer counts at the system (internal) clock freq divided by 4 */ -void __init -mpc83xx_calibrate_decr(void) -{ - bd_t *binfo = (bd_t *) __res; - unsigned int freq, divisor; - - freq = binfo->bi_busfreq; - divisor = 4; - tb_ticks_per_jiffy = freq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); -} - -#ifdef CONFIG_SERIAL_8250 -void __init -mpc83xx_early_serial_map(void) -{ -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - struct uart_port serial_req; -#endif - struct plat_serial8250_port *pdata; - bd_t *binfo = (bd_t *) __res; - pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART); - - /* Setup serial port access */ - pdata[0].uartclk = binfo->bi_busfreq; - pdata[0].mapbase += binfo->bi_immr_base; - pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - memset(&serial_req, 0, sizeof (serial_req)); - serial_req.iotype = UPIO_MEM; - serial_req.mapbase = pdata[0].mapbase; - serial_req.membase = pdata[0].membase; - serial_req.regshift = 0; - - gen550_init(0, &serial_req); -#endif - - pdata[1].uartclk = binfo->bi_busfreq; - pdata[1].mapbase += binfo->bi_immr_base; - pdata[1].membase = ioremap(pdata[1].mapbase, 0x100); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Assume gen550_init() doesn't modify serial_req */ - serial_req.mapbase = pdata[1].mapbase; - serial_req.membase = pdata[1].membase; - - gen550_init(1, &serial_req); -#endif -} -#endif - -void -mpc83xx_restart(char *cmd) -{ - volatile unsigned char __iomem *reg; - unsigned char tmp; - - reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE); - - local_irq_disable(); - - /* - * Unlock the BCSR bits so a PRST will update the contents. - * Otherwise the reset asserts but doesn't clear. - */ - tmp = in_8(reg + BCSR_MISC_REG3_OFF); - tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */ - out_8(reg + BCSR_MISC_REG3_OFF, tmp); - - /* - * Trigger a reset via a low->high transition of the - * PORESET bit. - */ - tmp = in_8(reg + BCSR_MISC_REG2_OFF); - tmp &= ~BCSR_MISC_REG2_PORESET; - out_8(reg + BCSR_MISC_REG2_OFF, tmp); - - udelay(1); - - tmp |= BCSR_MISC_REG2_PORESET; - out_8(reg + BCSR_MISC_REG2_OFF, tmp); - - for(;;); -} - -void -mpc83xx_power_off(void) -{ - local_irq_disable(); - for(;;); -} - -void -mpc83xx_halt(void) -{ - local_irq_disable(); - for(;;); -} - -#if defined(CONFIG_PCI) -void __init -mpc83xx_setup_pci1(struct pci_controller *hose) -{ - u16 reg16; - volatile immr_pcictrl_t * pci_ctrl; - volatile immr_ios_t * ios; - bd_t *binfo = (bd_t *) __res; - - pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t)); - ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); - - /* - * Configure PCI Outbound Translation Windows - */ - ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK; - ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK; - ios->pocmr0 = POCMR_EN | - (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM - - MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK); - - /* mapped to PCI1 IO space */ - ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK; - ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK; - ios->pocmr1 = POCMR_EN | POCMR_IO | - (((0xffffffff - (MPC83xx_PCI1_UPPER_IO - - MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl->pitar1 = 0x0; - pci_ctrl->pibar1 = 0x0; - pci_ctrl->piebar1 = 0x0; - pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; - - /* - * Release PCI RST signal - */ - pci_ctrl->gcr = 0; - udelay(2000); - pci_ctrl->gcr = 1; - udelay(2000); - - reg16 = 0xff; - early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); - early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); - - iounmap(pci_ctrl); - iounmap(ios); -} - -void __init -mpc83xx_setup_pci2(struct pci_controller *hose) -{ - u16 reg16; - volatile immr_pcictrl_t * pci_ctrl; - volatile immr_ios_t * ios; - bd_t *binfo = (bd_t *) __res; - - pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t)); - ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); - - /* - * Configure PCI Outbound Translation Windows - */ - ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK; - ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK; - ios->pocmr3 = POCMR_EN | POCMR_DST | - (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM - - MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK); - - /* mapped to PCI2 IO space */ - ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK; - ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK; - ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO | - (((0xffffffff - (MPC83xx_PCI2_UPPER_IO - - MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl->pitar1 = 0x0; - pci_ctrl->pibar1 = 0x0; - pci_ctrl->piebar1 = 0x0; - pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; - - /* - * Release PCI RST signal - */ - pci_ctrl->gcr = 0; - udelay(2000); - pci_ctrl->gcr = 1; - udelay(2000); - - reg16 = 0xff; - early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); - early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); - - iounmap(pci_ctrl); - iounmap(ios); -} - -/* - * PCI buses can be enabled only if SYS board combinates with PIB - * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses - * and 3 PCI slots, so people must configure the routes between them before - * enable PCI bus. This routes are under the control of PCA9555PW device which - * can be accessed via I2C bus 2 and are configured by firmware. Refer to - * Freescale to get more information about firmware configuration. - */ - -extern int mpc83xx_exclude_device(u_char bus, u_char devfn); -extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, - unsigned char pin); -void __init -mpc83xx_setup_hose(void) -{ - u32 val32; - volatile immr_clk_t * clk; - struct pci_controller * hose1; -#ifdef CONFIG_MPC83xx_PCI2 - struct pci_controller * hose2; -#endif - bd_t * binfo = (bd_t *)__res; - - clk = ioremap(binfo->bi_immr_base + 0xA00, - sizeof(immr_clk_t)); - - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); - clk->occr = 0xff000000; - udelay(2000); - - iounmap(clk); - - hose1 = pcibios_alloc_controller(); - if(!hose1) - return; - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = mpc83xx_map_irq; - - hose1->bus_offset = 0; - hose1->first_busno = 0; - hose1->last_busno = 0xff; - - setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, - binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); - hose1->set_cfg_type = 1; - - mpc83xx_setup_pci1(hose1); - - hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; - hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; - hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; - - hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; - hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; - hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; -#ifdef CONFIG_MPC83xx_PCI2 - isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, - MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); -#else - isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, - MPC83xx_PCI1_IO_SIZE); -#endif /* CONFIG_MPC83xx_PCI2 */ - hose1->io_base_virt = (void *)isa_io_base; - /* setup resources */ - pci_init_resource(&hose1->io_resource, - MPC83xx_PCI1_LOWER_IO, - MPC83xx_PCI1_UPPER_IO, - IORESOURCE_IO, "PCI host bridge 1"); - pci_init_resource(&hose1->mem_resources[0], - MPC83xx_PCI1_LOWER_MEM, - MPC83xx_PCI1_UPPER_MEM, - IORESOURCE_MEM, "PCI host bridge 1"); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device; - hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); - -#ifdef CONFIG_MPC83xx_PCI2 - hose2 = pcibios_alloc_controller(); - if(!hose2) - return; - - hose2->bus_offset = hose1->last_busno + 1; - hose2->first_busno = hose1->last_busno + 1; - hose2->last_busno = 0xff; - setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, - binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); - hose2->set_cfg_type = 1; - - mpc83xx_setup_pci2(hose2); - - hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; - hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; - hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; - - hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; - hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; - hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; - hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); - /* setup resources */ - pci_init_resource(&hose2->io_resource, - MPC83xx_PCI2_LOWER_IO, - MPC83xx_PCI2_UPPER_IO, - IORESOURCE_IO, "PCI host bridge 2"); - pci_init_resource(&hose2->mem_resources[0], - MPC83xx_PCI2_LOWER_MEM, - MPC83xx_PCI2_UPPER_MEM, - IORESOURCE_MEM, "PCI host bridge 2"); - - hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); -#endif /* CONFIG_MPC83xx_PCI2 */ -} -#endif /*CONFIG_PCI*/ diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h deleted file mode 100644 index b918a2d245ea..000000000000 --- a/arch/ppc/syslib/ppc83xx_setup.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * MPC83XX common board definitions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H -#define __PPC_SYSLIB_PPC83XX_SETUP_H - -#include <linux/init.h> - -extern unsigned long mpc83xx_find_end_of_memory(void) __init; -extern long mpc83xx_time_init(void) __init; -extern void mpc83xx_calibrate_decr(void) __init; -extern void mpc83xx_early_serial_map(void) __init; -extern void mpc83xx_restart(char *cmd); -extern void mpc83xx_power_off(void); -extern void mpc83xx_halt(void); -extern void mpc83xx_setup_hose(void) __init; - -/* PCI config */ -#define PCI1_CFG_ADDR_OFFSET (0x8300) -#define PCI1_CFG_DATA_OFFSET (0x8304) - -#define PCI2_CFG_ADDR_OFFSET (0x8380) -#define PCI2_CFG_DATA_OFFSET (0x8384) - -/* Serial Config */ -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 2 -#endif - -#ifndef BASE_BAUD -#define BASE_BAUD 115200 -#endif - -#endif /* __PPC_SYSLIB_PPC83XX_SETUP_H */ diff --git a/arch/ppc/syslib/ppc85xx_common.c b/arch/ppc/syslib/ppc85xx_common.c deleted file mode 100644 index e5ac699e7316..000000000000 --- a/arch/ppc/syslib/ppc85xx_common.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * MPC85xx support routines - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/types.h> -#include <linux/module.h> -#include <linux/init.h> - -#include <asm/mpc85xx.h> -#include <asm/mmu.h> - -/* ************************************************************************ */ -/* Return the value of CCSRBAR for the current board */ - -phys_addr_t -get_ccsrbar(void) -{ - return BOARD_CCSRBAR; -} - -EXPORT_SYMBOL(get_ccsrbar); - -/* For now this is a pass through */ -phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size) -{ - return addr; -}; -EXPORT_SYMBOL(fixup_bigphys_addr); - diff --git a/arch/ppc/syslib/ppc85xx_common.h b/arch/ppc/syslib/ppc85xx_common.h deleted file mode 100644 index 4fc405425113..000000000000 --- a/arch/ppc/syslib/ppc85xx_common.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * MPC85xx support routines - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PPC_SYSLIB_PPC85XX_COMMON_H -#define __PPC_SYSLIB_PPC85XX_COMMON_H - -#include <linux/init.h> - -/* Provide access to ccsrbar for any modules, etc */ -phys_addr_t get_ccsrbar(void); - -#endif /* __PPC_SYSLIB_PPC85XX_COMMON_H */ diff --git a/arch/ppc/syslib/ppc85xx_rio.c b/arch/ppc/syslib/ppc85xx_rio.c deleted file mode 100644 index af2425e4655f..000000000000 --- a/arch/ppc/syslib/ppc85xx_rio.c +++ /dev/null @@ -1,932 +0,0 @@ -/* - * MPC85xx RapidIO support - * - * Copyright 2005 MontaVista Software, Inc. - * Matt Porter <mporter@kernel.crashing.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/dma-mapping.h> -#include <linux/interrupt.h> -#include <linux/rio.h> -#include <linux/rio_drv.h> - -#include <asm/io.h> - -#define RIO_REGS_BASE (CCSRBAR + 0xc0000) -#define RIO_ATMU_REGS_OFFSET 0x10c00 -#define RIO_MSG_REGS_OFFSET 0x11000 -#define RIO_MAINT_WIN_SIZE 0x400000 -#define RIO_DBELL_WIN_SIZE 0x1000 - -#define RIO_MSG_OMR_MUI 0x00000002 -#define RIO_MSG_OSR_TE 0x00000080 -#define RIO_MSG_OSR_QOI 0x00000020 -#define RIO_MSG_OSR_QFI 0x00000010 -#define RIO_MSG_OSR_MUB 0x00000004 -#define RIO_MSG_OSR_EOMI 0x00000002 -#define RIO_MSG_OSR_QEI 0x00000001 - -#define RIO_MSG_IMR_MI 0x00000002 -#define RIO_MSG_ISR_TE 0x00000080 -#define RIO_MSG_ISR_QFI 0x00000010 -#define RIO_MSG_ISR_DIQI 0x00000001 - -#define RIO_MSG_DESC_SIZE 32 -#define RIO_MSG_BUFFER_SIZE 4096 -#define RIO_MIN_TX_RING_SIZE 2 -#define RIO_MAX_TX_RING_SIZE 2048 -#define RIO_MIN_RX_RING_SIZE 2 -#define RIO_MAX_RX_RING_SIZE 2048 - -#define DOORBELL_DMR_DI 0x00000002 -#define DOORBELL_DSR_TE 0x00000080 -#define DOORBELL_DSR_QFI 0x00000010 -#define DOORBELL_DSR_DIQI 0x00000001 -#define DOORBELL_TID_OFFSET 0x03 -#define DOORBELL_SID_OFFSET 0x05 -#define DOORBELL_INFO_OFFSET 0x06 - -#define DOORBELL_MESSAGE_SIZE 0x08 -#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET)) -#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET)) -#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) - -struct rio_atmu_regs { - u32 rowtar; - u32 pad1; - u32 rowbar; - u32 pad2; - u32 rowar; - u32 pad3[3]; -}; - -struct rio_msg_regs { - u32 omr; - u32 osr; - u32 pad1; - u32 odqdpar; - u32 pad2; - u32 osar; - u32 odpr; - u32 odatr; - u32 odcr; - u32 pad3; - u32 odqepar; - u32 pad4[13]; - u32 imr; - u32 isr; - u32 pad5; - u32 ifqdpar; - u32 pad6; - u32 ifqepar; - u32 pad7[250]; - u32 dmr; - u32 dsr; - u32 pad8; - u32 dqdpar; - u32 pad9; - u32 dqepar; - u32 pad10[26]; - u32 pwmr; - u32 pwsr; - u32 pad11; - u32 pwqbar; -}; - -struct rio_tx_desc { - u32 res1; - u32 saddr; - u32 dport; - u32 dattr; - u32 res2; - u32 res3; - u32 dwcnt; - u32 res4; -}; - -static u32 regs_win; -static struct rio_atmu_regs *atmu_regs; -static struct rio_atmu_regs *maint_atmu_regs; -static struct rio_atmu_regs *dbell_atmu_regs; -static u32 dbell_win; -static u32 maint_win; -static struct rio_msg_regs *msg_regs; - -static struct rio_dbell_ring { - void *virt; - dma_addr_t phys; -} dbell_ring; - -static struct rio_msg_tx_ring { - void *virt; - dma_addr_t phys; - void *virt_buffer[RIO_MAX_TX_RING_SIZE]; - dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; - int tx_slot; - int size; - void *dev_id; -} msg_tx_ring; - -static struct rio_msg_rx_ring { - void *virt; - dma_addr_t phys; - void *virt_buffer[RIO_MAX_RX_RING_SIZE]; - int rx_slot; - int size; - void *dev_id; -} msg_rx_ring; - -/** - * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message - * @index: ID of RapidIO interface - * @destid: Destination ID of target device - * @data: 16-bit info field of RapidIO doorbell message - * - * Sends a MPC85xx doorbell message. Returns %0 on success or - * %-EINVAL on failure. - */ -static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data) -{ - pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n", - index, destid, data); - out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22); - out_be16((void *)(dbell_win), data); - - return 0; -} - -/** - * mpc85xx_local_config_read - Generate a MPC85xx local config space read - * @index: ID of RapdiIO interface - * @offset: Offset into configuration space - * @len: Length (in bytes) of the maintenance transaction - * @data: Value to be read into - * - * Generates a MPC85xx local configuration space read. Returns %0 on - * success or %-EINVAL on failure. - */ -static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data) -{ - pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index, - offset); - *data = in_be32((void *)(regs_win + offset)); - - return 0; -} - -/** - * mpc85xx_local_config_write - Generate a MPC85xx local config space write - * @index: ID of RapdiIO interface - * @offset: Offset into configuration space - * @len: Length (in bytes) of the maintenance transaction - * @data: Value to be written - * - * Generates a MPC85xx local configuration space write. Returns %0 on - * success or %-EINVAL on failure. - */ -static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data) -{ - pr_debug - ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n", - index, offset, data); - out_be32((void *)(regs_win + offset), data); - - return 0; -} - -/** - * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction - * @index: ID of RapdiIO interface - * @destid: Destination ID of transaction - * @hopcount: Number of hops to target device - * @offset: Offset into configuration space - * @len: Length (in bytes) of the maintenance transaction - * @val: Location to be read into - * - * Generates a MPC85xx read maintenance transaction. Returns %0 on - * success or %-EINVAL on failure. - */ -static int -mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len, - u32 * val) -{ - u8 *data; - - pr_debug - ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", - index, destid, hopcount, offset, len); - out_be32((void *)&maint_atmu_regs->rowtar, - (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); - - data = (u8 *) maint_win + offset; - switch (len) { - case 1: - *val = in_8((u8 *) data); - break; - case 2: - *val = in_be16((u16 *) data); - break; - default: - *val = in_be32((u32 *) data); - break; - } - - return 0; -} - -/** - * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction - * @index: ID of RapdiIO interface - * @destid: Destination ID of transaction - * @hopcount: Number of hops to target device - * @offset: Offset into configuration space - * @len: Length (in bytes) of the maintenance transaction - * @val: Value to be written - * - * Generates an MPC85xx write maintenance transaction. Returns %0 on - * success or %-EINVAL on failure. - */ -static int -mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset, - int len, u32 val) -{ - u8 *data; - pr_debug - ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", - index, destid, hopcount, offset, len, val); - out_be32((void *)&maint_atmu_regs->rowtar, - (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); - - data = (u8 *) maint_win + offset; - switch (len) { - case 1: - out_8((u8 *) data, val); - break; - case 2: - out_be16((u16 *) data, val); - break; - default: - out_be32((u32 *) data, val); - break; - } - - return 0; -} - -/** - * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue - * @mport: Master port with outbound message queue - * @rdev: Target of outbound message - * @mbox: Outbound mailbox - * @buffer: Message to add to outbound queue - * @len: Length of message - * - * Adds the @buffer message to the MPC85xx outbound message queue. Returns - * %0 on success or %-EINVAL on failure. - */ -int -rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, - void *buffer, size_t len) -{ - u32 omr; - struct rio_tx_desc *desc = - (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot; - int ret = 0; - - pr_debug - ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", - rdev->destid, mbox, (int)buffer, len); - - if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { - ret = -EINVAL; - goto out; - } - - /* Copy and clear rest of buffer */ - memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len); - if (len < (RIO_MAX_MSG_SIZE - 4)) - memset((void *)((u32) msg_tx_ring. - virt_buffer[msg_tx_ring.tx_slot] + len), 0, - RIO_MAX_MSG_SIZE - len); - - /* Set mbox field for message */ - desc->dport = mbox & 0x3; - - /* Enable EOMI interrupt, set priority, and set destid */ - desc->dattr = 0x28000000 | (rdev->destid << 2); - - /* Set transfer size aligned to next power of 2 (in double words) */ - desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); - - /* Set snooping and source buffer address */ - desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot]; - - /* Increment enqueue pointer */ - omr = in_be32((void *)&msg_regs->omr); - out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI); - - /* Go to next descriptor */ - if (++msg_tx_ring.tx_slot == msg_tx_ring.size) - msg_tx_ring.tx_slot = 0; - - out: - return ret; -} - -EXPORT_SYMBOL_GPL(rio_hw_add_outb_message); - -/** - * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler - * @irq: Linux interrupt number - * @dev_instance: Pointer to interrupt-specific data - * - * Handles outbound message interrupts. Executes a register outbound - * mailbox event handler and acks the interrupt occurrence. - */ -static irqreturn_t -mpc85xx_rio_tx_handler(int irq, void *dev_instance) -{ - int osr; - struct rio_mport *port = (struct rio_mport *)dev_instance; - - osr = in_be32((void *)&msg_regs->osr); - - if (osr & RIO_MSG_OSR_TE) { - pr_info("RIO: outbound message transmission error\n"); - out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE); - goto out; - } - - if (osr & RIO_MSG_OSR_QOI) { - pr_info("RIO: outbound message queue overflow\n"); - out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI); - goto out; - } - - if (osr & RIO_MSG_OSR_EOMI) { - u32 dqp = in_be32((void *)&msg_regs->odqdpar); - int slot = (dqp - msg_tx_ring.phys) >> 5; - port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot); - - /* Ack the end-of-message interrupt */ - out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI); - } - - out: - return IRQ_HANDLED; -} - -/** - * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox - * @mport: Master port implementing the outbound message unit - * @dev_id: Device specific pointer to pass on event - * @mbox: Mailbox to open - * @entries: Number of entries in the outbound mailbox ring - * - * Initializes buffer ring, request the outbound message interrupt, - * and enables the outbound message unit. Returns %0 on success and - * %-EINVAL or %-ENOMEM on failure. - */ -int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) -{ - int i, j, rc = 0; - - if ((entries < RIO_MIN_TX_RING_SIZE) || - (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { - rc = -EINVAL; - goto out; - } - - /* Initialize shadow copy ring */ - msg_tx_ring.dev_id = dev_id; - msg_tx_ring.size = entries; - - for (i = 0; i < msg_tx_ring.size; i++) { - if (! - (msg_tx_ring.virt_buffer[i] = - dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE, - &msg_tx_ring.phys_buffer[i], - GFP_KERNEL))) { - rc = -ENOMEM; - for (j = 0; j < msg_tx_ring.size; j++) - if (msg_tx_ring.virt_buffer[j]) - dma_free_coherent(NULL, - RIO_MSG_BUFFER_SIZE, - msg_tx_ring. - virt_buffer[j], - msg_tx_ring. - phys_buffer[j]); - goto out; - } - } - - /* Initialize outbound message descriptor ring */ - if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL, - msg_tx_ring.size * - RIO_MSG_DESC_SIZE, - &msg_tx_ring.phys, - GFP_KERNEL))) { - rc = -ENOMEM; - goto out_dma; - } - memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE); - msg_tx_ring.tx_slot = 0; - - /* Point dequeue/enqueue pointers at first entry in ring */ - out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys); - out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys); - - /* Configure for snooping */ - out_be32((void *)&msg_regs->osar, 0x00000004); - - /* Clear interrupt status */ - out_be32((void *)&msg_regs->osr, 0x000000b3); - - /* Hook up outbound message handler */ - if ((rc = - request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0, - "msg_tx", (void *)mport)) < 0) - goto out_irq; - - /* - * Configure outbound message unit - * Snooping - * Interrupts (all enabled, except QEIE) - * Chaining mode - * Disable - */ - out_be32((void *)&msg_regs->omr, 0x00100220); - - /* Set number of entries */ - out_be32((void *)&msg_regs->omr, - in_be32((void *)&msg_regs->omr) | - ((get_bitmask_order(entries) - 2) << 12)); - - /* Now enable the unit */ - out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1); - - out: - return rc; - - out_irq: - dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE, - msg_tx_ring.virt, msg_tx_ring.phys); - - out_dma: - for (i = 0; i < msg_tx_ring.size; i++) - dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE, - msg_tx_ring.virt_buffer[i], - msg_tx_ring.phys_buffer[i]); - - return rc; -} - -/** - * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox - * @mport: Master port implementing the outbound message unit - * @mbox: Mailbox to close - * - * Disables the outbound message unit, free all buffers, and - * frees the outbound message interrupt. - */ -void rio_close_outb_mbox(struct rio_mport *mport, int mbox) -{ - /* Disable inbound message unit */ - out_be32((void *)&msg_regs->omr, 0); - - /* Free ring */ - dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE, - msg_tx_ring.virt, msg_tx_ring.phys); - - /* Free interrupt */ - free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport); -} - -/** - * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler - * @irq: Linux interrupt number - * @dev_instance: Pointer to interrupt-specific data - * - * Handles inbound message interrupts. Executes a registered inbound - * mailbox event handler and acks the interrupt occurrence. - */ -static irqreturn_t -mpc85xx_rio_rx_handler(int irq, void *dev_instance) -{ - int isr; - struct rio_mport *port = (struct rio_mport *)dev_instance; - - isr = in_be32((void *)&msg_regs->isr); - - if (isr & RIO_MSG_ISR_TE) { - pr_info("RIO: inbound message reception error\n"); - out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE); - goto out; - } - - /* XXX Need to check/dispatch until queue empty */ - if (isr & RIO_MSG_ISR_DIQI) { - /* - * We implement *only* mailbox 0, but can receive messages - * for any mailbox/letter to that mailbox destination. So, - * make the callback with an unknown/invalid mailbox number - * argument. - */ - port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1); - - /* Ack the queueing interrupt */ - out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI); - } - - out: - return IRQ_HANDLED; -} - -/** - * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox - * @mport: Master port implementing the inbound message unit - * @dev_id: Device specific pointer to pass on event - * @mbox: Mailbox to open - * @entries: Number of entries in the inbound mailbox ring - * - * Initializes buffer ring, request the inbound message interrupt, - * and enables the inbound message unit. Returns %0 on success - * and %-EINVAL or %-ENOMEM on failure. - */ -int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) -{ - int i, rc = 0; - - if ((entries < RIO_MIN_RX_RING_SIZE) || - (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { - rc = -EINVAL; - goto out; - } - - /* Initialize client buffer ring */ - msg_rx_ring.dev_id = dev_id; - msg_rx_ring.size = entries; - msg_rx_ring.rx_slot = 0; - for (i = 0; i < msg_rx_ring.size; i++) - msg_rx_ring.virt_buffer[i] = NULL; - - /* Initialize inbound message ring */ - if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL, - msg_rx_ring.size * - RIO_MAX_MSG_SIZE, - &msg_rx_ring.phys, - GFP_KERNEL))) { - rc = -ENOMEM; - goto out; - } - - /* Point dequeue/enqueue pointers at first entry in ring */ - out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys); - out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys); - - /* Clear interrupt status */ - out_be32((void *)&msg_regs->isr, 0x00000091); - - /* Hook up inbound message handler */ - if ((rc = - request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0, - "msg_rx", (void *)mport)) < 0) { - dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE, - msg_tx_ring.virt_buffer[i], - msg_tx_ring.phys_buffer[i]); - goto out; - } - - /* - * Configure inbound message unit: - * Snooping - * 4KB max message size - * Unmask all interrupt sources - * Disable - */ - out_be32((void *)&msg_regs->imr, 0x001b0060); - - /* Set number of queue entries */ - out_be32((void *)&msg_regs->imr, - in_be32((void *)&msg_regs->imr) | - ((get_bitmask_order(entries) - 2) << 12)); - - /* Now enable the unit */ - out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1); - - out: - return rc; -} - -/** - * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox - * @mport: Master port implementing the inbound message unit - * @mbox: Mailbox to close - * - * Disables the inbound message unit, free all buffers, and - * frees the inbound message interrupt. - */ -void rio_close_inb_mbox(struct rio_mport *mport, int mbox) -{ - /* Disable inbound message unit */ - out_be32((void *)&msg_regs->imr, 0); - - /* Free ring */ - dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE, - msg_rx_ring.virt, msg_rx_ring.phys); - - /* Free interrupt */ - free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport); -} - -/** - * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue - * @mport: Master port implementing the inbound message unit - * @mbox: Inbound mailbox number - * @buf: Buffer to add to inbound queue - * - * Adds the @buf buffer to the MPC85xx inbound message queue. Returns - * %0 on success or %-EINVAL on failure. - */ -int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) -{ - int rc = 0; - - pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", - msg_rx_ring.rx_slot); - - if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) { - printk(KERN_ERR - "RIO: error adding inbound buffer %d, buffer exists\n", - msg_rx_ring.rx_slot); - rc = -EINVAL; - goto out; - } - - msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf; - if (++msg_rx_ring.rx_slot == msg_rx_ring.size) - msg_rx_ring.rx_slot = 0; - - out: - return rc; -} - -EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer); - -/** - * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit - * @mport: Master port implementing the inbound message unit - * @mbox: Inbound mailbox number - * - * Gets the next available inbound message from the inbound message queue. - * A pointer to the message is returned on success or NULL on failure. - */ -void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) -{ - u32 imr; - u32 phys_buf, virt_buf; - void *buf = NULL; - int buf_idx; - - phys_buf = in_be32((void *)&msg_regs->ifqdpar); - - /* If no more messages, then bail out */ - if (phys_buf == in_be32((void *)&msg_regs->ifqepar)) - goto out2; - - virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys); - buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; - buf = msg_rx_ring.virt_buffer[buf_idx]; - - if (!buf) { - printk(KERN_ERR - "RIO: inbound message copy failed, no buffers\n"); - goto out1; - } - - /* Copy max message size, caller is expected to allocate that big */ - memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); - - /* Clear the available buffer */ - msg_rx_ring.virt_buffer[buf_idx] = NULL; - - out1: - imr = in_be32((void *)&msg_regs->imr); - out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI); - - out2: - return buf; -} - -EXPORT_SYMBOL_GPL(rio_hw_get_inb_message); - -/** - * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler - * @irq: Linux interrupt number - * @dev_instance: Pointer to interrupt-specific data - * - * Handles doorbell interrupts. Parses a list of registered - * doorbell event handlers and executes a matching event handler. - */ -static irqreturn_t -mpc85xx_rio_dbell_handler(int irq, void *dev_instance) -{ - int dsr; - struct rio_mport *port = (struct rio_mport *)dev_instance; - - dsr = in_be32((void *)&msg_regs->dsr); - - if (dsr & DOORBELL_DSR_TE) { - pr_info("RIO: doorbell reception error\n"); - out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE); - goto out; - } - - if (dsr & DOORBELL_DSR_QFI) { - pr_info("RIO: doorbell queue full\n"); - out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI); - goto out; - } - - /* XXX Need to check/dispatch until queue empty */ - if (dsr & DOORBELL_DSR_DIQI) { - u32 dmsg = - (u32) dbell_ring.virt + - (in_be32((void *)&msg_regs->dqdpar) & 0xfff); - u32 dmr; - struct rio_dbell *dbell; - int found = 0; - - pr_debug - ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", - DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); - - list_for_each_entry(dbell, &port->dbells, node) { - if ((dbell->res->start <= DBELL_INF(dmsg)) && - (dbell->res->end >= DBELL_INF(dmsg))) { - found = 1; - break; - } - } - if (found) { - dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), - DBELL_INF(dmsg)); - } else { - pr_debug - ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", - DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); - } - dmr = in_be32((void *)&msg_regs->dmr); - out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI); - out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI); - } - - out: - return IRQ_HANDLED; -} - -/** - * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init - * @mport: Master port implementing the inbound doorbell unit - * - * Initializes doorbell unit hardware and inbound DMA buffer - * ring. Called from mpc85xx_rio_setup(). Returns %0 on success - * or %-ENOMEM on failure. - */ -static int mpc85xx_rio_doorbell_init(struct rio_mport *mport) -{ - int rc = 0; - - /* Map outbound doorbell window immediately after maintenance window */ - if (!(dbell_win = - (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, - RIO_DBELL_WIN_SIZE))) { - printk(KERN_ERR - "RIO: unable to map outbound doorbell window\n"); - rc = -ENOMEM; - goto out; - } - - /* Initialize inbound doorbells */ - if (!(dbell_ring.virt = dma_alloc_coherent(NULL, - 512 * DOORBELL_MESSAGE_SIZE, - &dbell_ring.phys, - GFP_KERNEL))) { - printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); - rc = -ENOMEM; - iounmap((void *)dbell_win); - goto out; - } - - /* Point dequeue/enqueue pointers at first entry in ring */ - out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys); - out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys); - - /* Clear interrupt status */ - out_be32((void *)&msg_regs->dsr, 0x00000091); - - /* Hook up doorbell handler */ - if ((rc = - request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0, - "dbell_rx", (void *)mport) < 0)) { - iounmap((void *)dbell_win); - dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE, - dbell_ring.virt, dbell_ring.phys); - printk(KERN_ERR - "MPC85xx RIO: unable to request inbound doorbell irq"); - goto out; - } - - /* Configure doorbells for snooping, 512 entries, and enable */ - out_be32((void *)&msg_regs->dmr, 0x00108161); - - out: - return rc; -} - -static char *cmdline = NULL; - -static int mpc85xx_rio_get_hdid(int index) -{ - /* XXX Need to parse multiple entries in some format */ - if (!cmdline) - return -1; - - return simple_strtol(cmdline, NULL, 0); -} - -static int mpc85xx_rio_get_cmdline(char *s) -{ - if (!s) - return 0; - - cmdline = s; - return 1; -} - -__setup("riohdid=", mpc85xx_rio_get_cmdline); - -/** - * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface - * @law_start: Starting physical address of RapidIO LAW - * @law_size: Size of RapidIO LAW - * - * Initializes MPC85xx RapidIO hardware interface, configures - * master port with system-specific info, and registers the - * master port with the RapidIO subsystem. - */ -void mpc85xx_rio_setup(int law_start, int law_size) -{ - struct rio_ops *ops; - struct rio_mport *port; - - ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL); - ops->lcread = mpc85xx_local_config_read; - ops->lcwrite = mpc85xx_local_config_write; - ops->cread = mpc85xx_rio_config_read; - ops->cwrite = mpc85xx_rio_config_write; - ops->dsend = mpc85xx_rio_doorbell_send; - - port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL); - port->id = 0; - port->index = 0; - INIT_LIST_HEAD(&port->dbells); - port->iores.start = law_start; - port->iores.end = law_start + law_size; - port->iores.flags = IORESOURCE_MEM; - - rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); - rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); - rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); - strcpy(port->name, "RIO0 mport"); - - port->ops = ops; - port->host_deviceid = mpc85xx_rio_get_hdid(port->id); - - rio_register_mport(port); - - regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000); - atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET); - maint_atmu_regs = atmu_regs + 1; - dbell_atmu_regs = atmu_regs + 2; - msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET); - - /* Configure maintenance transaction window */ - out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000); - out_be32((void *)&maint_atmu_regs->rowar, 0x80077015); - - maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE); - - /* Configure outbound doorbell window */ - out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400); - out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b); - mpc85xx_rio_doorbell_init(port); -} diff --git a/arch/ppc/syslib/ppc85xx_rio.h b/arch/ppc/syslib/ppc85xx_rio.h deleted file mode 100644 index 6d3ff30b1579..000000000000 --- a/arch/ppc/syslib/ppc85xx_rio.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * MPC85xx RapidIO definitions - * - * Copyright 2005 MontaVista Software, Inc. - * Matt Porter <mporter@kernel.crashing.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PPC_SYSLIB_PPC85XX_RIO_H -#define __PPC_SYSLIB_PPC85XX_RIO_H - -#include <linux/init.h> - -extern void mpc85xx_rio_setup(int law_start, int law_size); - -#endif /* __PPC_SYSLIB_PPC85XX_RIO_H */ diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c deleted file mode 100644 index 2475ec6600fe..000000000000 --- a/arch/ppc/syslib/ppc85xx_setup.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * MPC85XX common board code - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/types.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/serial.h> -#include <linux/tty.h> /* for linux/serial_core.h */ -#include <linux/serial_core.h> -#include <linux/serial_8250.h> - -#include <asm/time.h> -#include <asm/mpc85xx.h> -#include <asm/immap_85xx.h> -#include <asm/mmu.h> -#include <asm/ppc_sys.h> -#include <asm/kgdb.h> -#include <asm/machdep.h> - -#include <syslib/ppc85xx_setup.h> - -extern void abort(void); - -/* Return the amount of memory */ -unsigned long __init -mpc85xx_find_end_of_memory(void) -{ - bd_t *binfo; - - binfo = (bd_t *) __res; - - return binfo->bi_memsize; -} - -/* The decrementer counts at the system (internal) clock freq divided by 8 */ -void __init -mpc85xx_calibrate_decr(void) -{ - bd_t *binfo = (bd_t *) __res; - unsigned int freq, divisor; - - /* get the core frequency */ - freq = binfo->bi_busfreq; - - /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */ - divisor = 8; - tb_ticks_per_jiffy = freq / divisor / HZ; - tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); - - /* Set the time base to zero */ - mtspr(SPRN_TBWL, 0); - mtspr(SPRN_TBWU, 0); - - /* Clear any pending timer interrupts */ - mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); - - /* Enable decrementer interrupt */ - mtspr(SPRN_TCR, TCR_DIE); -} - -#ifdef CONFIG_SERIAL_8250 -void __init -mpc85xx_early_serial_map(void) -{ -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - struct uart_port serial_req; -#endif - struct plat_serial8250_port *pdata; - bd_t *binfo = (bd_t *) __res; - pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART); - - /* Setup serial port access */ - pdata[0].uartclk = binfo->bi_busfreq; - pdata[0].mapbase += binfo->bi_immr_base; - pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - memset(&serial_req, 0, sizeof (serial_req)); - serial_req.iotype = UPIO_MEM; - serial_req.mapbase = pdata[0].mapbase; - serial_req.membase = pdata[0].membase; - serial_req.regshift = 0; - - gen550_init(0, &serial_req); -#endif - - pdata[1].uartclk = binfo->bi_busfreq; - pdata[1].mapbase += binfo->bi_immr_base; - pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Assume gen550_init() doesn't modify serial_req */ - serial_req.mapbase = pdata[1].mapbase; - serial_req.membase = pdata[1].membase; - - gen550_init(1, &serial_req); -#endif -} -#endif - -void -mpc85xx_restart(char *cmd) -{ - local_irq_disable(); - abort(); -} - -void -mpc85xx_power_off(void) -{ - local_irq_disable(); - for(;;); -} - -void -mpc85xx_halt(void) -{ - local_irq_disable(); - for(;;); -} - -#ifdef CONFIG_PCI - -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) -extern void mpc85xx_cds_enable_via(struct pci_controller *hose); -extern void mpc85xx_cds_fixup_via(struct pci_controller *hose); -#endif - -static void __init -mpc85xx_setup_pci1(struct pci_controller *hose) -{ - volatile struct ccsr_pci *pci; - volatile struct ccsr_guts *guts; - unsigned short temps; - bd_t *binfo = (bd_t *) __res; - - pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET, - MPC85xx_PCI1_SIZE); - - guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET, - MPC85xx_GUTS_SIZE); - - early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps); - temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - early_write_config_word(hose, 0, 0, PCI_COMMAND, temps); - -#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ - if (guts->pordevsr & PORDEVSR_PCI) { - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); - } else { - /* PCI-X init */ - temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps); - } - - /* Disable all windows (except powar0 since its ignored) */ - pci->powar1 = 0; - pci->powar2 = 0; - pci->powar3 = 0; - pci->powar4 = 0; - pci->piwar1 = 0; - pci->piwar2 = 0; - pci->piwar3 = 0; - - /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */ - pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff; - pci->potear1 = 0x00000000; - pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff; - /* Enable, Mem R/W */ - pci->powar1 = 0x80044000 | - (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1); - - /* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */ - pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff; - pci->potear2 = 0x00000000; - pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff; - /* Enable, IO R/W */ - pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1); - - /* Setup 2G inbound Memory Window @ 0 */ - pci->pitar1 = 0x00000000; - pci->piwbar1 = 0x00000000; - pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local - Mem, Snoop R/W, 2G */ -} - - -extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin); -extern int mpc85xx_exclude_device(u_char bus, u_char devfn); - -#ifdef CONFIG_85xx_PCI2 -static void __init -mpc85xx_setup_pci2(struct pci_controller *hose) -{ - volatile struct ccsr_pci *pci; - unsigned short temps; - bd_t *binfo = (bd_t *) __res; - - pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET, - MPC85xx_PCI2_SIZE); - - early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps); - temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps); - early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80); - - /* Disable all windows (except powar0 since its ignored) */ - pci->powar1 = 0; - pci->powar2 = 0; - pci->powar3 = 0; - pci->powar4 = 0; - pci->piwar1 = 0; - pci->piwar2 = 0; - pci->piwar3 = 0; - - /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */ - pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff; - pci->potear1 = 0x00000000; - pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff; - /* Enable, Mem R/W */ - pci->powar1 = 0x80044000 | - (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1); - - /* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */ - pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff; - pci->potear2 = 0x00000000; - pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff; - /* Enable, IO R/W */ - pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1); - - /* Setup 2G inbound Memory Window @ 0 */ - pci->pitar1 = 0x00000000; - pci->piwbar1 = 0x00000000; - pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local - Mem, Snoop R/W, 2G */ -} -#endif /* CONFIG_85xx_PCI2 */ - -int mpc85xx_pci1_last_busno = 0; - -void __init -mpc85xx_setup_hose(void) -{ - struct pci_controller *hose_a; -#ifdef CONFIG_85xx_PCI2 - struct pci_controller *hose_b; -#endif - bd_t *binfo = (bd_t *) __res; - - hose_a = pcibios_alloc_controller(); - - if (!hose_a) - return; - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = mpc85xx_map_irq; - - hose_a->first_busno = 0; - hose_a->bus_offset = 0; - hose_a->last_busno = 0xff; - - setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, - binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); - hose_a->set_cfg_type = 1; - - mpc85xx_setup_pci1(hose_a); - - hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET; - hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM; - hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM; - - hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO; - hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO; - hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE; -#ifdef CONFIG_85xx_PCI2 - hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE, - MPC85XX_PCI1_IO_SIZE + - MPC85XX_PCI2_IO_SIZE); -#else - hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE, - MPC85XX_PCI1_IO_SIZE); -#endif - isa_io_base = (unsigned long)hose_a->io_base_virt; - - /* setup resources */ - pci_init_resource(&hose_a->mem_resources[0], - MPC85XX_PCI1_LOWER_MEM, - MPC85XX_PCI1_UPPER_MEM, - IORESOURCE_MEM, "PCI1 host bridge"); - - pci_init_resource(&hose_a->io_resource, - MPC85XX_PCI1_LOWER_IO, - MPC85XX_PCI1_UPPER_IO, - IORESOURCE_IO, "PCI1 host bridge"); - - ppc_md.pci_exclude_device = mpc85xx_exclude_device; - -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) - /* Pre pciauto_bus_scan VIA init */ - mpc85xx_cds_enable_via(hose_a); -#endif - - hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); - -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) - /* Post pciauto_bus_scan VIA fixup */ - mpc85xx_cds_fixup_via(hose_a); -#endif - -#ifdef CONFIG_85xx_PCI2 - hose_b = pcibios_alloc_controller(); - - if (!hose_b) - return; - - hose_b->bus_offset = hose_a->last_busno + 1; - hose_b->first_busno = hose_a->last_busno + 1; - hose_b->last_busno = 0xff; - - setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, - binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); - hose_b->set_cfg_type = 1; - - mpc85xx_setup_pci2(hose_b); - - hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET; - hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM; - hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM; - - hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO; - hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO; - hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE; - hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE; - - /* setup resources */ - pci_init_resource(&hose_b->mem_resources[0], - MPC85XX_PCI2_LOWER_MEM, - MPC85XX_PCI2_UPPER_MEM, - IORESOURCE_MEM, "PCI2 host bridge"); - - pci_init_resource(&hose_b->io_resource, - MPC85XX_PCI2_LOWER_IO, - MPC85XX_PCI2_UPPER_IO, - IORESOURCE_IO, "PCI2 host bridge"); - - hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno); - - /* let board code know what the last bus number was on PCI1 */ - mpc85xx_pci1_last_busno = hose_a->last_busno; -#endif - return; -} -#endif /* CONFIG_PCI */ - - diff --git a/arch/ppc/syslib/ppc85xx_setup.h b/arch/ppc/syslib/ppc85xx_setup.h deleted file mode 100644 index 6ff79995210b..000000000000 --- a/arch/ppc/syslib/ppc85xx_setup.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * MPC85XX common board definitions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef __PPC_SYSLIB_PPC85XX_SETUP_H -#define __PPC_SYSLIB_PPC85XX_SETUP_H - -#include <linux/init.h> -#include <asm/ppcboot.h> - -extern unsigned long mpc85xx_find_end_of_memory(void) __init; -extern void mpc85xx_calibrate_decr(void) __init; -extern void mpc85xx_early_serial_map(void) __init; -extern void mpc85xx_restart(char *cmd); -extern void mpc85xx_power_off(void); -extern void mpc85xx_halt(void); -extern void mpc85xx_setup_hose(void) __init; - -/* PCI config */ -#define PCI1_CFG_ADDR_OFFSET (0x8000) -#define PCI1_CFG_DATA_OFFSET (0x8004) - -#define PCI2_CFG_ADDR_OFFSET (0x9000) -#define PCI2_CFG_DATA_OFFSET (0x9004) - -/* Additional register for PCI-X configuration */ -#define PCIX_NEXT_CAP 0x60 -#define PCIX_CAP_ID 0x61 -#define PCIX_COMMAND 0x62 -#define PCIX_STATUS 0x64 - -/* Serial Config */ -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 2 -#endif - -#ifndef BASE_BAUD -#define BASE_BAUD 115200 -#endif - -/* Offset of CPM register space */ -#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET) - -#endif /* __PPC_SYSLIB_PPC85XX_SETUP_H */ diff --git a/arch/ppc/syslib/ppc8xx_pic.c b/arch/ppc/syslib/ppc8xx_pic.c index e8619c750732..bce9a75c80e3 100644 --- a/arch/ppc/syslib/ppc8xx_pic.c +++ b/arch/ppc/syslib/ppc8xx_pic.c @@ -16,7 +16,7 @@ extern int cpm_get_irq(void); * the only interrupt controller. Some boards, like the MBX and * Sandpoint have the 8259 as a secondary controller. Depending * upon the processor type, the internal controller can have as - * few as 16 interrups or as many as 64. We could use the + * few as 16 interrupts or as many as 64. We could use the * "clear_bit()" and "set_bit()" functions like other platforms, * but they are overkill for us. */ diff --git a/arch/ppc/syslib/ppc8xx_pic.h b/arch/ppc/syslib/ppc8xx_pic.h index d7d9f651a91b..53bcd97ef7f5 100644 --- a/arch/ppc/syslib/ppc8xx_pic.h +++ b/arch/ppc/syslib/ppc8xx_pic.h @@ -6,7 +6,6 @@ extern struct hw_interrupt_type ppc8xx_pic; -void m8xx_pic_init(void); void m8xx_do_IRQ(struct pt_regs *regs, int cpu); int m8xx_get_irq(struct pt_regs *regs); diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c index 2d48018b71d9..837183c24dfc 100644 --- a/arch/ppc/syslib/ppc_sys.c +++ b/arch/ppc/syslib/ppc_sys.c @@ -185,7 +185,7 @@ void platform_notify_map(const struct platform_notify_dev_map *map, */ /* - Here we'll replace .name pointers with fixed-lenght strings + Here we'll replace .name pointers with fixed-length strings Hereby, this should be called *before* any func stuff triggeded. */ void ppc_sys_device_initfunc(void) |
