diff options
Diffstat (limited to 'arch/mips/include')
24 files changed, 800 insertions, 141 deletions
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 49df8c4c9d25..bac4a960b24c 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long * __clear_bit(nr, addr); } -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - /* * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists */ -static inline unsigned long __fls(unsigned long x) +static inline unsigned long __fls(unsigned long word) { - int lz; + int num; - if (sizeof(x) == 4) { + if (BITS_PER_LONG == 32 && + __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" " .set pop \n" - : "=r" (lz) - : "r" (x)); + : "=r" (num) + : "r" (word)); - return 31 - lz; + return 31 - num; } - BUG_ON(sizeof(x) != 8); + if (BITS_PER_LONG == 64 && + __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) { + __asm__( + " .set push \n" + " .set mips64 \n" + " dclz %0, %1 \n" + " .set pop \n" + : "=r" (num) + : "r" (word)); - __asm__( - " .set push \n" - " .set mips64 \n" - " dclz %0, %1 \n" - " .set pop \n" - : "=r" (lz) - : "r" (x)); + return 63 - num; + } + + num = BITS_PER_LONG - 1; - return 63 - lz; +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; } /* @@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word) * This is defined the same way as ffs. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ -static inline int fls(int word) +static inline int fls(int x) { - __asm__("clz %0, %1" : "=r" (word) : "r" (word)); + int r; - return 32 - word; -} + if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + __asm__("clz %0, %1" : "=r" (x) : "r" (x)); -#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) -static inline int fls64(__u64 word) -{ - __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); + return 32 - x; + } - return 64 - word; + r = 32; + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; } -#else + #include <asm-generic/bitops/fls64.h> -#endif /* * ffs - find first bit set. @@ -646,16 +694,6 @@ static inline int ffs(int word) return fls(word & -word); } -#else - -#include <asm-generic/bitops/__ffs.h> -#include <asm-generic/bitops/__fls.h> -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/fls.h> -#include <asm-generic/bitops/fls64.h> - -#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ - #include <asm-generic/bitops/ffz.h> #include <asm-generic/bitops/find.h> diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 25b980c91e7e..44437ed765e8 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -29,6 +29,7 @@ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ +#define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_MULOVF 1023 /* Multiply overflow */ #endif /* __ASM_BREAK_H */ diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h index 7eb63de808bc..08ea46863fe5 100644 --- a/arch/mips/include/asm/bug.h +++ b/arch/mips/include/asm/bug.h @@ -7,20 +7,31 @@ #include <asm/break.h> -#define BUG() \ -do { \ - __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ -} while (0) +static inline void __noreturn BUG(void) +{ + __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); + /* Fool GCC into thinking the function doesn't return. */ + while (1) + ; +} #define HAVE_ARCH_BUG #if (_MIPS_ISA > _MIPS_ISA_MIPS1) -#define BUG_ON(condition) \ -do { \ - __asm__ __volatile__("tne $0, %0, %1" \ - : : "r" (condition), "i" (BRK_BUG)); \ -} while (0) +static inline void __BUG_ON(unsigned long condition) +{ + if (__builtin_constant_p(condition)) { + if (condition) + BUG(); + else + return; + } + __asm__ __volatile__("tne $0, %0, %1" + : : "r" (condition), "i" (BRK_BUG)); +} + +#define BUG_ON(C) __BUG_ON((unsigned long)(C)) #define HAVE_ARCH_BUG_ON diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index fe7dc2d59b69..2988d29a0867 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -11,11 +11,19 @@ #include <linux/compiler.h> #include <asm/types.h> -#ifdef __GNUC__ +#if defined(__MIPSEB__) +# define __BIG_ENDIAN +#elif defined(__MIPSEL__) +# define __LITTLE_ENDIAN +#else +# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" +#endif + +#define __SWAB_64_THRU_32__ #ifdef CONFIG_CPU_MIPSR2 -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { __asm__( " wsbh %0, %1 \n" @@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) return x; } -#define __arch__swab16(x) ___arch__swab16(x) +#define __arch_swab16 __arch_swab16 -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __asm__( " wsbh %0, %1 \n" @@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) return x; } -#define __arch__swab32(x) ___arch__swab32(x) +#define __arch_swab32 __arch_swab32 #ifdef CONFIG_CPU_MIPS64_R2 - -static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) +static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( " dsbh %0, %1 \n" @@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) return x; } - -#define __arch__swab64(x) ___arch__swab64(x) - +#define __arch_swab64 __arch_swab64 #endif /* CONFIG_CPU_MIPS64_R2 */ #endif /* CONFIG_CPU_MIPSR2 */ -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#if defined(__MIPSEB__) -# include <linux/byteorder/big_endian.h> -#elif defined(__MIPSEL__) -# include <linux/byteorder/little_endian.h> -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif +#include <linux/byteorder.h> #endif /* _ASM_BYTEORDER_H */ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 5ea701fc3425..12d12dfe73c0 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -141,6 +141,8 @@ #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) +#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ + cpu_has_mips64r1 | cpu_has_mips64r2) #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h deleted file mode 100644 index 6983b6ff0af3..000000000000 --- a/arch/mips/include/asm/ds1286.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - * - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_DS1286_H -#define _ASM_DS1286_H - -#include <ds1286.h> - -#endif /* _ASM_DS1286_H */ diff --git a/arch/mips/include/asm/emma2rh/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h index 6a1af0af51e3..30aea91de626 100644 --- a/arch/mips/include/asm/emma2rh/emma2rh.h +++ b/arch/mips/include/asm/emma/emma2rh.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/emma2rh/emma2rh.h + * arch/mips/include/asm/emma/emma2rh.h * This file is EMMA2RH common header. * * Copyright (C) NEC Electronics Corporation 2005-2006 @@ -21,8 +21,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_EMMA2RH_EMMA2RH_H -#define __ASM_EMMA2RH_EMMA2RH_H +#ifndef __ASM_EMMA_EMMA2RH_H +#define __ASM_EMMA_EMMA2RH_H #include <irq.h> @@ -206,7 +206,6 @@ static inline void emma2rh_out32(u32 offset, u32 val) static inline u32 emma2rh_in32(u32 offset) { u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); return val; } @@ -219,7 +218,6 @@ static inline void emma2rh_out16(u32 offset, u16 val) static inline u16 emma2rh_in16(u32 offset) { u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); return val; } @@ -232,7 +230,6 @@ static inline void emma2rh_out8(u32 offset, u8 val) static inline u8 emma2rh_in8(u32 offset) { u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); - emma2rh_sync(); return val; } @@ -324,10 +321,10 @@ static inline u8 emma2rh_in8(u32 offset) /* * include the board dependent part */ -#if defined(CONFIG_MARKEINS) -#include <asm/emma2rh/markeins.h> +#ifdef CONFIG_NEC_MARKEINS +#include <asm/emma/markeins.h> #else #error "Unknown EMMA2RH board!" #endif -#endif /* __ASM_EMMA2RH_EMMA2RH_H */ +#endif /* __ASM_EMMA_EMMA2RH_H */ diff --git a/arch/mips/include/asm/emma2rh/markeins.h b/arch/mips/include/asm/emma/markeins.h index 973b0628490d..973b0628490d 100644 --- a/arch/mips/include/asm/emma2rh/markeins.h +++ b/arch/mips/include/asm/emma/markeins.h diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 2731c38bd7ae..e5189572956c 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -23,6 +23,9 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H +#include <asm/break.h> +#include <asm/inst.h> + struct mips_fpu_emulator_stats { unsigned int emulated; unsigned int loads; @@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats { extern struct mips_fpu_emulator_stats fpuemustats; +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long cpc); +extern int do_dsemulret(struct pt_regs *xcp); + +/* + * Instruction inserted following the badinst to further tag the sequence + */ +#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */ + +/* + * Break instruction with special math emu break code set + */ +#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16)) + #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h deleted file mode 100644 index f44852e9a96d..000000000000 --- a/arch/mips/include/asm/m48t35.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip - */ -#ifndef _ASM_M48T35_H -#define _ASM_M48T35_H - -#include <linux/spinlock.h> - -extern spinlock_t rtc_lock; - -struct m48t35_rtc { - volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */ - volatile u8 control; - volatile u8 sec; - volatile u8 min; - volatile u8 hour; - volatile u8 day; - volatile u8 date; - volatile u8 month; - volatile u8 year; -}; - -#define M48T35_RTC_SET 0x80 -#define M48T35_RTC_STOPPED 0x80 -#define M48T35_RTC_READ 0x40 - -#endif /* _ASM_M48T35_H */ diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h new file mode 100644 index 000000000000..ea6aa143b78e --- /dev/null +++ b/arch/mips/include/asm/mach-lemote/pci.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + */ + +#ifndef _LEMOTE_PCI_H_ +#define _LEMOTE_PCI_H_ + +#define LOONGSON2E_PCI_MEM_START 0x14000000UL +#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL +#define LOONGSON2E_PCI_IO_START 0x00004000UL +#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL + +#endif /* !_LEMOTE_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h new file mode 100644 index 000000000000..8de0eb9c98a3 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/gpio.h @@ -0,0 +1,172 @@ +/* + * gpio.h: GPIO Support for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel <chris.steel@nxp.com> + * Daniel Laird <daniel.j.laird@nxp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H +#define __ASM_MIPS_MACH_PNX833X_GPIO_H + +/* BIG FAT WARNING: races danger! + No protections exist here. Current users are only early init code, + when locking is not needed because no cuncurency yet exists there, + and GPIO IRQ dispatcher, which does locking. + However, if many uses will ever happen, proper locking will be needed + - including locking between different uses +*/ + +#include "pnx833x.h" + +#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0) +#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0) + +/* Initialize GPIO to a known state */ +static inline void pnx833x_gpio_init(void) +{ + PNX833X_PIO_DIR = 0; + PNX833X_PIO_DIR2 = 0; + PNX833X_PIO_SEL = 0; + PNX833X_PIO_SEL2 = 0; + PNX833X_PIO_INT_EDGE = 0; + PNX833X_PIO_INT_HI = 0; + PNX833X_PIO_INT_LO = 0; + + /* clear any GPIO interrupt requests */ + PNX833X_PIO_INT_CLEAR = 0xffff; + PNX833X_PIO_INT_CLEAR = 0; + PNX833X_PIO_INT_ENABLE = 0; +} + +/* Select GPIO direction for a pin */ +static inline void pnx833x_gpio_select_input(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} +static inline void pnx833x_gpio_select_output(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_DIR, pin); + else + SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); +} + +/* Select GPIO or alternate function for a pin */ +static inline void pnx833x_gpio_select_function_io(unsigned int pin) +{ + if (pin < 32) + CLEAR_REG_BIT(PNX833X_PIO_SEL, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} +static inline void pnx833x_gpio_select_function_alt(unsigned int pin) +{ + if (pin < 32) + SET_REG_BIT(PNX833X_PIO_SEL, pin); + else + SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31); +} + +/* Read GPIO pin */ +static inline int pnx833x_gpio_read(unsigned int pin) +{ + if (pin < 32) + return (PNX833X_PIO_IN >> pin) & 1; + else + return (PNX833X_PIO_IN2 >> (pin & 31)) & 1; +} + +/* Write GPIO pin */ +static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin) +{ + if (pin < 32) { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT, pin); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT, pin); + } else { + if (val) + SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + else + CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31); + } +} + +/* Configure GPIO interrupt */ +#define GPIO_INT_NONE 0 +#define GPIO_INT_LEVEL_LOW 1 +#define GPIO_INT_LEVEL_HIGH 2 +#define GPIO_INT_EDGE_RISING 3 +#define GPIO_INT_EDGE_FALLING 4 +#define GPIO_INT_EDGE_BOTH 5 +static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin) +{ + switch (when) { + case GPIO_INT_LEVEL_LOW: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_LEVEL_HIGH: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_RISING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_FALLING: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + case GPIO_INT_EDGE_BOTH: + SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + SET_REG_BIT(PNX833X_PIO_INT_HI, pin); + SET_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + default: + CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); + break; + } +} + +/* Enable/disable GPIO interrupt */ +static inline void pnx833x_gpio_enable_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} +static inline void pnx833x_gpio_disable_irq(unsigned int pin) +{ + CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); +} + +/* Clear GPIO interrupt request */ +static inline void pnx833x_gpio_clear_irq(unsigned int pin) +{ + SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); + CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); +} + +#endif diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h new file mode 100644 index 000000000000..657f089b1724 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h @@ -0,0 +1,126 @@ + +/* + * irq.h: IRQ mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel <chris.steel@nxp.com> + * Daniel Laird <daniel.j.laird@nxp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H +#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H +/* + * The "IRQ numbers" are completely virtual. + * + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, + * numbers 49..64 for (virtual) GPIO interrupts. + * + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, + * connected to PIC, which uses core hardware interrupt 2, and also + * a timer interrupt through hardware interrupt 5. + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, + * numbers 65..80 for (virtual) GPIO interrupts. + * + */ +#include <irq.h> + +#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) + +/* Interrupts supported by PIC */ +#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) +#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) +#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) +#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) +#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) +#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) +#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) +#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) +#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) +#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) +#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) +#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) +#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13) +#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14) +#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15) +#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16) +#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17) +#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18) +#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19) +#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20) +#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21) +#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22) +#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23) +#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24) +#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25) +#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26) +#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27) +#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28) +#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29) +#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30) +#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31) +#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32) +#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33) +#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34) +#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35) +#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36) + +#if defined(CONFIG_SOC_PNX8335) +#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37) +#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38) +#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39) +#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40) +#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41) +#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42) +#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43) +#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44) +#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45) +#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46) +#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47) +#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48) +#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49) +#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50) +#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51) +#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52) +#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53) +#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54) +#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55) +#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56) +#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57) +#endif + +/* GPIO interrupts */ +#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0) +#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1) +#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2) +#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3) +#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4) +#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5) +#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6) +#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7) +#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8) +#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9) +#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10) +#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11) +#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12) +#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13) +#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14) +#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) + +#endif + diff --git a/arch/mips/include/asm/mach-pnx833x/irq.h b/arch/mips/include/asm/mach-pnx833x/irq.h new file mode 100644 index 000000000000..745114b1d8d5 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/irq.h @@ -0,0 +1,53 @@ +/* + * irq.h: IRQ mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel <chris.steel@nxp.com> + * Daniel Laird <daniel.j.laird@nxp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H +#define __ASM_MIPS_MACH_PNX833X_IRQ_H +/* + * The "IRQ numbers" are completely virtual. + * + * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. + * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, + * numbers 49..64 for (virtual) GPIO interrupts. + * + * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, + * connected to PIC, which uses core hardware interrupt 2, and also + * a timer interrupt through hardware interrupt 5. + * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, + * numbers 65..80 for (virtual) GPIO interrupts. + * + */ +#if defined(CONFIG_SOC_PNX8335) + #define PNX833X_PIC_NUM_IRQ 58 +#else + #define PNX833X_PIC_NUM_IRQ 37 +#endif + +#define MIPS_CPU_NUM_IRQ 8 +#define PNX833X_GPIO_NUM_IRQ 16 + +#define MIPS_CPU_IRQ_BASE 0 +#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ) +#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ) +#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ) + +#endif diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h new file mode 100644 index 000000000000..100f52870e3c --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h @@ -0,0 +1,202 @@ +/* + * pnx833x.h: Register mappings for PNX833X. + * + * Copyright 2008 NXP Semiconductors + * Chris Steel <chris.steel@nxp.com> + * Daniel Laird <daniel.j.laird@nxp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H +#define __ASM_MIPS_MACH_PNX833X_PNX833X_H + +/* All regs are accessed in KSEG1 */ +#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) + +#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs))) + +/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ + +/* Read access to multibit fields */ +#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) +#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) + +/* Use PNX833X_FIELD to extract a field from val */ +#define PNX_FIELD(cpu, val, reg, field) \ + (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ + PNX##cpu##_##reg##_##field##_SHIFT) +#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) +#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) +#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) + +/* Use PNX833X_REGFIELD to extract a field from a register */ +#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) +#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) +#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) + + +#define PNX_WRITEFIELD(cpu, val, reg, field) \ + (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ + ((val) << PNX##cpu##_##reg##_##field##_SHIFT)) +#define PNX833X_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(833X, val, reg, field) +#define PNX8330_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8330, val, reg, field) +#define PNX8335_WRITEFIELD(val, reg, field) \ + PNX_WRITEFIELD(8335, val, reg, field) + + +/* Macros to detect CPU type */ + +#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) +#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 +#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 +#define PNX8330_CONFIG_MODULE_MAJREV 4 +#define PNX8335_CONFIG_MODULE_MAJREV 5 +#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8330_CONFIG_MODULE_MAJREV) +#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ + PNX8335_CONFIG_MODULE_MAJREV) + + + +#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) +#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) + +#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) +#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) +#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) +#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ +#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 +#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) + +#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) +#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ +#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 + +#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f +#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 + +#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) +#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ + +#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 +#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 + +#define PNX833X_PIO_IN PNX833X_REG(0xF000) +#define PNX833X_PIO_OUT PNX833X_REG(0xF004) +#define PNX833X_PIO_DIR PNX833X_REG(0xF008) +#define PNX833X_PIO_SEL PNX833X_REG(0xF014) +#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) +#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) +#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) +#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) +#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) +#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) +#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) +#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) +#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) +#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) + +#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) +#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) +#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) +#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) + +#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) +#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) + +#define PNX833X_CONFIG_USB PNX833X_REG(0x7008) + +#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) +#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) +#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) +#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) + +#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) +#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) +#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) + +#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX833X_IDE_MODULE_ID_VALUE 0xA009 + + +#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) +#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) +#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) +#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) +#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) +#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) +#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) +#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) + +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) +#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 + +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) +#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 + +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) +#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 + +#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) + +#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) +#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 + +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) +#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 + +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) +#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 + +#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) +#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 + +#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ + (PNX833X_MIU_CONFIG_SPI = \ + ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ + ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ + ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ + ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT)) + +#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) +#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) +#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) + +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 + + /* I/O location(gets remapped)*/ +#define PNX8335_NAND_BASE 0x18000000 +/* I/O location with CLE high */ +#define PNX8335_NAND_CLE_MASK 0x00100000 +/* I/O location with ALE high */ +#define PNX8335_NAND_ALE_MASK 0x00010000 + +#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) +#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) +#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) + +#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 +#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 +#define PNX8335_SATA_MODULE_ID_VALUE 0xA099 + +#endif diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h new file mode 100644 index 000000000000..82cd1e97bc2e --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H +#define __ASM_MIPS_MACH_PNX833X_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index c8e554eafce3..b5cf6457305a 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned extern unsigned get_434_reg(unsigned reg_offs); extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); extern unsigned char get_latch_u5(void); +extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); +extern void rb532_gpio_set_istat(int bit, unsigned gpio); #endif /* _RC32434_GPIO_H_ */ diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index 79e8ef67d0d3..f25a84916703 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -40,12 +40,14 @@ #define BTCS 0x010040 #define BTCOMPARE 0x010044 #define GPIOBASE 0x050000 -#define GPIOCFG 0x050004 -#define GPIOD 0x050008 -#define GPIOILEVEL 0x05000C -#define GPIOISTAT 0x050010 -#define GPIONMIEN 0x050014 -#define IMASK6 0x038038 +/* Offsets relative to GPIOBASE */ +#define GPIOFUNC 0x00 +#define GPIOCFG 0x04 +#define GPIOD 0x08 +#define GPIOILEVEL 0x0C +#define GPIOISTAT 0x10 +#define GPIONMIEN 0x14 +#define IMASK6 0x38 #define LO_WPX (1 << 0) #define LO_ALE (1 << 1) #define LO_CLE (1 << 2) diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h new file mode 100644 index 000000000000..5e6912fdd0ed --- /dev/null +++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h @@ -0,0 +1,26 @@ +#ifndef __ASM_MACH_TX49XX_MANGLE_PORT_H +#define __ASM_MACH_TX49XX_MANGLE_PORT_H + +#define __swizzle_addr_b(port) (port) +#define __swizzle_addr_w(port) (port) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +#define ioswabb(a, x) (x) +#define __mem_ioswabb(a, x) (x) +#if defined(CONFIG_TOSHIBA_RBTX4939) && \ + (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \ + defined(__BIG_ENDIAN) +#define NEEDS_TXX9_IOSWABW +extern u16 (*ioswabw)(volatile u16 *a, u16 x); +extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x); +#else +#define ioswabw(a, x) le16_to_cpu(x) +#define __mem_ioswabw(a, x) (x) +#endif +#define ioswabl(a, x) le32_to_cpu(x) +#define __mem_ioswabl(a, x) (x) +#define ioswabq(a, x) le64_to_cpu(x) +#define __mem_ioswabq(a, x) (x) + +#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 979866000da4..9316324d070d 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -192,6 +192,7 @@ #define PM_16M 0x01ffe000 #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 +#define PM_1G 0x7fffe000 #endif diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index de6d09ebbd80..e2e09b2cd265 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -98,6 +98,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "R5000 " #elif defined CONFIG_CPU_R5432 #define MODULE_PROC_FAMILY "R5432 " +#elif defined CONFIG_CPU_R5500 +#define MODULE_PROC_FAMILY "R5500 " #elif defined CONFIG_CPU_R6000 #define MODULE_PROC_FAMILY "R6000 " #elif defined CONFIG_CPU_NEVADA diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 9c22571b160d..c2c8bac43307 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -9,10 +9,6 @@ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H -#ifdef CONFIG_64BIT -#define __ARCH_WANT_COMPAT_SYS_PTRACE -#endif - /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ #define FPR_BASE 32 #define PC 64 @@ -80,25 +76,25 @@ enum pt_watch_style { pt_watch_style_mips64 }; struct mips32_watch_regs { - uint32_t watchlo[8]; + unsigned int watchlo[8]; /* Lower 16 bits of watchhi. */ - uint16_t watchhi[8]; + unsigned short watchhi[8]; /* Valid mask and I R W bits. * bit 0 -- 1 if W bit is usable. * bit 1 -- 1 if R bit is usable. * bit 2 -- 1 if I bit is usable. * bits 3 - 11 -- Valid watchhi mask bits. */ - uint16_t watch_masks[8]; + unsigned short watch_masks[8]; /* The number of valid watch register pairs. */ - uint32_t num_valid; + unsigned int num_valid; } __attribute__((aligned(8))); struct mips64_watch_regs { - uint64_t watchlo[8]; - uint16_t watchhi[8]; - uint16_t watch_masks[8]; - uint32_t num_valid; + unsigned long long watchlo[8]; + unsigned short watchhi[8]; + unsigned short watch_masks[8]; + unsigned int num_valid; } __attribute__((aligned(8))); struct pt_watch_regs { @@ -116,6 +112,7 @@ struct pt_watch_regs { #include <linux/compiler.h> #include <linux/linkage.h> +#include <linux/types.h> #include <asm/isadep.h> struct task_struct; diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index d3bd5c5aa2ec..9601ea950542 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void) /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CEVT_R4K +#ifdef CONFIG_CSRC_R4K extern int init_mips_clocksource(void); #else static inline int init_mips_clocksource(void) diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h index 4316a3e57678..9cde0090cbf6 100644 --- a/arch/mips/include/asm/txx9/generic.h +++ b/arch/mips/include/asm/txx9/generic.h @@ -86,4 +86,9 @@ void txx9_iocled_init(unsigned long baseaddr, int basenum, unsigned int num, int lowactive, const char *color, char **deftriggers); +/* 7SEG LED */ +void txx9_7segled_init(unsigned int num, + void (*putc)(unsigned int pos, unsigned char val)); +int txx9_7segled_putc(unsigned int pos, char c); + #endif /* __ASM_TXX9_GENERIC_H */ |
