diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/armada-370-xp.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-gp.dts | 19 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-xp.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/board-v7.c | 51 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/common.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/platsmp.c | 31 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/pm-board.c | 141 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/pm.c | 218 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/pmsu.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/pmsu_ll.S | 8 |
11 files changed, 462 insertions, 19 deletions
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 83286ec9702c..90dba78554c8 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -180,7 +180,8 @@ mbusc: mbus-controller@20000 { compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; + reg = <0x20000 0x100>, <0x20180 0x20>, + <0x20250 0x8>; }; mpic: interrupt-controller@20000 { diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 0478c55ca656..ea8673647494 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -23,6 +23,7 @@ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "armada-xp-mv78460.dtsi" / { @@ -48,6 +49,14 @@ <0x00000001 0x00000000 0x00000001 0x00000000>; }; + cpus { + pm_pic { + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, + <&gpio0 17 GPIO_ACTIVE_LOW>, + <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 @@ -115,7 +124,15 @@ serial@12300 { status = "okay"; }; - + pinctrl { + pinctrl-0 = <&pic_pins>; + pinctrl-names = "default"; + pic_pins: pic-pins-0 { + marvell,pins = "mpp16", "mpp17", + "mpp18"; + marvell,function = "gpio"; + }; + }; sata@a0000 { nr-ports = <2>; status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index bff9f6c18db1..2be244a96edf 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -35,6 +35,11 @@ }; internal-regs { + sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + L2: l2-cache { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index e24136b42765..b4f01497ce0b 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -7,7 +7,7 @@ CFLAGS_pmsu.o := -march=armv7-a obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o ifeq ($(CONFIG_MACH_MVEBU_V7),y) -obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o +obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o endif diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index e15ead876a48..89a139ed7d5b 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -16,10 +16,12 @@ #include <linux/init.h> #include <linux/clk-provider.h> #include <linux/of_address.h> +#include <linux/of_fdt.h> #include <linux/of_platform.h> #include <linux/io.h> #include <linux/clocksource.h> #include <linux/dma-mapping.h> +#include <linux/memblock.h> #include <linux/mbus.h> #include <linux/signal.h> #include <linux/slab.h> @@ -57,6 +59,54 @@ void __iomem *mvebu_get_scu_base(void) } /* + * When returning from suspend, the platform goes through the + * bootloader, which executes its DDR3 training code. This code has + * the unfortunate idea of using the first 10 KB of each DRAM bank to + * exercise the RAM and calculate the optimal timings. Therefore, this + * area of RAM is overwritten, and shouldn't be used by the kernel if + * suspend/resume is supported. + */ + +#ifdef CONFIG_SUSPEND +#define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K) +static int __init mvebu_scan_mem(unsigned long node, const char *uname, + int depth, void *data) +{ + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); + const __be32 *reg, *endp; + int l; + + if (type == NULL || strcmp(type, "memory")) + return 0; + + reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); + if (reg == NULL) + reg = of_get_flat_dt_prop(node, "reg", &l); + if (reg == NULL) + return 0; + + endp = reg + (l / sizeof(__be32)); + while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { + u64 base, size; + + base = dt_mem_next_cell(dt_root_addr_cells, ®); + size = dt_mem_next_cell(dt_root_size_cells, ®); + + memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ); + } + + return 0; +} + +static void __init mvebu_memblock_reserve(void) +{ + of_scan_flat_dt(mvebu_scan_mem, NULL); +} +#else +static void __init mvebu_memblock_reserve(void) {} +#endif + +/* * Early versions of Armada 375 SoC have a bug where the BootROM * leaves an external data abort pending. The kernel is hit by this * data abort as soon as it enters userspace, because it unmasks the @@ -151,6 +201,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") .init_machine = mvebu_dt_init, .init_irq = mvebu_init_irq, .restart = mvebu_restart, + .reserve = mvebu_memblock_reserve, .dt_compat = armada_370_xp_dt_compat, MACHINE_END diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index 3ccb40c3bf94..3e0aca1f288a 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -25,4 +25,6 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev); void __iomem *mvebu_get_scu_base(void); +int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)); + #endif diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index 622315c185b2..58cc8c1575eb 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -35,7 +35,7 @@ #define AXP_BOOTROM_BASE 0xfff00000 #define AXP_BOOTROM_SIZE 0x100000 -static struct clk *__init get_cpu_clk(int cpu) +static struct clk *get_cpu_clk(int cpu) { struct clk *cpu_clk; struct device_node *np = of_get_cpu_node(cpu, NULL); @@ -48,29 +48,28 @@ static struct clk *__init get_cpu_clk(int cpu) return cpu_clk; } -static void __init set_secondary_cpus_clock(void) +static void set_secondary_cpu_clock(unsigned int cpu) { - int thiscpu, cpu; + int thiscpu; unsigned long rate; struct clk *cpu_clk; - thiscpu = smp_processor_id(); + thiscpu = get_cpu(); + cpu_clk = get_cpu_clk(thiscpu); if (!cpu_clk) - return; + goto out; clk_prepare_enable(cpu_clk); rate = clk_get_rate(cpu_clk); - /* set all the other CPU clk to the same rate than the boot CPU */ - for_each_possible_cpu(cpu) { - if (cpu == thiscpu) - continue; - cpu_clk = get_cpu_clk(cpu); - if (!cpu_clk) - return; - clk_set_rate(cpu_clk, rate); - clk_prepare_enable(cpu_clk); - } + cpu_clk = get_cpu_clk(cpu); + if (!cpu_clk) + goto out; + clk_set_rate(cpu_clk, rate); + clk_prepare_enable(cpu_clk); + +out: + put_cpu(); } static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -80,6 +79,7 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle) pr_info("Booting CPU %d\n", cpu); hw_cpu = cpu_logical_map(cpu); + set_secondary_cpu_clock(hw_cpu); mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup); /* @@ -128,7 +128,6 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) struct resource res; int err; - set_secondary_cpus_clock(); flush_cache_all(); set_cpu_coherent(); diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c new file mode 100644 index 000000000000..6dfd4ab97b2a --- /dev/null +++ b/arch/arm/mach-mvebu/pm-board.c @@ -0,0 +1,141 @@ +/* + * Board-level suspend/resume support. + * + * Copyright (C) 2014 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_gpio.h> +#include <linux/slab.h> +#include "common.h" + +#define ARMADA_XP_GP_PIC_NR_GPIOS 3 + +static void __iomem *gpio_ctrl; +static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS]; +static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS]; + +static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd) +{ + u32 reg, ackcmd; + int i; + + /* Put 001 as value on the GPIOs */ + reg = readl(gpio_ctrl); + for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) + reg &= ~BIT(pic_raw_gpios[i]); + reg |= BIT(pic_raw_gpios[0]); + writel(reg, gpio_ctrl); + + /* Prepare writing 111 to the GPIOs */ + ackcmd = readl(gpio_ctrl); + for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) + ackcmd |= BIT(pic_raw_gpios[i]); + + /* + * Wait a while, the PIC needs quite a bit of time between the + * two GPIO commands. + */ + mdelay(3000); + + asm volatile ( + /* Align to a cache line */ + ".balign 32\n\t" + + /* Enter self refresh */ + "str %[srcmd], [%[sdram_reg]]\n\t" + + /* + * Wait 100 cycles for DDR to enter self refresh, by + * doing 50 times two instructions. + */ + "mov r1, #50\n\t" + "1: subs r1, r1, #1\n\t" + "bne 1b\n\t" + + /* Issue the command ACK */ + "str %[ackcmd], [%[gpio_ctrl]]\n\t" + + /* Trap the processor */ + "b .\n\t" + : : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg), + [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1"); +} + +static int mvebu_armada_xp_gp_pm_init(void) +{ + struct device_node *np; + struct device_node *gpio_ctrl_np; + int ret = 0, i; + + if (!of_machine_is_compatible("marvell,axp-gp")) + return -ENODEV; + + np = of_find_node_by_name(NULL, "pm_pic"); + if (!np) + return -ENODEV; + + for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) { + char *name; + struct of_phandle_args args; + + pic_gpios[i] = of_get_named_gpio(np, "ctrl-gpios", i); + if (pic_gpios[i] < 0) { + ret = -ENODEV; + goto out; + } + + name = kasprintf(GFP_KERNEL, "pic-pin%d", i); + if (!name) { + ret = -ENOMEM; + goto out; + } + + ret = gpio_request(pic_gpios[i], name); + if (ret < 0) { + kfree(name); + goto out; + } + + ret = gpio_direction_output(pic_gpios[i], 0); + if (ret < 0) { + gpio_free(pic_gpios[i]); + kfree(name); + goto out; + } + + ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2, + i, &args); + if (ret < 0) { + gpio_free(pic_gpios[i]); + kfree(name); + goto out; + } + + gpio_ctrl_np = args.np; + pic_raw_gpios[i] = args.args[0]; + } + + gpio_ctrl = of_iomap(gpio_ctrl_np, 0); + if (!gpio_ctrl) + return -ENOMEM; + + mvebu_pm_init(mvebu_armada_xp_gp_pm_enter); + +out: + of_node_put(np); + return ret; +} + +late_initcall(mvebu_armada_xp_gp_pm_init); diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c new file mode 100644 index 000000000000..6573a8f11f70 --- /dev/null +++ b/arch/arm/mach-mvebu/pm.c @@ -0,0 +1,218 @@ +/* + * Suspend/resume support. Currently supporting Armada XP only. + * + * Copyright (C) 2014 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/cpu_pm.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mbus.h> +#include <linux/of_address.h> +#include <linux/suspend.h> +#include <asm/cacheflush.h> +#include <asm/outercache.h> +#include <asm/suspend.h> + +#include "coherency.h" +#include "pmsu.h" + +#define SDRAM_CONFIG_OFFS 0x0 +#define SDRAM_CONFIG_SR_MODE_BIT BIT(24) +#define SDRAM_OPERATION_OFFS 0x18 +#define SDRAM_OPERATION_SELF_REFRESH 0x7 +#define SDRAM_DLB_EVICTION_OFFS 0x30c +#define SDRAM_DLB_EVICTION_THRESHOLD_MASK 0xff + +static void (*mvebu_board_pm_enter)(void __iomem *sdram_reg, u32 srcmd); +static void __iomem *sdram_ctrl; + +static int mvebu_pm_powerdown(unsigned long data) +{ + u32 reg, srcmd; + + flush_cache_all(); + outer_flush_all(); + + /* + * Issue a Data Synchronization Barrier instruction to ensure + * that all state saving has been completed. + */ + dsb(); + + /* Flush the DLB and wait ~7 usec */ + reg = readl(sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); + reg &= ~SDRAM_DLB_EVICTION_THRESHOLD_MASK; + writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); + + udelay(7); + + /* Set DRAM in battery backup mode */ + reg = readl(sdram_ctrl + SDRAM_CONFIG_OFFS); + reg &= ~SDRAM_CONFIG_SR_MODE_BIT; + writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS); + + /* Prepare to go to self-refresh */ + + srcmd = readl(sdram_ctrl + SDRAM_OPERATION_OFFS); + srcmd &= ~0x1F; + srcmd |= SDRAM_OPERATION_SELF_REFRESH; + + mvebu_board_pm_enter(sdram_ctrl + SDRAM_OPERATION_OFFS, srcmd); + + return 0; +} + +#define BOOT_INFO_ADDR 0x3000 +#define BOOT_MAGIC_WORD 0xdeadb002 +#define BOOT_MAGIC_LIST_END 0xffffffff + +/* + * Those registers are accessed before switching the internal register + * base, which is why we hardcode the 0xd0000000 base address, the one + * used by the SoC out of reset. + */ +#define MBUS_WINDOW_12_CTRL 0xd00200b0 +#define MBUS_INTERNAL_REG_ADDRESS 0xd0020080 + +#define SDRAM_WIN_BASE_REG(x) (0x20180 + (0x8*x)) +#define SDRAM_WIN_CTRL_REG(x) (0x20184 + (0x8*x)) + +static phys_addr_t mvebu_internal_reg_base(void) +{ + struct device_node *np; + __be32 in_addr[2]; + + np = of_find_node_by_name(NULL, "internal-regs"); + BUG_ON(!np); + + /* + * Ask the DT what is the internal register address on this + * platform. In the mvebu-mbus DT binding, 0xf0010000 + * corresponds to the internal register window. + */ + in_addr[0] = cpu_to_be32(0xf0010000); + in_addr[1] = 0x0; + + return of_translate_address(np, in_addr); +} + +static void mvebu_pm_store_bootinfo(void) +{ + u32 *store_addr; + phys_addr_t resume_pc; + + store_addr = phys_to_virt(BOOT_INFO_ADDR); + resume_pc = virt_to_phys(armada_370_xp_cpu_resume); + + /* + * The bootloader expects the first two words to be a magic + * value (BOOT_MAGIC_WORD), followed by the address of the + * resume code to jump to. Then, it expects a sequence of + * (address, value) pairs, which can be used to restore the + * value of certain registers. This sequence must end with the + * BOOT_MAGIC_LIST_END magic value. + */ + + writel(BOOT_MAGIC_WORD, store_addr++); + writel(resume_pc, store_addr++); + + /* + * Some platforms remap their internal register base address + * to 0xf1000000. However, out of reset, window 12 starts at + * 0xf0000000 and ends at 0xf7ffffff, which would overlap with + * the internal registers. Therefore, disable window 12. + */ + writel(MBUS_WINDOW_12_CTRL, store_addr++); + writel(0x0, store_addr++); + + /* + * Set the internal register base address to the value + * expected by Linux, as read from the Device Tree. + */ + writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++); + writel(mvebu_internal_reg_base(), store_addr++); + + /* + * Ask the mvebu-mbus driver to store the SDRAM window + * configuration, which has to be restored by the bootloader + * before re-entering the kernel on resume. + */ + store_addr += mvebu_mbus_save_cpu_target(store_addr); + + writel(BOOT_MAGIC_LIST_END, store_addr); +} + +static int mvebu_pm_enter(suspend_state_t state) +{ + if (state != PM_SUSPEND_MEM) + return -EINVAL; + + cpu_pm_enter(); + + mvebu_pm_store_bootinfo(); + cpu_suspend(0, mvebu_pm_powerdown); + + outer_resume(); + + mvebu_v7_pmsu_idle_exit(); + + set_cpu_coherent(); + + cpu_pm_exit(); + + return 0; +} + +static const struct platform_suspend_ops mvebu_pm_ops = { + .enter = mvebu_pm_enter, + .valid = suspend_valid_only_mem, +}; + +int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)) +{ + struct device_node *np; + struct resource res; + + if (!of_machine_is_compatible("marvell,armadaxp")) + return -ENODEV; + + np = of_find_compatible_node(NULL, NULL, + "marvell,armada-xp-sdram-controller"); + if (!np) + return -ENODEV; + + if (of_address_to_resource(np, 0, &res)) { + of_node_put(np); + return -ENODEV; + } + + if (!request_mem_region(res.start, resource_size(&res), + np->full_name)) { + of_node_put(np); + return -EBUSY; + } + + sdram_ctrl = ioremap(res.start, resource_size(&res)); + if (!sdram_ctrl) { + release_mem_region(res.start, resource_size(&res)); + of_node_put(np); + return -ENOMEM; + } + + of_node_put(np); + + mvebu_board_pm_enter = board_pm_enter; + + suspend_set_ops(&mvebu_pm_ops); + + return 0; +} diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h index c2c95db4f648..ea79269c2702 100644 --- a/arch/arm/mach-mvebu/pmsu.h +++ b/arch/arm/mach-mvebu/pmsu.h @@ -17,6 +17,7 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target, phys_addr_t resume_addr_reg); void mvebu_v7_pmsu_idle_exit(void); +void armada_370_xp_cpu_resume(void); int armada_370_xp_pmsu_idle_enter(unsigned long deepidle); int armada_38x_do_cpu_suspend(unsigned long deepidle); diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S index 83d014698314..88651221dbdd 100644 --- a/arch/arm/mach-mvebu/pmsu_ll.S +++ b/arch/arm/mach-mvebu/pmsu_ll.S @@ -30,6 +30,14 @@ ENDPROC(armada_38x_scu_power_up) */ ENTRY(armada_370_xp_cpu_resume) ARM_BE8(setend be ) @ go BE8 if entered LE + /* + * Disable the MMU that might have been enabled in BootROM if + * this code is used in the resume path of a suspend/resume + * cycle. + */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, #1 + mcr p15, 0, r1, c1, c0, 0 bl ll_add_cpu_to_smp_group bl ll_enable_coherency b cpu_resume |
