diff options
Diffstat (limited to 'arch/arm')
470 files changed, 8885 insertions, 23142 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7d7cdf955e5..64ae22c4fce7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -11,6 +11,7 @@ config ARM select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB + select HAVE_ARCH_TRACEHOOK select HAVE_KPROBES if !XIP_KERNEL select HAVE_KRETPROBES if (HAVE_KPROBES) select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) @@ -30,10 +31,15 @@ config ARM select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) select HAVE_C_RECORDMCOUNT select HAVE_GENERIC_HARDIRQS + select HARDIRQS_SW_RESEND + select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW + select GENERIC_IRQ_PROBE + select HARDIRQS_SW_RESEND select CPU_PM if (SUSPEND || CPU_IDLE) select GENERIC_PCI_IOMAP - select HAVE_BPF_JIT if NET + select HAVE_BPF_JIT + select GENERIC_SMP_IDLE_THREAD help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -126,14 +132,6 @@ config TRACE_IRQFLAGS_SUPPORT bool default y -config HARDIRQS_SW_RESEND - bool - default y - -config GENERIC_IRQ_PROBE - bool - default y - config GENERIC_LOCKBREAK bool default y @@ -159,9 +157,6 @@ config ARCH_HAS_CPUFREQ and that the relevant menu configurations are displayed for it. -config ARCH_HAS_CPU_IDLE_WAIT - def_bool y - config GENERIC_HWEIGHT bool default y @@ -280,6 +275,7 @@ config ARCH_INTEGRATOR select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ + select MULTI_IRQ_HANDLER help Support for ARM's Integrator platform. @@ -340,8 +336,8 @@ config ARCH_AT91 select IRQ_DOMAIN select NEED_MACH_IO_H if PCCARD help - This enables support for systems based on the Atmel AT91RM9200, - AT91SAM9 processors. + This enables support for systems based on Atmel + AT91RM9200 and AT91SAM9* processors. config ARCH_BCMRING bool "Broadcom BCMRING" @@ -373,12 +369,12 @@ config ARCH_HIGHBANK Support for the Calxeda Highbank SoC based boards. config ARCH_CLPS711X - bool "Cirrus Logic CLPS711x/EP721x-based" + bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select CPU_ARM720T select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H help - Support for Cirrus Logic 711x/721x based boards. + Support for Cirrus Logic 711x/721x/731x based boards. config ARCH_CNS3XXX bool "Cavium Networks CNS3XXX family" @@ -528,28 +524,6 @@ config ARCH_IOP33X help Support for Intel's IOP33X (XScale) family of processors. -config ARCH_IXP23XX - bool "IXP23XX-based" - depends on MMU - select CPU_XSC3 - select PCI - select ARCH_USES_GETTIMEOFFSET - select NEED_MACH_IO_H - select NEED_MACH_MEMORY_H - help - Support for Intel's IXP23xx (XScale) family of processors. - -config ARCH_IXP2000 - bool "IXP2400/2800-based" - depends on MMU - select CPU_XSCALE - select PCI - select ARCH_USES_GETTIMEOFFSET - select NEED_MACH_IO_H - select NEED_MACH_MEMORY_H - help - Support for Intel's IXP2400/2800 (XScale) family of processors. - config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU @@ -632,7 +606,6 @@ config ARCH_MMP select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select GPIO_PXA - select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ select GENERIC_ALLOCATOR @@ -716,7 +689,6 @@ config ARCH_PXA select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select GPIO_PXA - select TICK_ONESHOT select PLAT_PXA select SPARSE_IRQ select AUTO_ZRELADDR @@ -783,7 +755,6 @@ config ARCH_SA1100 select CPU_FREQ select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP - select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB select HAVE_IDE select NEED_MACH_MEMORY_H @@ -1046,10 +1017,6 @@ source "arch/arm/mach-iop13xx/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" -source "arch/arm/mach-ixp2000/Kconfig" - -source "arch/arm/mach-ixp23xx/Kconfig" - source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-ks8695/Kconfig" @@ -1552,10 +1519,15 @@ config HAVE_ARM_SCU help This option enables support for the ARM system coherency unit +config ARM_ARCH_TIMER + bool "Architected timer support" + depends on CPU_V7 + help + This option enables support for the ARM architected timer + config HAVE_ARM_TWD bool depends on SMP - select TICK_ONESHOT help This options enables support for the ARM timer and watchdog unit diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 047a20780fc1..157900da8782 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -70,8 +70,6 @@ arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4 arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3 # This selects how we optimise for the processor. -tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610 -tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710 tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi @@ -119,7 +117,7 @@ KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/ CHECKFLAGS += -D__arm__ #Default value -head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o +head-y := arch/arm/kernel/head$(MMUEXT).o textofs-y := 0x00008000 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 # We don't want the htc bootloader to corrupt kernel during resume @@ -149,8 +147,6 @@ machine-$(CONFIG_ARCH_INTEGRATOR) := integrator machine-$(CONFIG_ARCH_IOP13XX) := iop13xx machine-$(CONFIG_ARCH_IOP32X) := iop32x machine-$(CONFIG_ARCH_IOP33X) := iop33x -machine-$(CONFIG_ARCH_IXP2000) := ixp2000 -machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood machine-$(CONFIG_ARCH_KS8695) := ks8695 diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index aa5ee49c5c5a..6ab0599c02dd 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -32,10 +32,3 @@ __XScale_start: bic r0, r0, #0x1000 @ clear Icache mcr p15, 0, r0, c1, c0, 0 -#ifdef CONFIG_ARCH_IXP2000 - mov r1, #-1 - mov r0, #0xd6000000 - str r1, [r0, #0x14] - str r1, [r0, #0x18] -#endif - diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index dc7e8ce8e6be..b8c64b80bafc 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -567,6 +567,12 @@ __armv3_mpu_cache_on: mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH +#define CB_BITS 0x08 +#else +#define CB_BITS 0x0c +#endif + __setup_mmu: sub r3, r4, #16384 @ Page directory size bic r3, r3, #0xff @ Align the pointer bic r3, r3, #0x3f00 @@ -578,17 +584,14 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size mov r9, r0, lsr #18 mov r9, r9, lsl #18 @ start of RAM add r10, r9, #0x10000000 @ a reasonable RAM size - mov r1, #0x12 - orr r1, r1, #3 << 10 + mov r1, #0x12 @ XN|U + section mapping + orr r1, r1, #3 << 10 @ AP=11 add r2, r3, #16384 1: cmp r1, r9 @ if virt > start of RAM -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - orrhs r1, r1, #0x08 @ set cacheable -#else - orrhs r1, r1, #0x0c @ set cacheable, bufferable -#endif - cmp r1, r10 @ if virt > end of RAM - bichs r1, r1, #0x0c @ clear cacheable, bufferable + cmphs r10, r1 @ && end of RAM > virt + bic r1, r1, #0x1c @ clear XN|U + C + B + orrlo r1, r1, #0x10 @ Set XN|U for non-RAM + orrhs r1, r1, r6 @ set RAM section settings str r1, [r0], #4 @ 1:1 mapping add r1, r1, #1048576 teq r0, r2 @@ -599,7 +602,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size * so there is no map overlap problem for up to 1 MB compressed kernel. * If the execution is in RAM then we would only be duplicating the above. */ - mov r1, #0x1e + orr r1, r6, #0x04 @ ensure B is set for this orr r1, r1, #3 << 10 mov r2, pc mov r2, r2, lsr #20 @@ -620,6 +623,7 @@ __arm926ejs_mmu_cache_on: __armv4_mmu_cache_on: mov r12, lr #ifdef CONFIG_MMU + mov r6, #CB_BITS | 0x12 @ U bl __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer @@ -641,6 +645,7 @@ __armv7_mmu_cache_on: #ifdef CONFIG_MMU mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 tst r11, #0xf @ VMSA + movne r6, #CB_BITS | 0x02 @ !XN blne __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer @@ -655,7 +660,7 @@ __armv7_mmu_cache_on: orr r0, r0, #1 << 25 @ big-endian page tables #endif orrne r0, r0, #1 @ MMU enabled - movne r1, #-1 + movne r1, #0xfffffffd @ domain 0 = client mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control #endif @@ -668,6 +673,7 @@ __armv7_mmu_cache_on: __fa526_cache_on: mov r12, lr + mov r6, #CB_BITS | 0x12 @ U bl __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache @@ -680,18 +686,6 @@ __fa526_cache_on: mcr p15, 0, r0, c8, c7, 0 @ flush UTLB mov pc, r12 -__arm6_mmu_cache_on: - mov r12, lr - bl __setup_mmu - mov r0, #0 - mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 - mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 - mov r0, #0x30 - bl __common_mmu_cache_on - mov r0, #0 - mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 - mov pc, r12 - __common_mmu_cache_on: #ifndef CONFIG_THUMB2_KERNEL #ifndef DEBUG @@ -756,16 +750,6 @@ call_cache_fn: adr r12, proc_types .align 2 .type proc_types,#object proc_types: - .word 0x41560600 @ ARM6/610 - .word 0xffffffe0 - W(b) __arm6_mmu_cache_off @ works, but slow - W(b) __arm6_mmu_cache_off - mov pc, lr - THUMB( nop ) -@ b __arm6_mmu_cache_on @ untested -@ b __arm6_mmu_cache_off -@ b __armv3_mmu_cache_flush - .word 0x00000000 @ old ARM ID .word 0x0000f000 mov pc, lr @@ -777,8 +761,10 @@ proc_types: .word 0x41007000 @ ARM7/710 .word 0xfff8fe00 - W(b) __arm7_mmu_cache_off - W(b) __arm7_mmu_cache_off + mov pc, lr + THUMB( nop ) + mov pc, lr + THUMB( nop ) mov pc, lr THUMB( nop ) @@ -977,21 +963,6 @@ __armv7_mmu_cache_off: mcr p15, 0, r0, c7, c5, 4 @ ISB mov pc, r12 -__arm6_mmu_cache_off: - mov r0, #0x00000030 @ ARM6 control reg. - b __armv3_mmu_cache_off - -__arm7_mmu_cache_off: - mov r0, #0x00000070 @ ARM7 control reg. - b __armv3_mmu_cache_off - -__armv3_mmu_cache_off: - mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off - mov r0, #0 - mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 - mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 - mov pc, lr - /* * Clean and flush the cache to maintain consistency. * diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 215816f1775f..e8a4e58f1b82 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -11,7 +11,5 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o -obj-$(CONFIG_ARCH_IXP2000) += uengine.o -obj-$(CONFIG_ARCH_IXP23XX) += uengine.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index dcb13494ca0d..c4110d1b1f2d 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -222,7 +222,7 @@ static int it8152_pci_write_config(struct pci_bus *bus, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops it8152_ops = { +struct pci_ops it8152_ops = { .read = it8152_pci_read_config, .write = it8152_pci_write_config, }; @@ -346,9 +346,4 @@ void pcibios_set_master(struct pci_dev *dev) } -struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources); -} - EXPORT_SYMBOL(dma_set_coherent_mask); diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c deleted file mode 100644 index bef408f3d76c..000000000000 --- a/arch/arm/common/uengine.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Generic library functions for the microengines found on the Intel - * IXP2000 series of network processors. - * - * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> - * Dedicated to Marija Kulikova. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of the - * License, or (at your option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/hardware/uengine.h> - -#if defined(CONFIG_ARCH_IXP2000) -#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE -#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID -#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL -#define IXP_RESET1 IXP2000_RESET1 -#else -#if defined(CONFIG_ARCH_IXP23XX) -#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE -#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID -#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL -#define IXP_RESET1 IXP23XX_RESET1 -#else -#error unknown platform -#endif -#endif - -#define USTORE_ADDRESS 0x000 -#define USTORE_DATA_LOWER 0x004 -#define USTORE_DATA_UPPER 0x008 -#define CTX_ENABLES 0x018 -#define CC_ENABLE 0x01c -#define CSR_CTX_POINTER 0x020 -#define INDIRECT_CTX_STS 0x040 -#define ACTIVE_CTX_STS 0x044 -#define INDIRECT_CTX_SIG_EVENTS 0x048 -#define INDIRECT_CTX_WAKEUP_EVENTS 0x050 -#define NN_PUT 0x080 -#define NN_GET 0x084 -#define TIMESTAMP_LOW 0x0c0 -#define TIMESTAMP_HIGH 0x0c4 -#define T_INDEX_BYTE_INDEX 0x0f4 -#define LOCAL_CSR_STATUS 0x180 - -u32 ixp2000_uengine_mask; - -static void *ixp2000_uengine_csr_area(int uengine) -{ - return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10); -} - -/* - * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR - * space means that the microengine we tried to access was also trying - * to access its own CSR space on the same clock cycle as we did. When - * this happens, we lose the arbitration process by default, and the - * read or write we tried to do was not actually performed, so we try - * again until it succeeds. - */ -u32 ixp2000_uengine_csr_read(int uengine, int offset) -{ - void *uebase; - u32 *local_csr_status; - u32 *reg; - u32 value; - - uebase = ixp2000_uengine_csr_area(uengine); - - local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); - reg = (u32 *)(uebase + offset); - do { - value = ixp2000_reg_read(reg); - } while (ixp2000_reg_read(local_csr_status) & 1); - - return value; -} -EXPORT_SYMBOL(ixp2000_uengine_csr_read); - -void ixp2000_uengine_csr_write(int uengine, int offset, u32 value) -{ - void *uebase; - u32 *local_csr_status; - u32 *reg; - - uebase = ixp2000_uengine_csr_area(uengine); - - local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); - reg = (u32 *)(uebase + offset); - do { - ixp2000_reg_write(reg, value); - } while (ixp2000_reg_read(local_csr_status) & 1); -} -EXPORT_SYMBOL(ixp2000_uengine_csr_write); - -void ixp2000_uengine_reset(u32 uengine_mask) -{ - u32 value; - - value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask; - - uengine_mask &= ixp2000_uengine_mask; - ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask); - ixp2000_reg_wrb(IXP_RESET1, value); -} -EXPORT_SYMBOL(ixp2000_uengine_reset); - -void ixp2000_uengine_set_mode(int uengine, u32 mode) -{ - /* - * CTL_STR_PAR_EN: unconditionally enable parity checking on - * control store. - */ - mode |= 0x10000000; - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode); - - /* - * Enable updating of condition codes. - */ - ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000); - - /* - * Initialise other per-microengine registers. - */ - ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00); - ixp2000_uengine_csr_write(uengine, NN_GET, 0x00); - ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0); -} -EXPORT_SYMBOL(ixp2000_uengine_set_mode); - -static int make_even_parity(u32 x) -{ - return hweight32(x) & 1; -} - -static void ustore_write(int uengine, u64 insn) -{ - /* - * Generate even parity for top and bottom 20 bits. - */ - insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41; - insn |= (u64)make_even_parity(insn & 0x000fffff) << 40; - - /* - * Write to microstore. The second write auto-increments - * the USTORE_ADDRESS index register. - */ - ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn); - ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32)); -} - -void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns) -{ - int i; - - /* - * Start writing to microstore at address 0. - */ - ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000); - for (i = 0; i < insns; i++) { - u64 insn; - - insn = (((u64)ucode[0]) << 32) | - (((u64)ucode[1]) << 24) | - (((u64)ucode[2]) << 16) | - (((u64)ucode[3]) << 8) | - ((u64)ucode[4]); - ucode += 5; - - ustore_write(uengine, insn); - } - - /* - * Pad with a few NOPs at the end (to avoid the microengine - * aborting as it prefetches beyond the last instruction), unless - * we run off the end of the instruction store first, at which - * point the address register will wrap back to zero. - */ - for (i = 0; i < 4; i++) { - u32 addr; - - addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS); - if (addr == 0x80000000) - break; - ustore_write(uengine, 0xf0000c0300ULL); - } - - /* - * End programming. - */ - ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000); -} -EXPORT_SYMBOL(ixp2000_uengine_load_microcode); - -void ixp2000_uengine_init_context(int uengine, int context, int pc) -{ - /* - * Select the right context for indirect access. - */ - ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context); - - /* - * Initialise signal masks to immediately go to Ready state. - */ - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1); - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1); - - /* - * Set program counter. - */ - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc); -} -EXPORT_SYMBOL(ixp2000_uengine_init_context); - -void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask) -{ - u32 mask; - - /* - * Enable the specified context to go to Executing state. - */ - mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); - mask |= ctx_mask << 8; - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); -} -EXPORT_SYMBOL(ixp2000_uengine_start_contexts); - -void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask) -{ - u32 mask; - - /* - * Disable the Ready->Executing transition. Note that this - * does not stop the context until it voluntarily yields. - */ - mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); - mask &= ~(ctx_mask << 8); - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); -} -EXPORT_SYMBOL(ixp2000_uengine_stop_contexts); - -static int check_ixp_type(struct ixp2000_uengine_code *c) -{ - u32 product_id; - u32 rev; - - product_id = ixp2000_reg_read(IXP_PRODUCT_ID); - if (((product_id >> 16) & 0x1f) != 0) - return 0; - - switch ((product_id >> 8) & 0xff) { -#ifdef CONFIG_ARCH_IXP2000 - case 0: /* IXP2800 */ - if (!(c->cpu_model_bitmask & 4)) - return 0; - break; - - case 1: /* IXP2850 */ - if (!(c->cpu_model_bitmask & 8)) - return 0; - break; - - case 2: /* IXP2400 */ - if (!(c->cpu_model_bitmask & 2)) - return 0; - break; -#endif - -#ifdef CONFIG_ARCH_IXP23XX - case 4: /* IXP23xx */ - if (!(c->cpu_model_bitmask & 0x3f0)) - return 0; - break; -#endif - - default: - return 0; - } - - rev = product_id & 0xff; - if (rev < c->cpu_min_revision || rev > c->cpu_max_revision) - return 0; - - return 1; -} - -static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) -{ - int offset; - int i; - - offset = 0; - - for (i = 0; i < 128; i++) { - u8 b3; - u8 b2; - u8 b1; - u8 b0; - - b3 = (gpr_a[i] >> 24) & 0xff; - b2 = (gpr_a[i] >> 16) & 0xff; - b1 = (gpr_a[i] >> 8) & 0xff; - b0 = gpr_a[i] & 0xff; - - /* immed[@ai, (b1 << 8) | b0] */ - /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */ - ucode[offset++] = 0xf0; - ucode[offset++] = (b1 >> 4); - ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6); - ucode[offset++] = (b0 << 2); - ucode[offset++] = 0x80 | i; - - /* immed_w1[@ai, (b3 << 8) | b2] */ - /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */ - ucode[offset++] = 0xf4; - ucode[offset++] = 0x40 | (b3 >> 4); - ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6); - ucode[offset++] = (b2 << 2); - ucode[offset++] = 0x80 | i; - } - - for (i = 0; i < 128; i++) { - u8 b3; - u8 b2; - u8 b1; - u8 b0; - - b3 = (gpr_b[i] >> 24) & 0xff; - b2 = (gpr_b[i] >> 16) & 0xff; - b1 = (gpr_b[i] >> 8) & 0xff; - b0 = gpr_b[i] & 0xff; - - /* immed[@bi, (b1 << 8) | b0] */ - /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */ - ucode[offset++] = 0xf0; - ucode[offset++] = (b1 >> 4); - ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6); - ucode[offset++] = (i << 2) | 0x03; - ucode[offset++] = b0; - - /* immed_w1[@bi, (b3 << 8) | b2] */ - /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */ - ucode[offset++] = 0xf4; - ucode[offset++] = 0x40 | (b3 >> 4); - ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6); - ucode[offset++] = (i << 2) | 0x03; - ucode[offset++] = b2; - } - - /* ctx_arb[kill] */ - ucode[offset++] = 0xe0; - ucode[offset++] = 0x00; - ucode[offset++] = 0x01; - ucode[offset++] = 0x00; - ucode[offset++] = 0x00; -} - -static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c) -{ - int per_ctx_regs; - u32 *gpr_a; - u32 *gpr_b; - u8 *ucode; - int i; - - gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL); - gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL); - ucode = kmalloc(513 * 5, GFP_KERNEL); - if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) { - kfree(ucode); - kfree(gpr_b); - kfree(gpr_a); - return 1; - } - - per_ctx_regs = 16; - if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS) - per_ctx_regs = 32; - - for (i = 0; i < 256; i++) { - struct ixp2000_reg_value *r = c->initial_reg_values + i; - u32 *bank; - int inc; - int j; - - if (r->reg == -1) - break; - - bank = (r->reg & 0x400) ? gpr_b : gpr_a; - inc = (r->reg & 0x80) ? 128 : per_ctx_regs; - - j = r->reg & 0x7f; - while (j < 128) { - bank[j] = r->value; - j += inc; - } - } - - generate_ucode(ucode, gpr_a, gpr_b); - ixp2000_uengine_load_microcode(uengine, ucode, 513); - ixp2000_uengine_init_context(uengine, 0, 0); - ixp2000_uengine_start_contexts(uengine, 0x01); - for (i = 0; i < 100; i++) { - u32 status; - - status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS); - if (!(status & 0x80000000)) - break; - } - ixp2000_uengine_stop_contexts(uengine, 0x01); - - kfree(ucode); - kfree(gpr_b); - kfree(gpr_a); - - return !!(i == 100); -} - -int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c) -{ - int ctx; - - if (!check_ixp_type(c)) - return 1; - - if (!(ixp2000_uengine_mask & (1 << uengine))) - return 1; - - ixp2000_uengine_reset(1 << uengine); - ixp2000_uengine_set_mode(uengine, c->uengine_parameters); - if (set_initial_registers(uengine, c)) - return 1; - ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns); - - for (ctx = 0; ctx < 8; ctx++) - ixp2000_uengine_init_context(uengine, ctx, 0); - - return 0; -} -EXPORT_SYMBOL(ixp2000_uengine_load); - - -static int __init ixp2000_uengine_init(void) -{ - int uengine; - u32 value; - - /* - * Determine number of microengines present. - */ - switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) { -#ifdef CONFIG_ARCH_IXP2000 - case 0: /* IXP2800 */ - case 1: /* IXP2850 */ - ixp2000_uengine_mask = 0x00ff00ff; - break; - - case 2: /* IXP2400 */ - ixp2000_uengine_mask = 0x000f000f; - break; -#endif - -#ifdef CONFIG_ARCH_IXP23XX - case 4: /* IXP23xx */ - ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf; - break; -#endif - - default: - printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n", - (unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID)); - ixp2000_uengine_mask = 0x00000000; - break; - } - - /* - * Reset microengines. - */ - ixp2000_uengine_reset(ixp2000_uengine_mask); - - /* - * Synchronise timestamp counters across all microengines. - */ - value = ixp2000_reg_read(IXP_MISC_CONTROL); - ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80); - for (uengine = 0; uengine < 32; uengine++) { - if (ixp2000_uengine_mask & (1 << uengine)) { - ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0); - ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0); - } - } - ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80); - - return 0; -} - -subsys_initcall(ixp2000_uengine_init); diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c index 1171a5010aea..6cb362e56d29 100644 --- a/arch/arm/common/via82c505.c +++ b/arch/arm/common/via82c505.c @@ -51,7 +51,7 @@ via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops via82c505_ops = { +struct pci_ops via82c505_ops = { .read = via82c505_read_config, .write = via82c505_write_config, }; @@ -81,12 +81,3 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys) { return (nr == 0); } - -struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - if (nr == 0) - return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata, - &sysdata->resources); - - return NULL; -} diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 7e288f96cedf..e0d538803cc3 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -39,6 +39,7 @@ * struct vic_device - VIC PM device * @irq: The IRQ number for the base of the VIC. * @base: The register base for the VIC. + * @valid_sources: A bitmask of valid interrupts * @resume_sources: A bitmask of interrupts for resume. * @resume_irqs: The IRQs enabled for resume. * @int_select: Save for VIC_INT_SELECT. @@ -50,6 +51,7 @@ struct vic_device { void __iomem *base; int irq; + u32 valid_sources; u32 resume_sources; u32 resume_irqs; u32 int_select; @@ -164,10 +166,32 @@ static int __init vic_pm_init(void) late_initcall(vic_pm_init); #endif /* CONFIG_PM */ +static struct irq_chip vic_chip; + +static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct vic_device *v = d->host_data; + + /* Skip invalid IRQs, only register handlers for the real ones */ + if (!(v->valid_sources & (1 << hwirq))) + return -ENOTSUPP; + irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); + irq_set_chip_data(irq, v->base); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + return 0; +} + +static struct irq_domain_ops vic_irqdomain_ops = { + .map = vic_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, +}; + /** * vic_register() - Register a VIC. * @base: The base address of the VIC. * @irq: The base IRQ for the VIC. + * @valid_sources: bitmask of valid interrupts * @resume_sources: bitmask of interrupts allowed for resume sources. * @node: The device tree node associated with the VIC. * @@ -178,7 +202,8 @@ late_initcall(vic_pm_init); * This also configures the IRQ domain for the VIC. */ static void __init vic_register(void __iomem *base, unsigned int irq, - u32 resume_sources, struct device_node *node) + u32 valid_sources, u32 resume_sources, + struct device_node *node) { struct vic_device *v; @@ -189,11 +214,12 @@ static void __init vic_register(void __iomem *base, unsigned int irq, v = &vic_devices[vic_id]; v->base = base; + v->valid_sources = valid_sources; v->resume_sources = resume_sources; v->irq = irq; vic_id++; - v->domain = irq_domain_add_legacy(node, 32, irq, 0, - &irq_domain_simple_ops, v); + v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0, + &vic_irqdomain_ops, v); } static void vic_ack_irq(struct irq_data *d) @@ -287,23 +313,6 @@ static void __init vic_clear_interrupts(void __iomem *base) } } -static void __init vic_set_irq_sources(void __iomem *base, - unsigned int irq_start, u32 vic_sources) -{ - unsigned int i; - - for (i = 0; i < 32; i++) { - if (vic_sources & (1 << i)) { - unsigned int irq = irq_start + i; - - irq_set_chip_and_handler(irq, &vic_chip, - handle_level_irq); - irq_set_chip_data(irq, base); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } -} - /* * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. * The original cell has 32 interrupts, while the modified one has 64, @@ -338,8 +347,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, writel(32, base + VIC_PL190_DEF_VECT_ADDR); } - vic_set_irq_sources(base, irq_start, vic_sources); - vic_register(base, irq_start, 0, node); + vic_register(base, irq_start, vic_sources, 0, node); } void __init __vic_init(void __iomem *base, unsigned int irq_start, @@ -379,9 +387,7 @@ void __init __vic_init(void __iomem *base, unsigned int irq_start, vic_init2(base); - vic_set_irq_sources(base, irq_start, vic_sources); - - vic_register(base, irq_start, resume_sources, node); + vic_register(base, irq_start, vic_sources, resume_sources, node); } /** diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig new file mode 100644 index 000000000000..67bc571ed0c3 --- /dev/null +++ b/arch/arm/configs/at91_dt_defconfig @@ -0,0 +1,196 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_AT91=y +CONFIG_SOC_AT91SAM9260=y +CONFIG_SOC_AT91SAM9263=y +CONFIG_SOC_AT91SAM9G45=y +CONFIG_SOC_AT91SAM9X5=y +CONFIG_MACH_AT91SAM_DT=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AT91_TIMER_HZ=128 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_KEXEC=y +CONFIG_AUTO_ZRELADDR=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT_6RD=y +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_ATMEL_PWM=y +CONFIG_ATMEL_TCLIB=y +CONFIG_EEPROM_93CX6=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_MACB=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_DAVICOM_PHY=y +CONFIG_MICREL_PHY=y +# CONFIG_WLAN is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_AT91SAM9X_WATCHDOG=y +CONFIG_SSB=m +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_ATMEL=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_ATMEL_LCDC=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_MINI_4x6=y +CONFIG_LOGO=y +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_GADGET=y +CONFIG_USB_AT91=m +CONFIG_USB_ATMEL_USBA=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_DMADEVICES=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_FANOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=m +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m +CONFIG_AVERAGE=y diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index bbe4e1a1f5d8..d54e2acd3ab1 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig @@ -14,6 +14,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91RM9200=y CONFIG_MACH_ONEARM=y CONFIG_ARCH_AT91RM9200DK=y CONFIG_MACH_AT91RM9200EK=y diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig deleted file mode 100644 index 8405aded97a3..000000000000 --- a/arch/arm/configs/ixp2000_defconfig +++ /dev/null @@ -1,99 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_HOTPLUG is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_IXP2000=y -CONFIG_ARCH_ENP2611=y -CONFIG_ARCH_IXDP2400=y -CONFIG_ARCH_IXDP2800=y -CONFIG_ARCH_IXDP2401=y -CONFIG_ARCH_IXDP2801=y -# CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO is not set -# CONFIG_ARM_THUMB is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_SYN_COOKIES=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_IXP2000=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_EEPROM_LEGACY=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_CS89x0=y -CONFIG_E100=y -CONFIG_ENP2611_MSF_NET=y -CONFIG_WAN=y -CONFIG_HDLC=y -CONFIG_HDLC_RAW=y -CONFIG_HDLC_CISCO=y -CONFIG_HDLC_FR=y -CONFIG_HDLC_PPP=y -CONFIG_DLCI=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=3 -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IXP2000=y -CONFIG_WATCHDOG=y -CONFIG_IXP2000_WATCHDOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_INOTIFY=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig deleted file mode 100644 index 688717612e91..000000000000 --- a/arch/arm/configs/ixp23xx_defconfig +++ /dev/null @@ -1,105 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_IXP23XX=y -CONFIG_MACH_ESPRESSO=y -CONFIG_MACH_IXDP2351=y -CONFIG_MACH_ROADRUNNER=y -# CONFIG_ARM_THUMB is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_SYN_COOKIES=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_EEPROM_LEGACY=y -CONFIG_IDE=y -CONFIG_BLK_DEV_SIIMAGE=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_E100=y -CONFIG_E1000=y -CONFIG_WAN=y -CONFIG_HDLC=y -CONFIG_HDLC_RAW=y -CONFIG_HDLC_CISCO=y -CONFIG_HDLC_FR=y -CONFIG_HDLC_PPP=y -CONFIG_DLCI=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_WATCHDOG=y -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_INOTIFY=y -CONFIG_MSDOS_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig index af278f7a2246..00515ef9782d 100644 --- a/arch/arm/configs/rpc_defconfig +++ b/arch/arm/configs/rpc_defconfig @@ -8,8 +8,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_RPC=y -CONFIG_CPU_ARM610=y -CONFIG_CPU_ARM710=y CONFIG_CPU_SA110=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h new file mode 100644 index 000000000000..ed2e95d46e29 --- /dev/null +++ b/arch/arm/include/asm/arch_timer.h @@ -0,0 +1,19 @@ +#ifndef __ASMARM_ARCH_TIMER_H +#define __ASMARM_ARCH_TIMER_H + +#ifdef CONFIG_ARM_ARCH_TIMER +int arch_timer_of_register(void); +int arch_timer_sched_clock_init(void); +#else +static inline int arch_timer_of_register(void) +{ + return -ENXIO; +} + +static inline int arch_timer_sched_clock_init(void) +{ + return -ENXIO; +} +#endif + +#endif diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index d5d8d5c72682..004c1bc95d2b 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -101,7 +101,7 @@ struct cpu_cache_fns { void (*flush_user_range)(unsigned long, unsigned long, unsigned int); void (*coherent_kern_range)(unsigned long, unsigned long); - void (*coherent_user_range)(unsigned long, unsigned long); + int (*coherent_user_range)(unsigned long, unsigned long); void (*flush_kern_dcache_area)(void *, size_t); void (*dma_map_area)(const void *, size_t, int); @@ -142,7 +142,7 @@ extern void __cpuc_flush_kern_all(void); extern void __cpuc_flush_user_all(void); extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); -extern void __cpuc_coherent_user_range(unsigned long, unsigned long); +extern int __cpuc_coherent_user_range(unsigned long, unsigned long); extern void __cpuc_flush_dcache_area(void *, size_t); /* @@ -249,7 +249,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr * Harvard caches are synchronised for the user space address range. * This is used for the ARM private sys_cacheflush system call. */ -#define flush_cache_user_range(vma,start,end) \ +#define flush_cache_user_range(start,end) \ __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) /* diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index d41d7cbf0ada..7eb18c1d8d6c 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -229,66 +229,19 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, (unsigned long)(n), \ sizeof(*(ptr)))) -#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ - -/* - * Note : ARMv7-M (currently unsupported by Linux) does not support - * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should - * not be allowed to use __cmpxchg64. - */ -static inline unsigned long long __cmpxchg64(volatile void *ptr, - unsigned long long old, - unsigned long long new) -{ - register unsigned long long oldval asm("r0"); - register unsigned long long __old asm("r2") = old; - register unsigned long long __new asm("r4") = new; - unsigned long res; - - do { - asm volatile( - " @ __cmpxchg8\n" - " ldrexd %1, %H1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " teqeq %H1, %H3\n" - " strexdeq %0, %4, %H4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (__old), "r" (__new) - : "memory", "cc"); - } while (res); - - return oldval; -} - -static inline unsigned long long __cmpxchg64_mb(volatile void *ptr, - unsigned long long old, - unsigned long long new) -{ - unsigned long long ret; - - smp_mb(); - ret = __cmpxchg64(ptr, old, new); - smp_mb(); - - return ret; -} - -#define cmpxchg64(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#define cmpxchg64_local(ptr,o,n) \ - ((__typeof__(*(ptr)))__cmpxchg64((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#else /* min ARCH = ARMv6 */ - -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#endif +#define cmpxchg64(ptr, o, n) \ + ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr), \ + atomic64_t, \ + counter), \ + (unsigned long)(o), \ + (unsigned long)(n))) + +#define cmpxchg64_local(ptr, o, n) \ + ((__typeof__(*(ptr)))local64_cmpxchg(container_of((ptr), \ + local64_t, \ + a), \ + (unsigned long)(o), \ + (unsigned long)(n))) #endif /* __LINUX_ARM_ARCH__ >= 6 */ diff --git a/arch/arm/include/asm/cpu.h b/arch/arm/include/asm/cpu.h index 793968173bef..d797223b39d5 100644 --- a/arch/arm/include/asm/cpu.h +++ b/arch/arm/include/asm/cpu.h @@ -16,7 +16,6 @@ struct cpuinfo_arm { struct cpu cpu; #ifdef CONFIG_SMP - struct task_struct *idle; unsigned int loops_per_jiffy; #endif }; diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h index 354d571e8bcc..8cacbcda76da 100644 --- a/arch/arm/include/asm/glue-df.h +++ b/arch/arm/include/asm/glue-df.h @@ -31,14 +31,6 @@ #undef CPU_DABORT_HANDLER #undef MULTI_DABORT -#if defined(CONFIG_CPU_ARM610) -# ifdef CPU_DABORT_HANDLER -# define MULTI_DABORT 1 -# else -# define CPU_DABORT_HANDLER cpu_arm6_data_abort -# endif -#endif - #if defined(CONFIG_CPU_ARM710) # ifdef CPU_DABORT_HANDLER # define MULTI_DABORT 1 diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h index e2be7f142668..ac1dd54724b6 100644 --- a/arch/arm/include/asm/glue-proc.h +++ b/arch/arm/include/asm/glue-proc.h @@ -23,15 +23,6 @@ * CPU_NAME - the prefix for CPU related functions */ -#ifdef CONFIG_CPU_ARM610 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm6 -# endif -#endif - #ifdef CONFIG_CPU_ARM7TDMI # ifdef CPU_NAME # undef MULTI_CPU @@ -41,15 +32,6 @@ # endif #endif -#ifdef CONFIG_CPU_ARM710 -# ifdef CPU_NAME -# undef MULTI_CPU -# define MULTI_CPU -# else -# define CPU_NAME cpu_arm7 -# endif -#endif - #ifdef CONFIG_CPU_ARM720T # ifdef CPU_NAME # undef MULTI_CPU diff --git a/arch/arm/include/asm/hardware/cs89712.h b/arch/arm/include/asm/hardware/cs89712.h deleted file mode 100644 index f75626933e94..000000000000 --- a/arch/arm/include/asm/hardware/cs89712.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/arm/include/asm/hardware/cs89712.h - * - * This file contains the hardware definitions of the CS89712 - * additional internal registers. - * - * Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de> - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_HARDWARE_CS89712_H -#define __ASM_HARDWARE_CS89712_H - -/* -* CS89712 additional registers -*/ - -#define PCDR 0x0002 /* Port C Data register ---------------------------- */ -#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */ -#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/ -#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/ - -#define SDCONF_ACTIVE (1 << 10) -#define SDCONF_CLKCTL (1 << 9) -#define SDCONF_WIDTH_4 (0 << 7) -#define SDCONF_WIDTH_8 (1 << 7) -#define SDCONF_WIDTH_16 (2 << 7) -#define SDCONF_WIDTH_32 (3 << 7) -#define SDCONF_SIZE_16 (0 << 5) -#define SDCONF_SIZE_64 (1 << 5) -#define SDCONF_SIZE_128 (2 << 5) -#define SDCONF_SIZE_256 (3 << 5) -#define SDCONF_CASLAT_2 (2) -#define SDCONF_CASLAT_3 (3) - -#endif /* __ASM_HARDWARE_CS89712_H */ diff --git a/arch/arm/include/asm/hardware/ep7211.h b/arch/arm/include/asm/hardware/ep7211.h deleted file mode 100644 index 654d5f625c49..000000000000 --- a/arch/arm/include/asm/hardware/ep7211.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/include/asm/hardware/ep7211.h - * - * This file contains the hardware definitions of the EP7211 internal - * registers. - * - * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_HARDWARE_EP7211_H -#define __ASM_HARDWARE_EP7211_H - -#include <asm/hardware/clps7111.h> - -/* - * define EP7211_BASE to be the base address of the region - * you want to access. - */ - -#define EP7211_PHYS_BASE (0x80000000) - -/* - * XXX miket@bluemug.com: need to introduce EP7211 registers (those not - * present in 7212) here. - */ - -#endif /* __ASM_HARDWARE_EP7211_H */ diff --git a/arch/arm/include/asm/hardware/ep7212.h b/arch/arm/include/asm/hardware/ep7212.h deleted file mode 100644 index 3b43bbeaf1db..000000000000 --- a/arch/arm/include/asm/hardware/ep7212.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * arch/arm/include/asm/hardware/ep7212.h - * - * This file contains the hardware definitions of the EP7212 internal - * registers. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_HARDWARE_EP7212_H -#define __ASM_HARDWARE_EP7212_H - -/* - * define EP7212_BASE to be the base address of the region - * you want to access. - */ - -#define EP7212_PHYS_BASE (0x80000000) - -#ifndef __ASSEMBLY__ -#define ep_readl(off) __raw_readl(EP7212_BASE + (off)) -#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off)) -#endif - -/* - * These registers are specific to the EP7212 only - */ -#define DAIR 0x2000 -#define DAIR0 0x2040 -#define DAIDR1 0x2080 -#define DAIDR2 0x20c0 -#define DAISR 0x2100 -#define SYSCON3 0x2200 -#define INTSR3 0x2240 -#define INTMR3 0x2280 -#define LEDFLSH 0x22c0 - -#define DAIR_DAIEN (1 << 16) -#define DAIR_ECS (1 << 17) -#define DAIR_LCTM (1 << 19) -#define DAIR_LCRM (1 << 20) -#define DAIR_RCTM (1 << 21) -#define DAIR_RCRM (1 << 22) -#define DAIR_LBM (1 << 23) - -#define DAIDR2_FIFOEN (1 << 15) -#define DAIDR2_FIFOLEFT (0x0d << 16) -#define DAIDR2_FIFORIGHT (0x11 << 16) - -#define DAISR_RCTS (1 << 0) -#define DAISR_RCRS (1 << 1) -#define DAISR_LCTS (1 << 2) -#define DAISR_LCRS (1 << 3) -#define DAISR_RCTU (1 << 4) -#define DAISR_RCRO (1 << 5) -#define DAISR_LCTU (1 << 6) -#define DAISR_LCRO (1 << 7) -#define DAISR_RCNF (1 << 8) -#define DAISR_RCNE (1 << 9) -#define DAISR_LCNF (1 << 10) -#define DAISR_LCNE (1 << 11) -#define DAISR_FIFO (1 << 12) - -#define SYSCON3_ADCCON (1 << 0) -#define SYSCON3_DAISEL (1 << 3) -#define SYSCON3_ADCCKNSEN (1 << 4) -#define SYSCON3_FASTWAKE (1 << 8) -#define SYSCON3_DAIEN (1 << 9) - -#endif /* __ASM_HARDWARE_EP7212_H */ diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h index 73f84fa4f366..d36a73d7c0e8 100644 --- a/arch/arm/include/asm/hardware/it8152.h +++ b/arch/arm/include/asm/hardware/it8152.h @@ -110,6 +110,6 @@ extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc); extern void it8152_init_irq(void); extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); extern int it8152_pci_setup(int nr, struct pci_sys_data *sys); -extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys); +extern struct pci_ops it8152_ops; #endif /* __ASM_HARDWARE_IT8152_H */ diff --git a/arch/arm/include/asm/hardware/uengine.h b/arch/arm/include/asm/hardware/uengine.h deleted file mode 100644 index b442d65c6593..000000000000 --- a/arch/arm/include/asm/hardware/uengine.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Generic library functions for the microengines found on the Intel - * IXP2000 series of network processors. - * - * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> - * Dedicated to Marija Kulikova. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of the - * License, or (at your option) any later version. - */ - -#ifndef __IXP2000_UENGINE_H -#define __IXP2000_UENGINE_H - -extern u32 ixp2000_uengine_mask; - -struct ixp2000_uengine_code -{ - u32 cpu_model_bitmask; - u8 cpu_min_revision; - u8 cpu_max_revision; - - u32 uengine_parameters; - - struct ixp2000_reg_value { - int reg; - u32 value; - } *initial_reg_values; - - int num_insns; - u8 *insns; -}; - -u32 ixp2000_uengine_csr_read(int uengine, int offset); -void ixp2000_uengine_csr_write(int uengine, int offset, u32 value); -void ixp2000_uengine_reset(u32 uengine_mask); -void ixp2000_uengine_set_mode(int uengine, u32 mode); -void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns); -void ixp2000_uengine_init_context(int uengine, int context, int pc); -void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask); -void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask); -int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c); - -#define IXP2000_UENGINE_8_CONTEXTS 0x00000000 -#define IXP2000_UENGINE_4_CONTEXTS 0x80000000 -#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000 -#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000 -#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000 -#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000 -#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000 -#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000 -#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000 -#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000 - - -#endif diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index d943b7d20f11..26c511fddf8f 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -12,13 +12,14 @@ #define __ASM_MACH_PCI_H struct pci_sys_data; +struct pci_ops; struct pci_bus; struct hw_pci { #ifdef CONFIG_PCI_DOMAINS int domain; #endif - struct list_head buses; + struct pci_ops *ops; int nr_controllers; int (*setup)(int nr, struct pci_sys_data *); struct pci_bus *(*scan)(int nr, struct pci_sys_data *); @@ -45,16 +46,10 @@ struct pci_sys_data { u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ int (*map_irq)(const struct pci_dev *, u8, u8); - struct hw_pci *hw; void *private_data; /* platform controller private data */ }; /* - * This is the standard PCI-PCI bridge swizzling algorithm. - */ -#define pci_std_swizzle pci_common_swizzle - -/* * Call this with your hw_pci struct to initialise the PCI system. */ void pci_common_init(struct hw_pci *); @@ -62,22 +57,22 @@ void pci_common_init(struct hw_pci *); /* * PCI controllers */ +extern struct pci_ops iop3xx_ops; extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); extern void iop3xx_pci_preinit(void); extern void iop3xx_pci_preinit_cond(void); +extern struct pci_ops dc21285_ops; extern int dc21285_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); extern void dc21285_preinit(void); extern void dc21285_postinit(void); +extern struct pci_ops via82c505_ops; extern int via82c505_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *); extern void via82c505_init(void *sysdata); +extern struct pci_ops pci_v3_ops; extern int pci_v3_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *); extern void pci_v3_preinit(void); extern void pci_v3_postinit(void); diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index f73c908b7fa0..6ca945f534ab 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -42,4 +42,9 @@ struct sys_timer { extern void timer_tick(void); +struct timespec; +typedef void (*clock_access_fn)(struct timespec *); +extern int register_persistent_clock(clock_access_fn read_boot, + clock_access_fn read_persistent); + #endif diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index b8e580a297e4..14965658a923 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -34,11 +34,4 @@ typedef struct { #endif -/* - * switch_mm() may do a full cache flush over the context switch, - * so enable interrupts over the context switch to avoid high - * latency. - */ -#define __ARCH_WANT_INTERRUPTS_ON_CTXSW - #endif diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index a0b3cac0547c..0306bc642c0d 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -43,45 +43,104 @@ void __check_kvm_seq(struct mm_struct *mm); #define ASID_FIRST_VERSION (1 << ASID_BITS) extern unsigned int cpu_last_asid; -#ifdef CONFIG_SMP -DECLARE_PER_CPU(struct mm_struct *, current_mm); -#endif void __init_new_context(struct task_struct *tsk, struct mm_struct *mm); void __new_context(struct mm_struct *mm); +void cpu_set_reserved_ttbr0(void); -static inline void check_context(struct mm_struct *mm) +static inline void switch_new_context(struct mm_struct *mm) { - /* - * This code is executed with interrupts enabled. Therefore, - * mm->context.id cannot be updated to the latest ASID version - * on a different CPU (and condition below not triggered) - * without first getting an IPI to reset the context. The - * alternative is to take a read_lock on mm->context.id_lock - * (after changing its type to rwlock_t). - */ - if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) - __new_context(mm); + unsigned long flags; + + __new_context(mm); + + local_irq_save(flags); + cpu_switch_mm(mm->pgd, mm); + local_irq_restore(flags); +} +static inline void check_and_switch_context(struct mm_struct *mm, + struct task_struct *tsk) +{ if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) __check_kvm_seq(mm); + + /* + * Required during context switch to avoid speculative page table + * walking with the wrong TTBR. + */ + cpu_set_reserved_ttbr0(); + + if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) + /* + * The ASID is from the current generation, just switch to the + * new pgd. This condition is only true for calls from + * context_switch() and interrupts are already disabled. + */ + cpu_switch_mm(mm->pgd, mm); + else if (irqs_disabled()) + /* + * Defer the new ASID allocation until after the context + * switch critical region since __new_context() cannot be + * called with interrupts disabled (it sends IPIs). + */ + set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM); + else + /* + * That is a direct call to switch_mm() or activate_mm() with + * interrupts enabled and a new context. + */ + switch_new_context(mm); } #define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0) -#else - -static inline void check_context(struct mm_struct *mm) +#define finish_arch_post_lock_switch \ + finish_arch_post_lock_switch +static inline void finish_arch_post_lock_switch(void) { + if (test_and_clear_thread_flag(TIF_SWITCH_MM)) + switch_new_context(current->mm); +} + +#else /* !CONFIG_CPU_HAS_ASID */ + #ifdef CONFIG_MMU + +static inline void check_and_switch_context(struct mm_struct *mm, + struct task_struct *tsk) +{ if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq)) __check_kvm_seq(mm); -#endif + + if (irqs_disabled()) + /* + * cpu_switch_mm() needs to flush the VIVT caches. To avoid + * high interrupt latencies, defer the call and continue + * running with the old mm. Since we only support UP systems + * on non-ASID CPUs, the old mm will remain valid until the + * finish_arch_post_lock_switch() call. + */ + set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM); + else + cpu_switch_mm(mm->pgd, mm); } +#define finish_arch_post_lock_switch \ + finish_arch_post_lock_switch +static inline void finish_arch_post_lock_switch(void) +{ + if (test_and_clear_thread_flag(TIF_SWITCH_MM)) { + struct mm_struct *mm = current->mm; + cpu_switch_mm(mm->pgd, mm); + } +} + +#endif /* CONFIG_MMU */ + #define init_new_context(tsk,mm) 0 -#endif +#endif /* CONFIG_CPU_HAS_ASID */ #define destroy_context(mm) do { } while(0) @@ -119,12 +178,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, __flush_icache_all(); #endif if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) { -#ifdef CONFIG_SMP - struct mm_struct **crt_mm = &per_cpu(current_mm, cpu); - *crt_mm = next; -#endif - check_context(next); - cpu_switch_mm(next->pgd, next); + check_and_switch_context(next, tsk); if (cache_is_vivt()) cpumask_clear_cpu(cpu, mm_cpumask(prev)); } diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index 5838361c48b3..ecf901902e44 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -34,7 +34,6 @@ * processor(s) we're building for. * * We have the following to choose from: - * v3 - ARMv3 * v4wt - ARMv4 with writethrough cache, without minicache * v4wb - ARMv4 with writeback cache, without minicache * v4_mc - ARMv4 with minicache @@ -44,14 +43,6 @@ #undef _USER #undef MULTI_USER -#ifdef CONFIG_CPU_COPY_V3 -# ifdef _USER -# define MULTI_USER 1 -# else -# define _USER v3 -# endif -#endif - #ifdef CONFIG_CPU_COPY_V4WT # ifdef _USER # define MULTI_USER 1 diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 759af70f9a0a..b24903549d1c 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -69,8 +69,6 @@ */ #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Valid */ #define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ -#define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ -#define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 5ac8d3d3e025..d7038fa22343 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -88,8 +88,6 @@ unsigned long get_wchan(struct task_struct *p); #define cpu_relax() barrier() #endif -void cpu_idle_wait(void); - /* * Create a new kernel thread */ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 451808ba1211..355ece523f41 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -249,6 +249,11 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) return regs->ARM_sp; } +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return regs->ARM_sp; +} + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h new file mode 100644 index 000000000000..c334a23ddf75 --- /dev/null +++ b/arch/arm/include/asm/syscall.h @@ -0,0 +1,93 @@ +/* + * Access to user system call parameters and results + * + * See asm-generic/syscall.h for descriptions of what we must do here. + */ + +#ifndef _ASM_ARM_SYSCALL_H +#define _ASM_ARM_SYSCALL_H + +#include <linux/err.h> + +extern const unsigned long sys_call_table[]; + +static inline int syscall_get_nr(struct task_struct *task, + struct pt_regs *regs) +{ + return task_thread_info(task)->syscall; +} + +static inline void syscall_rollback(struct task_struct *task, + struct pt_regs *regs) +{ + regs->ARM_r0 = regs->ARM_ORIG_r0; +} + +static inline long syscall_get_error(struct task_struct *task, + struct pt_regs *regs) +{ + unsigned long error = regs->ARM_r0; + return IS_ERR_VALUE(error) ? error : 0; +} + +static inline long syscall_get_return_value(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->ARM_r0; +} + +static inline void syscall_set_return_value(struct task_struct *task, + struct pt_regs *regs, + int error, long val) +{ + regs->ARM_r0 = (long) error ? error : val; +} + +#define SYSCALL_MAX_ARGS 7 + +static inline void syscall_get_arguments(struct task_struct *task, + struct pt_regs *regs, + unsigned int i, unsigned int n, + unsigned long *args) +{ + if (i + n > SYSCALL_MAX_ARGS) { + unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i; + unsigned int n_bad = n + i - SYSCALL_MAX_ARGS; + pr_warning("%s called with max args %d, handling only %d\n", + __func__, i + n, SYSCALL_MAX_ARGS); + memset(args_bad, 0, n_bad * sizeof(args[0])); + n = SYSCALL_MAX_ARGS - i; + } + + if (i == 0) { + args[0] = regs->ARM_ORIG_r0; + args++; + i++; + n--; + } + + memcpy(args, ®s->ARM_r0 + i, n * sizeof(args[0])); +} + +static inline void syscall_set_arguments(struct task_struct *task, + struct pt_regs *regs, + unsigned int i, unsigned int n, + const unsigned long *args) +{ + if (i + n > SYSCALL_MAX_ARGS) { + pr_warning("%s called with max args %d, handling only %d\n", + __func__, i + n, SYSCALL_MAX_ARGS); + n = SYSCALL_MAX_ARGS - i; + } + + if (i == 0) { + regs->ARM_ORIG_r0 = args[0]; + args++; + i++; + n--; + } + + memcpy(®s->ARM_r0 + i, args, n * sizeof(args[0])); +} + +#endif /* _ASM_ARM_SYSCALL_H */ diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 0f04d84582e1..68388eb4946b 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -153,6 +153,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *, #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_RESTORE_SIGMASK 20 #define TIF_SECCOMP 21 +#define TIF_SWITCH_MM 22 /* deferred switch_mm */ #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 85fe61e73202..6e924d3a77eb 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -65,21 +65,6 @@ #define MULTI_TLB 1 #endif -#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE) - -#ifdef CONFIG_CPU_TLB_V3 -# define v3_possible_flags v3_tlb_flags -# define v3_always_flags v3_tlb_flags -# ifdef _TLB -# define MULTI_TLB 1 -# else -# define _TLB v3 -# endif -#else -# define v3_possible_flags 0 -# define v3_always_flags (-1UL) -#endif - #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE) #ifdef CONFIG_CPU_TLB_V4WT @@ -298,8 +283,7 @@ extern struct cpu_tlb_fns cpu_tlb; * implemented the "%?" method, but this has been discontinued due to too * many people getting it wrong. */ -#define possible_tlb_flags (v3_possible_flags | \ - v4_possible_flags | \ +#define possible_tlb_flags (v4_possible_flags | \ v4wbi_possible_flags | \ fr_possible_flags | \ v4wb_possible_flags | \ @@ -307,8 +291,7 @@ extern struct cpu_tlb_fns cpu_tlb; v6wbi_possible_flags | \ v7wbi_possible_flags) -#define always_tlb_flags (v3_always_flags & \ - v4_always_flags & \ +#define always_tlb_flags (v4_always_flags & \ v4wbi_always_flags & \ fr_always_flags & \ v4wb_always_flags & \ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 7b787d642af4..7ad2d5cf7008 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o +obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o @@ -81,4 +82,4 @@ head-y := head$(MMUEXT).o obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -extra-y := $(head-y) init_task.o vmlinux.lds +extra-y := $(head-y) vmlinux.lds diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c new file mode 100644 index 000000000000..dd58035621f7 --- /dev/null +++ b/arch/arm/kernel/arch_timer.c @@ -0,0 +1,350 @@ +/* + * linux/arch/arm/kernel/arch_timer.c + * + * Copyright (C) 2011 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/smp.h> +#include <linux/cpu.h> +#include <linux/jiffies.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/of_irq.h> +#include <linux/io.h> + +#include <asm/cputype.h> +#include <asm/localtimer.h> +#include <asm/arch_timer.h> +#include <asm/system_info.h> +#include <asm/sched_clock.h> + +static unsigned long arch_timer_rate; +static int arch_timer_ppi; +static int arch_timer_ppi2; + +static struct clock_event_device __percpu **arch_timer_evt; + +/* + * Architected system timer support. + */ + +#define ARCH_TIMER_CTRL_ENABLE (1 << 0) +#define ARCH_TIMER_CTRL_IT_MASK (1 << 1) +#define ARCH_TIMER_CTRL_IT_STAT (1 << 2) + +#define ARCH_TIMER_REG_CTRL 0 +#define ARCH_TIMER_REG_FREQ 1 +#define ARCH_TIMER_REG_TVAL 2 + +static void arch_timer_reg_write(int reg, u32 val) +{ + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); + break; + } + + isb(); +} + +static u32 arch_timer_reg_read(int reg) +{ + u32 val; + + switch (reg) { + case ARCH_TIMER_REG_CTRL: + asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); + break; + case ARCH_TIMER_REG_FREQ: + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); + break; + case ARCH_TIMER_REG_TVAL: + asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); + break; + default: + BUG(); + } + + return val; +} + +static irqreturn_t arch_timer_handler(int irq, void *dev_id) +{ + struct clock_event_device *evt = *(struct clock_event_device **)dev_id; + unsigned long ctrl; + + ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); + if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { + ctrl |= ARCH_TIMER_CTRL_IT_MASK; + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + evt->event_handler(evt); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static void arch_timer_disable(void) +{ + unsigned long ctrl; + + ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); +} + +static void arch_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + switch (mode) { + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + arch_timer_disable(); + break; + default: + break; + } +} + +static int arch_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl; + + ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); + ctrl |= ARCH_TIMER_CTRL_ENABLE; + ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; + + arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + + return 0; +} + +static int __cpuinit arch_timer_setup(struct clock_event_device *clk) +{ + /* Be safe... */ + arch_timer_disable(); + + clk->features = CLOCK_EVT_FEAT_ONESHOT; + clk->name = "arch_sys_timer"; + clk->rating = 450; + clk->set_mode = arch_timer_set_mode; + clk->set_next_event = arch_timer_set_next_event; + clk->irq = arch_timer_ppi; + + clockevents_config_and_register(clk, arch_timer_rate, + 0xf, 0x7fffffff); + + *__this_cpu_ptr(arch_timer_evt) = clk; + + enable_percpu_irq(clk->irq, 0); + if (arch_timer_ppi2) + enable_percpu_irq(arch_timer_ppi2, 0); + + return 0; +} + +/* Is the optional system timer available? */ +static int local_timer_is_architected(void) +{ + return (cpu_architecture() >= CPU_ARCH_ARMv7) && + ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1; +} + +static int arch_timer_available(void) +{ + unsigned long freq; + + if (!local_timer_is_architected()) + return -ENXIO; + + if (arch_timer_rate == 0) { + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0); + freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ); + + /* Check the timer frequency. */ + if (freq == 0) { + pr_warn("Architected timer frequency not available\n"); + return -EINVAL; + } + + arch_timer_rate = freq; + } + + pr_info_once("Architected local timer running at %lu.%02luMHz.\n", + arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100); + return 0; +} + +static inline cycle_t arch_counter_get_cntpct(void) +{ + u32 cvall, cvalh; + + asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); + + return ((cycle_t) cvalh << 32) | cvall; +} + +static inline cycle_t arch_counter_get_cntvct(void) +{ + u32 cvall, cvalh; + + asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh)); + + return ((cycle_t) cvalh << 32) | cvall; +} + +static u32 notrace arch_counter_get_cntvct32(void) +{ + cycle_t cntvct = arch_counter_get_cntvct(); + + /* + * The sched_clock infrastructure only knows about counters + * with at most 32bits. Forget about the upper 24 bits for the + * time being... + */ + return (u32)(cntvct & (u32)~0); +} + +static cycle_t arch_counter_read(struct clocksource *cs) +{ + return arch_counter_get_cntpct(); +} + +static struct clocksource clocksource_counter = { + .name = "arch_sys_counter", + .rating = 400, + .read = arch_counter_read, + .mask = CLOCKSOURCE_MASK(56), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __cpuinit arch_timer_stop(struct clock_event_device *clk) +{ + pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", + clk->irq, smp_processor_id()); + disable_percpu_irq(clk->irq); + if (arch_timer_ppi2) + disable_percpu_irq(arch_timer_ppi2); + arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk); +} + +static struct local_timer_ops arch_timer_ops __cpuinitdata = { + .setup = arch_timer_setup, + .stop = arch_timer_stop, +}; + +static struct clock_event_device arch_timer_global_evt; + +static int __init arch_timer_register(void) +{ + int err; + + err = arch_timer_available(); + if (err) + return err; + + arch_timer_evt = alloc_percpu(struct clock_event_device *); + if (!arch_timer_evt) + return -ENOMEM; + + clocksource_register_hz(&clocksource_counter, arch_timer_rate); + + err = request_percpu_irq(arch_timer_ppi, arch_timer_handler, + "arch_timer", arch_timer_evt); + if (err) { + pr_err("arch_timer: can't register interrupt %d (%d)\n", + arch_timer_ppi, err); + goto out_free; + } + + if (arch_timer_ppi2) { + err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler, + "arch_timer", arch_timer_evt); + if (err) { + pr_err("arch_timer: can't register interrupt %d (%d)\n", + arch_timer_ppi2, err); + arch_timer_ppi2 = 0; + goto out_free_irq; + } + } + + err = local_timer_register(&arch_timer_ops); + if (err) { + /* + * We couldn't register as a local timer (could be + * because we're on a UP platform, or because some + * other local timer is already present...). Try as a + * global timer instead. + */ + arch_timer_global_evt.cpumask = cpumask_of(0); + err = arch_timer_setup(&arch_timer_global_evt); + } + + if (err) + goto out_free_irq; + + return 0; + +out_free_irq: + free_percpu_irq(arch_timer_ppi, arch_timer_evt); + if (arch_timer_ppi2) + free_percpu_irq(arch_timer_ppi2, arch_timer_evt); + +out_free: + free_percpu(arch_timer_evt); + + return err; +} + +static const struct of_device_id arch_timer_of_match[] __initconst = { + { .compatible = "arm,armv7-timer", }, + {}, +}; + +int __init arch_timer_of_register(void) +{ + struct device_node *np; + u32 freq; + + np = of_find_matching_node(NULL, arch_timer_of_match); + if (!np) { + pr_err("arch_timer: can't find DT node\n"); + return -ENODEV; + } + + /* Try to determine the frequency from the device tree or CNTFRQ */ + if (!of_property_read_u32(np, "clock-frequency", &freq)) + arch_timer_rate = freq; + + arch_timer_ppi = irq_of_parse_and_map(np, 0); + arch_timer_ppi2 = irq_of_parse_and_map(np, 1); + pr_info("arch_timer: found %s irqs %d %d\n", + np->name, arch_timer_ppi, arch_timer_ppi2); + + return arch_timer_register(); +} + +int __init arch_timer_sched_clock_init(void) +{ + int err; + + err = arch_timer_available(); + if (err) + return err; + + setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate); + return 0; +} diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index ede5f7741c42..25552508c3fd 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -374,16 +374,29 @@ EXPORT_SYMBOL(pcibios_fixup_bus); #endif /* - * Swizzle the device pin each time we cross a bridge. - * This might update pin and returns the slot number. + * Swizzle the device pin each time we cross a bridge. If a platform does + * not provide a swizzle function, we perform the standard PCI swizzling. + * + * The default swizzling walks up the bus tree one level at a time, applying + * the standard swizzle function at each step, stopping when it finds the PCI + * root bus. This will return the slot number of the bridge device on the + * root bus and the interrupt pin on that device which should correspond + * with the downstream device interrupt. + * + * Platforms may override this, in which case the slot and pin returned + * depend entirely on the platform code. However, please note that the + * PCI standard swizzle is implemented on plug-in cards and Cardbus based + * PCI extenders, so it can not be ignored. */ static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin) { struct pci_sys_data *sys = dev->sysdata; - int slot = 0, oldpin = *pin; + int slot, oldpin = *pin; if (sys->swizzle) slot = sys->swizzle(dev, pin); + else + slot = pci_common_swizzle(dev, pin); if (debug_pci) printk("PCI: %s swizzling pin %d => pin %d slot %d\n", @@ -410,7 +423,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static void __init pcibios_init_hw(struct hw_pci *hw) +static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; int ret; @@ -424,7 +437,6 @@ static void __init pcibios_init_hw(struct hw_pci *hw) #ifdef CONFIG_PCI_DOMAINS sys->domain = hw->domain; #endif - sys->hw = hw; sys->busnr = busnr; sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; @@ -440,14 +452,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw) &iomem_resource, sys->mem_offset); } - sys->bus = hw->scan(nr, sys); + if (hw->scan) + sys->bus = hw->scan(nr, sys); + else + sys->bus = pci_scan_root_bus(NULL, sys->busnr, + hw->ops, sys, &sys->resources); if (!sys->bus) panic("PCI: unable to scan bus!"); busnr = sys->bus->subordinate + 1; - list_add(&sys->node, &hw->buses); + list_add(&sys->node, head); } else { kfree(sys); if (ret < 0) @@ -459,19 +475,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw) void __init pci_common_init(struct hw_pci *hw) { struct pci_sys_data *sys; - - INIT_LIST_HEAD(&hw->buses); + LIST_HEAD(head); pci_add_flags(PCI_REASSIGN_ALL_RSRC); if (hw->preinit) hw->preinit(); - pcibios_init_hw(hw); + pcibios_init_hw(hw, &head); if (hw->postinit) hw->postinit(); pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); - list_for_each_entry(sys, &hw->buses, node) { + list_for_each_entry(sys, &head, node) { struct pci_bus *bus = sys->bus; if (!pci_has_flag(PCI_PROBE_ONLY)) { diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 7fd3ad048da9..437f0c426517 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -556,10 +556,6 @@ call_fpe: #endif tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 -#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) - and r8, r0, #0x0f000000 @ mask out op-code bits - teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? -#endif moveq pc, lr get_thread_info r10 @ get current thread and r8, r0, #0x00000f00 @ mask out CP number diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 54ee265dd819..7bd2d3cb8957 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -335,20 +335,6 @@ ENDPROC(ftrace_stub) *----------------------------------------------------------------------------- */ - /* If we're optimising for StrongARM the resulting code won't - run on an ARM7 and we can save a couple of instructions. - --pb */ -#ifdef CONFIG_CPU_ARM710 -#define A710(code...) code -.Larm710bug: - ldmia sp, {r0 - lr}^ @ Get calling r0 - lr - mov r0, r0 - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 -#else -#define A710(code...) -#endif - .align 5 ENTRY(vector_swi) sub sp, sp, #S_FRAME_SIZE @@ -379,9 +365,6 @@ ENTRY(vector_swi) ldreq r10, [lr, #-4] @ get SWI instruction #else ldr r10, [lr, #-4] @ get SWI instruction - A710( and ip, r10, #0x0f000000 @ check for SWI ) - A710( teq ip, #0x0f000000 ) - A710( bne .Larm710bug ) #endif #ifdef CONFIG_CPU_ENDIAN_BE8 rev r10, r10 @ little endian instruction @@ -392,26 +375,15 @@ ENTRY(vector_swi) /* * Pure EABI user space always put syscall number into scno (r7). */ - A710( ldr ip, [lr, #-4] @ get SWI instruction ) - A710( and ip, ip, #0x0f000000 @ check for SWI ) - A710( teq ip, #0x0f000000 ) - A710( bne .Larm710bug ) - #elif defined(CONFIG_ARM_THUMB) - /* Legacy ABI only, possibly thumb mode. */ tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs addne scno, r7, #__NR_SYSCALL_BASE @ put OS number in ldreq scno, [lr, #-4] #else - /* Legacy ABI only. */ ldr scno, [lr, #-4] @ get SWI instruction - A710( and ip, scno, #0x0f000000 @ check for SWI ) - A710( teq ip, #0x0f000000 ) - A710( bne .Larm710bug ) - #endif #ifdef CONFIG_ALIGNMENT_TRAP diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 3bf0c7f8b043..835898e7d704 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -277,10 +277,6 @@ __create_page_tables: mov r3, r3, lsl #PMD_ORDER add r0, r4, r3 - rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) - cmp r3, #0x0800 @ limit to 512MB - movhi r3, #0x0800 - add r6, r0, r3 mov r3, r7, lsr #SECTION_SHIFT ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags orr r3, r7, r3, lsl #SECTION_SHIFT @@ -289,13 +285,10 @@ __create_page_tables: #else orr r3, r3, #PMD_SECT_XN #endif -1: str r3, [r0], #4 + str r3, [r0], #4 #ifdef CONFIG_ARM_LPAE str r7, [r0], #4 #endif - add r3, r3, #1 << SECTION_SHIFT - cmp r0, r6 - blo 1b #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ /* we don't need any serial debugging mappings */ diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c deleted file mode 100644 index e7cbb50dc356..000000000000 --- a/arch/arm/kernel/init_task.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * linux/arch/arm/kernel/init_task.c - */ -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/fs.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/init_task.h> -#include <linux/mqueue.h> -#include <linux/uaccess.h> - -#include <asm/pgtable.h> - -static struct signal_struct init_signals = INIT_SIGNALS(init_signals); -static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); -/* - * Initial thread structure. - * - * We need to make sure that this is 8192-byte aligned due to the - * way process stacks are handled. This is done by making sure - * the linker maps this in the .text segment right after head.S, - * and making head.S ensure the proper alignment. - * - * The things we do for performance.. - */ -union thread_union init_thread_union __init_task_data = - { INIT_THREAD_INFO(init_task) }; - -/* - * Initial task structure. - * - * All other task structs will be allocated on slabs in fork.c - */ -struct task_struct init_task = INIT_TASK(init_task); - -EXPORT_SYMBOL(init_task); diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 2b7b017a20cd..19c95ea65b2f 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -157,26 +157,6 @@ EXPORT_SYMBOL(pm_power_off); void (*arm_pm_restart)(char str, const char *cmd) = null_restart; EXPORT_SYMBOL_GPL(arm_pm_restart); -static void do_nothing(void *unused) -{ -} - -/* - * cpu_idle_wait - Used to ensure that all the CPUs discard old value of - * pm_idle and update to new pm_idle value. Required while changing pm_idle - * handler on SMP systems. - * - * Caller must have changed pm_idle to the new value before the call. Old - * pm_idle value will not be used by any CPU after the return of this function. - */ -void cpu_idle_wait(void) -{ - smp_mb(); - /* kick all the CPUs so that they exit out of pm_idle */ - smp_call_function(do_nothing, NULL, 1); -} -EXPORT_SYMBOL_GPL(cpu_idle_wait); - /* * This is our default idle handler. */ diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 80abafb9bf33..14e38261cd31 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -24,6 +24,7 @@ #include <linux/hw_breakpoint.h> #include <linux/regset.h> #include <linux/audit.h> +#include <linux/tracehook.h> #include <asm/pgtable.h> #include <asm/traps.h> @@ -906,49 +907,33 @@ long arch_ptrace(struct task_struct *child, long request, return ret; } -#ifdef __ARMEB__ -#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB -#else -#define AUDIT_ARCH_NR AUDIT_ARCH_ARM -#endif - asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) { unsigned long ip; - /* - * Save IP. IP is used to denote syscall entry/exit: - * IP = 0 -> entry, = 1 -> exit - */ - ip = regs->ARM_ip; - regs->ARM_ip = why; - - if (!ip) + if (why) audit_syscall_exit(regs); else - audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0, + audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); if (!test_thread_flag(TIF_SYSCALL_TRACE)) return scno; - if (!(current->ptrace & PT_PTRACED)) - return scno; current_thread_info()->syscall = scno; - /* the 0x80 provides a way for the tracing parent to distinguish - between a syscall stop and SIGTRAP delivery */ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) - ? 0x80 : 0)); /* - * this isn't the same as continuing with a signal, but it will do - * for normal use. strace only continues with a signal if the - * stopping signal is not SIGTRAP. -brl + * IP is used to denote syscall entry/exit: + * IP = 0 -> entry, =1 -> exit */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } + ip = regs->ARM_ip; + regs->ARM_ip = why; + + if (why) + tracehook_report_syscall_exit(regs, 0); + else if (tracehook_report_syscall_entry(regs)) + current_thread_info()->syscall = -1; + regs->ARM_ip = ip; return current_thread_info()->syscall; diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index d68d1b694680..73d9a420850d 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -589,6 +589,8 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, */ block_sigmask(ka, sig); + tracehook_signal_handler(sig, info, ka, regs, 0); + return 0; } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index f6a4d32b0421..b735521a4a54 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -60,32 +60,11 @@ enum ipi_msg_type { static DECLARE_COMPLETION(cpu_running); -int __cpuinit __cpu_up(unsigned int cpu) +int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) { - struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu); - struct task_struct *idle = ci->idle; int ret; /* - * Spawn a new process manually, if not already done. - * Grab a pointer to its task struct so we can mess with it - */ - if (!idle) { - idle = fork_idle(cpu); - if (IS_ERR(idle)) { - printk(KERN_ERR "CPU%u: fork() failed\n", cpu); - return PTR_ERR(idle); - } - ci->idle = idle; - } else { - /* - * Since this idle thread is being re-used, call - * init_idle() to reinitialize the thread structure. - */ - init_idle(idle, cpu); - } - - /* * We need to tell the secondary core where to find * its stack and the page tables. */ @@ -251,8 +230,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void) struct mm_struct *mm = &init_mm; unsigned int cpu = smp_processor_id(); - printk("CPU%u: Booted secondary processor\n", cpu); - /* * All kernel threads share the same mm context; grab a * reference and switch to it. @@ -264,6 +241,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) enter_lazy_tlb(mm, current); local_flush_tlb_all(); + printk("CPU%u: Booted secondary processor\n", cpu); + cpu_init(); preempt_disable(); trace_hardirqs_off(); @@ -318,9 +297,6 @@ void __init smp_cpus_done(unsigned int max_cpus) void __init smp_prepare_boot_cpu(void) { - unsigned int cpu = smp_processor_id(); - - per_cpu(cpu_data, cpu).idle = current; } void __init smp_prepare_cpus(unsigned int max_cpus) @@ -454,6 +430,9 @@ static struct local_timer_ops *lt_ops; #ifdef CONFIG_LOCAL_TIMERS int local_timer_register(struct local_timer_ops *ops) { + if (!is_smp() || !setup_max_cpus) + return -ENXIO; + if (lt_ops) return -EBUSY; diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 8f5dd7963356..b9f015e843d8 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/io.h> +#include <asm/smp_plat.h> #include <asm/smp_scu.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -74,7 +75,7 @@ void scu_enable(void __iomem *scu_base) int scu_power_mode(void __iomem *scu_base, unsigned int mode) { unsigned int val; - int cpu = smp_processor_id(); + int cpu = cpu_logical_map(smp_processor_id()); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index d2b177905cdb..76cbb055dd05 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -115,7 +115,7 @@ int kernel_execve(const char *filename, "Ir" (THREAD_START_SP - sizeof(regs)), "r" (®s), "Ir" (sizeof(regs)) - : "r0", "r1", "r2", "r3", "ip", "lr", "memory"); + : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory"); out: return ret; diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c index aab899764053..7b8403b76666 100644 --- a/arch/arm/kernel/thumbee.c +++ b/arch/arm/kernel/thumbee.c @@ -20,6 +20,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <asm/cputype.h> #include <asm/system_info.h> #include <asm/thread_notify.h> @@ -67,8 +68,7 @@ static int __init thumbee_init(void) if (cpu_arch < CPU_ARCH_ARMv7) return 0; - /* processor feature register 0 */ - asm("mrc p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0)); + pfr0 = read_cpuid_ext(CPUID_EXT_PFR0); if ((pfr0 & 0x0000f000) != 0x00001000) return 0; diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index fe31b22f18fd..af2afb019672 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -110,6 +110,42 @@ void timer_tick(void) } #endif +static void dummy_clock_access(struct timespec *ts) +{ + ts->tv_sec = 0; + ts->tv_nsec = 0; +} + +static clock_access_fn __read_persistent_clock = dummy_clock_access; +static clock_access_fn __read_boot_clock = dummy_clock_access;; + +void read_persistent_clock(struct timespec *ts) +{ + __read_persistent_clock(ts); +} + +void read_boot_clock(struct timespec *ts) +{ + __read_boot_clock(ts); +} + +int __init register_persistent_clock(clock_access_fn read_boot, + clock_access_fn read_persistent) +{ + /* Only allow the clockaccess functions to be registered once */ + if (__read_persistent_clock == dummy_clock_access && + __read_boot_clock == dummy_clock_access) { + if (read_boot) + __read_boot_clock = read_boot; + if (read_persistent) + __read_persistent_clock = read_persistent; + + return 0; + } + + return -EINVAL; +} + #if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS) static int timer_suspend(void) { diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 778454750a6c..3647170e9a16 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -479,14 +479,14 @@ static int bad_syscall(int n, struct pt_regs *regs) return regs->ARM_r0; } -static inline void +static inline int do_cache_op(unsigned long start, unsigned long end, int flags) { struct mm_struct *mm = current->active_mm; struct vm_area_struct *vma; if (end < start || flags) - return; + return -EINVAL; down_read(&mm->mmap_sem); vma = find_vma(mm, start); @@ -496,9 +496,11 @@ do_cache_op(unsigned long start, unsigned long end, int flags) if (end > vma->vm_end) end = vma->vm_end; - flush_cache_user_range(vma, start, end); + up_read(&mm->mmap_sem); + return flush_cache_user_range(start, end); } up_read(&mm->mmap_sem); + return -EINVAL; } /* @@ -544,8 +546,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) * the specified region). */ case NR(cacheflush): - do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2); - return 0; + return do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2); case NR(usr26): if (!(elf_hwcap & HWCAP_26BIT)) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 0ade0acc1ed9..992769ae2599 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -17,30 +17,13 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ call_with_stack.o mmu-y := clear_user.o copy_page.o getuser.o putuser.o - -# the code in uaccess.S is not preemption safe and -# probably faster on ARMv3 only -ifeq ($(CONFIG_PREEMPT),y) - mmu-y += copy_from_user.o copy_to_user.o -else -ifneq ($(CONFIG_CPU_32v3),y) - mmu-y += copy_from_user.o copy_to_user.o -else - mmu-y += uaccess.o -endif -endif +mmu-y += copy_from_user.o copy_to_user.o # using lib_ here won't override already available weak symbols obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o -lib-$(CONFIG_MMU) += $(mmu-y) - -ifeq ($(CONFIG_CPU_32v3),y) - lib-y += io-readsw-armv3.o io-writesw-armv3.o -else - lib-y += io-readsw-armv4.o io-writesw-armv4.o -endif - +lib-$(CONFIG_MMU) += $(mmu-y) +lib-y += io-readsw-armv4.o io-writesw-armv4.o lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o lib-$(CONFIG_ARCH_SHARK) += io-shark.o diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S deleted file mode 100644 index 88487c8c4f23..000000000000 --- a/arch/arm/lib/io-readsw-armv3.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * linux/arch/arm/lib/io-readsw-armv3.S - * - * Copyright (C) 1995-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> - -.Linsw_bad_alignment: - adr r0, .Linsw_bad_align_msg - mov r2, lr - b panic -.Linsw_bad_align_msg: - .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" - .align - -.Linsw_align: tst r1, #1 - bne .Linsw_bad_alignment - - ldr r3, [r0] - strb r3, [r1], #1 - mov r3, r3, lsr #8 - strb r3, [r1], #1 - - subs r2, r2, #1 - moveq pc, lr - -ENTRY(__raw_readsw) - teq r2, #0 @ do we have to check for the zero len? - moveq pc, lr - tst r1, #3 - bne .Linsw_align - -.Linsw_aligned: mov ip, #0xff - orr ip, ip, ip, lsl #8 - stmfd sp!, {r4, r5, r6, lr} - - subs r2, r2, #8 - bmi .Lno_insw_8 - -.Linsw_8_lp: ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - ldr r4, [r0] - and r4, r4, ip - ldr r5, [r0] - orr r4, r4, r5, lsl #16 - - ldr r5, [r0] - and r5, r5, ip - ldr r6, [r0] - orr r5, r5, r6, lsl #16 - - ldr r6, [r0] - and r6, r6, ip - ldr lr, [r0] - orr r6, r6, lr, lsl #16 - - stmia r1!, {r3 - r6} - - subs r2, r2, #8 - bpl .Linsw_8_lp - - tst r2, #7 - ldmeqfd sp!, {r4, r5, r6, pc} - -.Lno_insw_8: tst r2, #4 - beq .Lno_insw_4 - - ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - ldr r4, [r0] - and r4, r4, ip - ldr r5, [r0] - orr r4, r4, r5, lsl #16 - - stmia r1!, {r3, r4} - -.Lno_insw_4: tst r2, #2 - beq .Lno_insw_2 - - ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - str r3, [r1], #4 - -.Lno_insw_2: tst r2, #1 - ldrne r3, [r0] - strneb r3, [r1], #1 - movne r3, r3, lsr #8 - strneb r3, [r1] - - ldmfd sp!, {r4, r5, r6, pc} - - diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S deleted file mode 100644 index 49b800419e32..000000000000 --- a/arch/arm/lib/io-writesw-armv3.S +++ /dev/null @@ -1,126 +0,0 @@ -/* - * linux/arch/arm/lib/io-writesw-armv3.S - * - * Copyright (C) 1995-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> - -.Loutsw_bad_alignment: - adr r0, .Loutsw_bad_align_msg - mov r2, lr - b panic -.Loutsw_bad_align_msg: - .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n" - .align - -.Loutsw_align: tst r1, #1 - bne .Loutsw_bad_alignment - - add r1, r1, #2 - - ldr r3, [r1, #-4] - mov r3, r3, lsr #16 - orr r3, r3, r3, lsl #16 - str r3, [r0] - subs r2, r2, #1 - moveq pc, lr - -ENTRY(__raw_writesw) - teq r2, #0 @ do we have to check for the zero len? - moveq pc, lr - tst r1, #3 - bne .Loutsw_align - - stmfd sp!, {r4, r5, r6, lr} - - subs r2, r2, #8 - bmi .Lno_outsw_8 - -.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6} - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r4, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r4, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r5, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r5, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r6, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r6, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - subs r2, r2, #8 - bpl .Loutsw_8_lp - - tst r2, #7 - ldmeqfd sp!, {r4, r5, r6, pc} - -.Lno_outsw_8: tst r2, #4 - beq .Lno_outsw_4 - - ldmia r1!, {r3, r4} - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r4, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r4, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - -.Lno_outsw_4: tst r2, #2 - beq .Lno_outsw_2 - - ldr r3, [r1], #4 - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - -.Lno_outsw_2: tst r2, #1 - - ldrne r3, [r1] - - movne ip, r3, lsl #16 - orrne ip, ip, ip, lsr #16 - strne ip, [r0] - - ldmfd sp!, {r4, r5, r6, pc} diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S deleted file mode 100644 index 5c908b1cb8ed..000000000000 --- a/arch/arm/lib/uaccess.S +++ /dev/null @@ -1,564 +0,0 @@ -/* - * linux/arch/arm/lib/uaccess.S - * - * Copyright (C) 1995, 1996,1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Routines to block copy data to/from user memory - * These are highly optimised both for the 4k page size - * and for various alignments. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/errno.h> -#include <asm/domain.h> - - .text - -#define PAGE_SHIFT 12 - -/* Prototype: int __copy_to_user(void *to, const char *from, size_t n) - * Purpose : copy a block to user memory from kernel memory - * Params : to - user memory - * : from - kernel memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ - -.Lc2u_dest_not_aligned: - rsb ip, ip, #4 - cmp ip, #2 - ldrb r3, [r1], #1 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #1 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - sub r2, r2, ip - b .Lc2u_dest_aligned - -ENTRY(__copy_to_user) - stmfd sp!, {r2, r4 - r7, lr} - cmp r2, #4 - blt .Lc2u_not_enough - ands ip, r0, #3 - bne .Lc2u_dest_not_aligned -.Lc2u_dest_aligned: - - ands ip, r1, #3 - bne .Lc2u_src_not_aligned -/* - * Seeing as there has to be at least 8 bytes to copy, we can - * copy one word, and force a user-mode page fault... - */ - -.Lc2u_0fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_0nowords - ldr r3, [r1], #4 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_0fupi -/* - * ip = max no. of bytes to copy before needing another "strt" insn - */ - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #32 - blt .Lc2u_0rem8lp - -.Lc2u_0cpy8lp: ldmia r1!, {r3 - r6} - stmia r0!, {r3 - r6} @ Shouldnt fault - ldmia r1!, {r3 - r6} - subs ip, ip, #32 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_0cpy8lp - -.Lc2u_0rem8lp: cmn ip, #16 - ldmgeia r1!, {r3 - r6} - stmgeia r0!, {r3 - r6} @ Shouldnt fault - tst ip, #8 - ldmneia r1!, {r3 - r4} - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - ldrne r3, [r1], #4 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_0fupi -.Lc2u_0nowords: teq ip, #0 - beq .Lc2u_finished -.Lc2u_nowords: cmp ip, #2 - ldrb r3, [r1], #1 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #1 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_not_enough: - movs ip, r2 - bne .Lc2u_nowords -.Lc2u_finished: mov r0, #0 - ldmfd sp!, {r2, r4 - r7, pc} - -.Lc2u_src_not_aligned: - bic r1, r1, #3 - ldr r7, [r1], #4 - cmp ip, #2 - bgt .Lc2u_3fupi - beq .Lc2u_2fupi -.Lc2u_1fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_1nowords - mov r3, r7, pull #8 - ldr r7, [r1], #4 - orr r3, r3, r7, push #24 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_1fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_1rem8lp - -.Lc2u_1cpy8lp: mov r3, r7, pull #8 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_1cpy8lp - -.Lc2u_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #8 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #24 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_1fupi -.Lc2u_1nowords: mov r3, r7, get_byte_1 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - movge r3, r7, get_byte_2 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - movgt r3, r7, get_byte_3 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_2fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_2nowords - mov r3, r7, pull #16 - ldr r7, [r1], #4 - orr r3, r3, r7, push #16 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_2fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_2rem8lp - -.Lc2u_2cpy8lp: mov r3, r7, pull #16 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_2cpy8lp - -.Lc2u_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #16 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #16 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_2fupi -.Lc2u_2nowords: mov r3, r7, get_byte_2 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - movge r3, r7, get_byte_3 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #0 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_3fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_3nowords - mov r3, r7, pull #24 - ldr r7, [r1], #4 - orr r3, r3, r7, push #8 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_3fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_3rem8lp - -.Lc2u_3cpy8lp: mov r3, r7, pull #24 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_3cpy8lp - -.Lc2u_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #24 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #8 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_3fupi -.Lc2u_3nowords: mov r3, r7, get_byte_3 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #0 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished -ENDPROC(__copy_to_user) - - .pushsection .fixup,"ax" - .align 0 -9001: ldmfd sp!, {r0, r4 - r7, pc} - .popsection - -/* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n); - * Purpose : copy a block from user memory to kernel memory - * Params : to - kernel memory - * : from - user memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ -.Lcfu_dest_not_aligned: - rsb ip, ip, #4 - cmp ip, #2 -USER( TUSER( ldrb) r3, [r1], #1) @ May fault - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - sub r2, r2, ip - b .Lcfu_dest_aligned - -ENTRY(__copy_from_user) - stmfd sp!, {r0, r2, r4 - r7, lr} - cmp r2, #4 - blt .Lcfu_not_enough - ands ip, r0, #3 - bne .Lcfu_dest_not_aligned -.Lcfu_dest_aligned: - ands ip, r1, #3 - bne .Lcfu_src_not_aligned - -/* - * Seeing as there has to be at least 8 bytes to copy, we can - * copy one word, and force a user-mode page fault... - */ - -.Lcfu_0fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_0nowords -USER( TUSER( ldr) r3, [r1], #4) - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_0fupi -/* - * ip = max no. of bytes to copy before needing another "strt" insn - */ - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #32 - blt .Lcfu_0rem8lp - -.Lcfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault - stmia r0!, {r3 - r6} - ldmia r1!, {r3 - r6} @ Shouldnt fault - subs ip, ip, #32 - stmia r0!, {r3 - r6} - bpl .Lcfu_0cpy8lp - -.Lcfu_0rem8lp: cmn ip, #16 - ldmgeia r1!, {r3 - r6} @ Shouldnt fault - stmgeia r0!, {r3 - r6} - tst ip, #8 - ldmneia r1!, {r3 - r4} @ Shouldnt fault - stmneia r0!, {r3 - r4} - tst ip, #4 - TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_0fupi -.Lcfu_0nowords: teq ip, #0 - beq .Lcfu_finished -.Lcfu_nowords: cmp ip, #2 -USER( TUSER( ldrb) r3, [r1], #1) @ May fault - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_not_enough: - movs ip, r2 - bne .Lcfu_nowords -.Lcfu_finished: mov r0, #0 - add sp, sp, #8 - ldmfd sp!, {r4 - r7, pc} - -.Lcfu_src_not_aligned: - bic r1, r1, #3 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - cmp ip, #2 - bgt .Lcfu_3fupi - beq .Lcfu_2fupi -.Lcfu_1fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_1nowords - mov r3, r7, pull #8 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #24 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_1fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_1rem8lp - -.Lcfu_1cpy8lp: mov r3, r7, pull #8 - ldmia r1!, {r4 - r7} @ Shouldnt fault - subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 - stmia r0!, {r3 - r6} - bpl .Lcfu_1cpy8lp - -.Lcfu_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #8 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #24 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_1fupi -.Lcfu_1nowords: mov r3, r7, get_byte_1 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 - movge r3, r7, get_byte_2 - strgeb r3, [r0], #1 - movgt r3, r7, get_byte_3 - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_2fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_2nowords - mov r3, r7, pull #16 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #16 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_2fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_2rem8lp - - -.Lcfu_2cpy8lp: mov r3, r7, pull #16 - ldmia r1!, {r4 - r7} @ Shouldnt fault - subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 - stmia r0!, {r3 - r6} - bpl .Lcfu_2cpy8lp - -.Lcfu_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #16 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #16 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_2fupi -.Lcfu_2nowords: mov r3, r7, get_byte_2 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 - movge r3, r7, get_byte_3 - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_3fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_3nowords - mov r3, r7, pull #24 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #8 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_3fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_3rem8lp - -.Lcfu_3cpy8lp: mov r3, r7, pull #24 - ldmia r1!, {r4 - r7} @ Shouldnt fault - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 - stmia r0!, {r3 - r6} - subs ip, ip, #16 - bpl .Lcfu_3cpy8lp - -.Lcfu_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #24 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #8 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_3fupi -.Lcfu_3nowords: mov r3, r7, get_byte_3 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished -ENDPROC(__copy_from_user) - - .pushsection .fixup,"ax" - .align 0 - /* - * We took an exception. r0 contains a pointer to - * the byte not copied. - */ -9001: ldr r2, [sp], #4 @ void *to - sub r2, r0, r2 @ bytes copied - ldr r1, [sp], #4 @ unsigned long count - subs r4, r1, r2 @ bytes left to copy - movne r1, r4 - blne __memzero - mov r0, r4 - ldmfd sp!, {r4 - r7, pc} - .popsection - diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 45db05d8d94c..98a42f3472d5 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -9,15 +9,6 @@ config HAVE_AT91_DBGU0 config HAVE_AT91_DBGU1 bool -config HAVE_AT91_USART3 - bool - -config HAVE_AT91_USART4 - bool - -config HAVE_AT91_USART5 - bool - config AT91_SAM9_ALT_RESET bool default !ARCH_AT91X40 @@ -26,87 +17,121 @@ config AT91_SAM9G45_RESET bool default !ARCH_AT91X40 +config SOC_AT91SAM9 + bool + select GENERIC_CLOCKEVENTS + select CPU_ARM926T + menu "Atmel AT91 System-on-Chip" -choice - prompt "Atmel AT91 Processor" +comment "Atmel AT91 Processor" -config ARCH_AT91RM9200 +config SOC_AT91SAM9 + bool + select CPU_ARM926T + select AT91_SAM9_TIME + select AT91_SAM9_SMC + +config SOC_AT91RM9200 bool "AT91RM9200" select CPU_ARM920T select GENERIC_CLOCKEVENTS select HAVE_AT91_DBGU0 - select HAVE_AT91_USART3 -config ARCH_AT91SAM9260 - bool "AT91SAM9260 or AT91SAM9XE" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS +config SOC_AT91SAM9260 + bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 - select HAVE_AT91_USART3 - select HAVE_AT91_USART4 - select HAVE_AT91_USART5 select HAVE_NET_MACB + help + Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE + or AT91SAM9G20 SoC. -config ARCH_AT91SAM9261 - bool "AT91SAM9261" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS +config SOC_AT91SAM9261 + bool "AT91SAM9261 or AT91SAM9G10" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL + help + Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. + +config SOC_AT91SAM9263 + bool "AT91SAM9263" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU1 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + +config SOC_AT91SAM9RL + bool "AT91SAM9RL" + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 + select HAVE_FB_ATMEL -config ARCH_AT91SAM9G10 - bool "AT91SAM9G10" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS +config SOC_AT91SAM9G45 + bool "AT91SAM9G45 or AT91SAM9M10 families" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU1 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + help + Select this if you are using one of Atmel's AT91SAM9G45 family SoC. + This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + +config SOC_AT91SAM9X5 + bool "AT91SAM9x5 family" + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL + select HAVE_NET_MACB + help + Select this if you are using one of Atmel's AT91SAM9x5 family SoC. + This means that your SAM9 name finishes with a '5' (except if it is + AT91SAM9G45!). + This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 + and AT91SAM9X35. + +choice + prompt "Atmel AT91 Processor Devices for non DT boards" + +config ARCH_AT91_NONE + bool "None" + +config ARCH_AT91RM9200 + bool "AT91RM9200" + select SOC_AT91RM9200 + +config ARCH_AT91SAM9260 + bool "AT91SAM9260 or AT91SAM9XE" + select SOC_AT91SAM9260 + +config ARCH_AT91SAM9261 + bool "AT91SAM9261" + select SOC_AT91SAM9261 + +config ARCH_AT91SAM9G10 + bool "AT91SAM9G10" + select SOC_AT91SAM9261 config ARCH_AT91SAM9263 bool "AT91SAM9263" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_FB_ATMEL - select HAVE_NET_MACB - select HAVE_AT91_DBGU1 + select SOC_AT91SAM9263 config ARCH_AT91SAM9RL bool "AT91SAM9RL" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_AT91_USART3 - select HAVE_FB_ATMEL - select HAVE_AT91_DBGU0 + select SOC_AT91SAM9RL config ARCH_AT91SAM9G20 bool "AT91SAM9G20" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_AT91_DBGU0 - select HAVE_AT91_USART3 - select HAVE_AT91_USART4 - select HAVE_AT91_USART5 - select HAVE_NET_MACB + select SOC_AT91SAM9260 config ARCH_AT91SAM9G45 bool "AT91SAM9G45" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_AT91_USART3 - select HAVE_FB_ATMEL - select HAVE_NET_MACB - select HAVE_AT91_DBGU1 - -config ARCH_AT91SAM9X5 - bool "AT91SAM9x5 family" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_FB_ATMEL - select HAVE_NET_MACB - select HAVE_AT91_DBGU0 + select SOC_AT91SAM9G45 config ARCH_AT91X40 bool "AT91x40" + depends on !MMU select ARCH_USES_GETTIMEOFFSET endchoice @@ -364,6 +389,7 @@ config MACH_AT91SAM9G20EK_2MMC Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and onwards. + <http://www.atmel.com/tools/SAM9G20-EK.aspx> config MACH_CPU9G20 bool "Eukrea CPU9G20 board" @@ -433,9 +459,10 @@ comment "AT91SAM9G45 Board Type" config MACH_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" help - Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. - "ES" at the end of the name means that this board is an - Engineering Sample. + Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. + Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 + families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx> endif @@ -515,41 +542,6 @@ config AT91_TIMER_HZ system clock (of at least several MHz), rounding is less of a problem so it can be safer to use a decimal values like 100. -choice - prompt "Select a UART for early kernel messages" - -config AT91_EARLY_DBGU0 - bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl" - depends on HAVE_AT91_DBGU0 - -config AT91_EARLY_DBGU1 - bool "DBGU on 9263 and 9g45" - depends on HAVE_AT91_DBGU1 - -config AT91_EARLY_USART0 - bool "USART0" - -config AT91_EARLY_USART1 - bool "USART1" - -config AT91_EARLY_USART2 - bool "USART2" - depends on ! ARCH_AT91X40 - -config AT91_EARLY_USART3 - bool "USART3" - depends on HAVE_AT91_USART3 - -config AT91_EARLY_USART4 - bool "USART4" - depends on HAVE_AT91_USART4 - -config AT91_EARLY_USART5 - bool "USART5" - depends on HAVE_AT91_USART5 - -endchoice - endmenu endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 8512e53bed93..79d0f60af0b2 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -10,17 +10,25 @@ obj- := obj-$(CONFIG_AT91_PMC_UNIT) += clock.o obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o +obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o # CPU-specific support -obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o sam9_smc.o +obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o +obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o +obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o +obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o +obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o +obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o +obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o + +obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 364c19357e60..26917687fc30 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -26,15 +26,6 @@ #include "clock.h" #include "sam9_smc.h" -static struct map_desc at91rm9200_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_EMAC, - .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), - .length = SZ_16K, - .type = MT_DEVICE, - }, -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -258,18 +249,6 @@ static void __init at91rm9200_register_clocks(void) clk_register(&pck3); } -static struct clk_lookup console_clock_lookup; - -void __init at91rm9200_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ @@ -315,7 +294,6 @@ static void __init at91rm9200_map_io(void) { /* Map peripherals */ at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); - iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); } static void __init at91rm9200_ioremap_registers(void) diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 05774e5b1cba..e6b7d0533dd7 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -140,8 +140,8 @@ static struct macb_platform_data eth_data; static struct resource eth_resources[] = { [0] = { - .start = AT91_VA_BASE_EMAC, - .end = AT91_VA_BASE_EMAC + SZ_16K - 1, + .start = AT91RM9200_BASE_EMAC, + .end = AT91RM9200_BASE_EMAC + SZ_16K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -1152,14 +1152,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91rm9200_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1168,13 +1160,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 46f774233298..a27bbec50ca3 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -268,18 +268,6 @@ static void __init at91sam9260_register_clocks(void) clk_register(&pck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9260_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 5652dde4bbe2..ad00fe91d37d 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -1229,14 +1229,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9260_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1245,13 +1237,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 7de81e6222f1..c77d503d09d1 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -239,18 +239,6 @@ static void __init at91sam9261_register_clocks(void) clk_register(&hck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9261_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 4db961a93085..9295e90b08ff 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -1051,14 +1051,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9261_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1067,13 +1059,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index ef301be66575..7fae36502fbb 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -255,18 +255,6 @@ static void __init at91sam9263_register_clocks(void) clk_register(&pck3); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9263_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index fe99206de880..dfe5bc006d5e 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -1461,14 +1461,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9263_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1477,13 +1469,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index d222f8333dab..f2054495a655 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -288,18 +288,6 @@ static void __init at91sam9g45_register_clocks(void) clk_register(&pck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9g45_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 6b008aee1dff..db2f88c246ff 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -1741,14 +1741,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9g45_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1757,13 +1749,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index d9f2774f385e..e420085a57ef 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -232,18 +232,6 @@ static void __init at91sam9rl_register_clocks(void) clk_register(&pck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9rl_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index fe4ae22e8561..9c0b1481a9a7 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -1192,14 +1192,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9rl_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1208,13 +1200,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index 2628384aaae1..271f994314a4 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c @@ -47,20 +47,6 @@ static void __init onearm_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata onearm_eth_data = { @@ -82,6 +68,16 @@ static struct at91_udc_data __initdata onearm_udc_data = { static void __init onearm_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&onearm_eth_data); diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index 161efbaa1029..b7d8aa7b81e6 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -52,22 +52,6 @@ static void __init afeb9260_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR - | ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -183,6 +167,18 @@ static struct at91_cf_data afeb9260_cf_data = { static void __init afeb9260_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&afeb9260_usbh_data); diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index c6d44ee0c77e..29d3ef0a50fb 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -49,12 +49,6 @@ static void __init cam60_init_early(void) { /* Initialize processor: 10 MHz crystal */ at91_initialize(10000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -175,6 +169,8 @@ static void __init cam60_add_device_nand(void) static void __init cam60_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* SPI */ at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices)); diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 59d9cf997537..44328a6d4609 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -44,17 +44,6 @@ static void __init carmeva_init_early(void) { /* Initialize processor: 20.000 MHz crystal */ at91_initialize(20000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata carmeva_eth_data = { @@ -139,6 +128,13 @@ static struct gpio_led carmeva_leds[] = { static void __init carmeva_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&carmeva_eth_data); diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index 5f3680e7c883..69951ec7dbf3 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c @@ -52,34 +52,6 @@ static void __init cpu9krea_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DGBU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | - ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | - ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* USART3 on ttyS4. (Rx, Tx) */ - at91_register_uart(AT91SAM9260_ID_US3, 4, 0); - - /* USART4 on ttyS5. (Rx, Tx) */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); - - /* USART5 on ttyS6. (Rx, Tx) */ - at91_register_uart(AT91SAM9260_ID_US5, 6, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -352,6 +324,30 @@ static void __init cpu9krea_board_init(void) /* NOR */ cpu9krea_add_device_nor(); /* Serial */ + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | + ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | + ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | + ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | + ATMEL_UART_RTS); + + /* USART3 on ttyS4. (Rx, Tx) */ + at91_register_uart(AT91SAM9260_ID_US3, 4, 0); + + /* USART4 on ttyS5. (Rx, Tx) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx, Tx) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&cpu9krea_usbh_data); diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index e094cc81fe25..895cf2dba612 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c @@ -59,28 +59,6 @@ static void __init cpuat91_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | - ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | - ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART2 on ttyS3 (Rx, Tx) */ - at91_register_uart(AT91RM9200_ID_US2, 3, 0); - - /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata cpuat91_eth_data = { @@ -161,6 +139,24 @@ static struct platform_device *platform_devices[] __initdata = { static void __init cpuat91_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | + ATMEL_UART_RTS); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | + ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | + ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART2 on ttyS3 (Rx, Tx) */ + at91_register_uart(AT91RM9200_ID_US2, 3, 0); + + /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | + ATMEL_UART_RTS); at91_add_device_serial(); /* LEDs. */ at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds)); diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index 1a1547b1ce4e..cd813361cd26 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -47,15 +47,6 @@ static void __init csb337_init_early(void) { /* Initialize processor: 3.6864 MHz crystal */ at91_initialize(3686400); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); - - /* DBGU on ttyS0 */ - at91_register_uart(0, 0, 0); - - /* make console=ttyS0 the default */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata csb337_eth_data = { @@ -228,7 +219,11 @@ static struct gpio_led csb_leds[] = { static void __init csb337_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); /* Serial */ + /* DBGU on ttyS0 */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&csb337_eth_data); diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index f650bf39455d..7c8b05a57d7f 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c @@ -44,12 +44,6 @@ static void __init csb637_init_early(void) { /* Initialize processor: 3.6864 MHz crystal */ at91_initialize(3686400); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* make console=ttyS0 (ie, DBGU) the default */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata csb637_eth_data = { @@ -118,6 +112,8 @@ static void __init csb637_board_init(void) /* LED(s) */ at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds)); /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&csb637_eth_data); diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c index c18d4d307801..a1fce05aa7a5 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt.c @@ -1,10 +1,6 @@ /* * Setup code for AT91SAM Evaluation Kits with Device Tree support * - * Covers: * AT91SAM9G45-EKES board - * * AT91SAM9M10-EKES board - * * AT91SAM9M10G45-EK board - * * Copyright (C) 2011 Atmel, * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> * @@ -49,9 +45,7 @@ static void __init at91_dt_device_init(void) } static const char *at91_dt_board_compat[] __initdata = { - "atmel,at91sam9m10g45ek", - "atmel,at91sam9x5ek", - "calao,usb-a9g20", + "atmel,at91sam9", NULL }; diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index d302ca3eeb64..bd1017297989 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c @@ -44,20 +44,6 @@ static void __init eb9200_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART2 on ttyS2. (Rx, Tx) - IRDA */ - at91_register_uart(AT91RM9200_ID_US2, 2, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata eb9200_eth_data = { @@ -101,6 +87,16 @@ static struct i2c_board_info __initdata eb9200_i2c_devices[] = { static void __init eb9200_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART2 on ttyS2. (Rx, Tx) - IRDA */ + at91_register_uart(AT91RM9200_ID_US2, 2, 0); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&eb9200_eth_data); diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index 69966ce4d776..89cc3726a9ce 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c @@ -50,18 +50,6 @@ static void __init ecb_at91init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx & Tx only) */ - at91_register_uart(AT91RM9200_ID_US0, 1, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata ecb_at91eth_data = { @@ -151,7 +139,15 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = { static void __init ecb_at91board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx & Tx only) */ + at91_register_uart(AT91RM9200_ID_US0, 1, 0); at91_add_device_serial(); /* Ethernet */ diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index f23aabef8551..558546cf63f4 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c @@ -37,15 +37,6 @@ static void __init eco920_init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); - - /* DBGU on ttyS0. (Rx & Tx only */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata eco920_eth_data = { @@ -103,6 +94,10 @@ static struct spi_board_info eco920_spi_devices[] = { static void __init eco920_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); + /* DBGU on ttyS0. (Rx & Tx only */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); at91_add_device_eth(&eco920_eth_data); at91_add_device_usbh(&eco920_usbh_data); diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 1815152001f7..47658f78105d 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c @@ -41,12 +41,6 @@ static void __init flexibity_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* USB Host port */ @@ -143,6 +137,8 @@ static struct gpio_led flexibity_leds[] = { static void __init flexibity_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&flexibity_usbh_data); diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index caf017f0f4ee..33411e6ecb1f 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c @@ -61,44 +61,6 @@ static void __init foxg20_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS - | ATMEL_UART_RTS - | ATMEL_UART_DTR - | ATMEL_UART_DSR - | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx & Tx only) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, 0); - - /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US3, 4, - ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART4 on ttyS5. (Rx & Tx only) */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); - - /* USART5 on ttyS6. (Rx & Tx only) */ - at91_register_uart(AT91SAM9260_ID_US5, 6, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); - - /* Set the internal pull-up resistor on DRXD */ - at91_set_A_periph(AT91_PIN_PB14, 1); - } /* @@ -241,6 +203,39 @@ static struct i2c_board_info __initdata foxg20_i2c_devices[] = { static void __init foxg20_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS + | ATMEL_UART_RTS + | ATMEL_UART_DTR + | ATMEL_UART_DSR + | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, 0); + + /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US3, 4, + ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART4 on ttyS5. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + + /* Set the internal pull-up resistor on DRXD */ + at91_set_A_periph(AT91_PIN_PB14, 1); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&foxg20_usbh_data); diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 230e71969fb7..3e0dfa643a86 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c @@ -41,38 +41,6 @@ static void __init gsia18s_init_early(void) { stamp9g20_init_early(); - - /* - * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI). - * Used for Internal Analog Modem. - */ - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS | ATMEL_UART_RTS | - ATMEL_UART_DTR | ATMEL_UART_DSR | - ATMEL_UART_DCD | ATMEL_UART_RI); - /* - * USART1 on ttyS2 (Rx, Tx, CTS, RTS). - * Used for GPS or WiFi or Data stream. - */ - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS | ATMEL_UART_RTS); - /* - * USART2 on ttyS3 (Rx, Tx, CTS, RTS). - * Used for External Modem. - */ - at91_register_uart(AT91SAM9260_ID_US2, 3, - ATMEL_UART_CTS | ATMEL_UART_RTS); - /* - * USART3 on ttyS4 (Rx, Tx, RTS). - * Used for RS-485. - */ - at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS); - - /* - * USART4 on ttyS5 (Rx, Tx). - * Used for TRX433 Radio Module. - */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); } /* @@ -558,6 +526,37 @@ static int __init gsia18s_power_off_init(void) static void __init gsia18s_board_init(void) { + /* + * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI). + * Used for Internal Analog Modem. + */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS | + ATMEL_UART_DTR | ATMEL_UART_DSR | + ATMEL_UART_DCD | ATMEL_UART_RI); + /* + * USART1 on ttyS2 (Rx, Tx, CTS, RTS). + * Used for GPS or WiFi or Data stream. + */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); + /* + * USART2 on ttyS3 (Rx, Tx, CTS, RTS). + * Used for External Modem. + */ + at91_register_uart(AT91SAM9260_ID_US2, 3, + ATMEL_UART_CTS | ATMEL_UART_RTS); + /* + * USART3 on ttyS4 (Rx, Tx, RTS). + * Used for RS-485. + */ + at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS); + + /* + * USART4 on ttyS5 (Rx, Tx). + * Used for TRX433 Radio Module. + */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); stamp9g20_board_init(); at91_add_device_usbh(&usbh_data); at91_add_device_udc(&udc_data); diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index efde1b2327c8..f260657f32bc 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c @@ -47,18 +47,6 @@ static void __init kafa_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Set up the LEDs */ - at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata kafa_eth_data = { @@ -79,7 +67,15 @@ static struct at91_udc_data __initdata kafa_udc_data = { static void __init kafa_board_init(void) { + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&kafa_eth_data); diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index 59b92aab9bcf..ba39db5482b9 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c @@ -50,24 +50,6 @@ static void __init kb9202_init_early(void) /* Initialize processor: 10 MHz crystal */ at91_initialize(10000000); - - /* Set up the LEDs */ - at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1 (Rx & Tx only) */ - at91_register_uart(AT91RM9200_ID_US0, 1, 0); - - /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */ - at91_register_uart(AT91RM9200_ID_US1, 2, 0); - - /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */ - at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata kb9202_eth_data = { @@ -115,7 +97,21 @@ static struct atmel_nand_data __initdata kb9202_nand_data = { static void __init kb9202_board_init(void) { + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1 (Rx & Tx only) */ + at91_register_uart(AT91RM9200_ID_US0, 1, 0); + + /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */ + at91_register_uart(AT91RM9200_ID_US1, 2, 0); + + /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */ + at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&kb9202_eth_data); diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c index 57d5f6a4726a..d2f4cc161766 100644 --- a/arch/arm/mach-at91/board-neocore926.c +++ b/arch/arm/mach-at91/board-neocore926.c @@ -55,15 +55,6 @@ static void __init neocore926_init_early(void) { /* Initialize processor: 20 MHz crystal */ at91_initialize(20000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -341,6 +332,11 @@ static struct ac97c_platform_data neocore926_ac97_data = { static void __init neocore926_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index b4a12fc184c8..7fe638342421 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -40,17 +40,6 @@ static void __init pcontrol_g20_init_early(void) { stamp9g20_init_early(); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ - at91_register_uart(AT91SAM9260_ID_US4, 3, 0); } static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { @@ -199,6 +188,16 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = { static void __init pcontrol_g20_board_init(void) { + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ + at91_register_uart(AT91SAM9260_ID_US4, 3, 0); stamp9g20_board_init(); at91_add_device_usbh(&usbh_data); at91_add_device_eth(&macb_data); diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index 59e35dd14863..b45c0a5d5ca7 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c @@ -48,17 +48,6 @@ static void __init picotux200_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata picotux200_eth_data = { @@ -106,6 +95,13 @@ static struct platform_device picotux200_flash = { static void __init picotux200_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&picotux200_eth_data); diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index b6ed5ed7081a..0c61bf0d272c 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c @@ -52,24 +52,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS1 (ie, USART0) */ - at91_set_serial_console(1); - } /* @@ -235,6 +217,19 @@ static struct gpio_led ek_leds[] = { static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c index 01332aa538b2..afd7a4713766 100644 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ b/arch/arm/mach-at91/board-rm9200dk.c @@ -50,20 +50,6 @@ static void __init dk_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata dk_eth_data = { @@ -190,7 +176,17 @@ static struct gpio_led dk_leds[] = { static void __init dk_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&dk_eth_data); diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index b2e4fe21f346..2b15b8adec4c 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c @@ -50,20 +50,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata ek_eth_data = { @@ -161,7 +147,17 @@ static struct gpio_led ek_leds[] = { static void __init ek_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&ek_eth_data); diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c index af0750fafa29..24ab9be7510f 100644 --- a/arch/arm/mach-at91/board-rsi-ews.c +++ b/arch/arm/mach-at91/board-rsi-ews.c @@ -35,26 +35,6 @@ static void __init rsi_ews_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); - - /* DBGU on ttyS0. (Rx & Tx only) */ - /* This one is for debugging */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - /* Dialin/-out modem interface */ - at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART3 on ttyS4. (Rx, Tx, RTS) */ - /* RS485 communication */ - at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -204,7 +184,23 @@ static struct platform_device rsiews_nor_flash = { */ static void __init rsi_ews_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + /* This one is for debugging */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + /* Dialin/-out modem interface */ + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART3 on ttyS4. (Rx, Tx, RTS) */ + /* RS485 communication */ + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); at91_add_device_serial(); at91_set_gpio_output(AT91_PIN_PA21, 0); /* Ethernet */ diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index e8b116b6cba6..cdd21f2595d2 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c @@ -48,23 +48,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -184,7 +167,20 @@ static struct at91_mmc_data __initdata ek_mmc_data = { static void __init ek_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index d5aec55b0eb4..7b3c3913551a 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -54,20 +54,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -320,6 +306,16 @@ static void __init ek_add_device_buttons(void) {} static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 065fed342424..2736453821b0 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -58,15 +58,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -577,7 +568,12 @@ static struct gpio_led ek_leds[] = { static void __init ek_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 2ffe50f3a9e9..983cb98d2465 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -57,15 +57,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 16.367 MHz crystal */ at91_initialize(16367660); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -412,6 +403,11 @@ static struct at91_can_data ek_can_data = { static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 8923ec9f5831..3d615532ae5c 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -65,20 +65,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -372,6 +358,16 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = { static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index c88e908ddd82..9a87f0b072f8 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -53,16 +53,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ at91_initialize(12000000); - - /* DGBU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 not connected on the -EK board */ - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -457,6 +447,12 @@ static struct platform_device *devices[] __initdata = { static void __init ek_board_init(void) { /* Serial */ + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 not connected on the -EK board */ + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB HS Host */ at91_add_device_usbh_ohci(&ek_usbh_hs_data); diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index b109ce2ba864..be3239f13daa 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -42,15 +42,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -296,6 +287,11 @@ static void __init ek_add_device_buttons(void) {} static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB HS */ at91_add_device_usba(&ek_usba_udc_data); diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index ebc9d01ce742..9d446f1bb45f 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -43,16 +43,6 @@ static void __init snapper9260_init_early(void) { at91_initialize(18432000); - - /* Debug on ttyS0 */ - at91_register_uart(0, 0, 0); - at91_set_serial_console(0); - - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_register_uart(AT91SAM9260_ID_US2, 3, 0); } static struct at91_usbh_data __initdata snapper9260_usbh_data = { @@ -168,6 +158,14 @@ static void __init snapper9260_board_init(void) snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31); i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1); + /* Debug on ttyS0 */ + at91_register_uart(0, 0, 0); + + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_register_uart(AT91SAM9260_ID_US2, 3, 0); at91_add_device_serial(); at91_add_device_usbh(&snapper9260_usbh_data); at91_add_device_udc(&snapper9260_udc_data); diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index 7640049410a0..ee86f9d7ee72 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c @@ -36,44 +36,6 @@ void __init stamp9g20_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DGBU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); -} - -static void __init stamp9g20evb_init_early(void) -{ - stamp9g20_init_early(); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR - | ATMEL_UART_DCD | ATMEL_UART_RI); -} - -static void __init portuxg20_init_early(void) -{ - stamp9g20_init_early(); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR - | ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART4 on ttyS5. (Rx, Tx only) */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); - - /* USART5 on ttyS6. (Rx, Tx only) */ - at91_register_uart(AT91SAM9260_ID_US5, 6, 0); } /* @@ -254,6 +216,8 @@ void add_w1(void) void __init stamp9g20_board_init(void) { /* Serial */ + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* NAND */ add_device_nand(); @@ -269,6 +233,22 @@ void __init stamp9g20_board_init(void) static void __init portuxg20_board_init(void) { + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART4 on ttyS5. (Rx, Tx only) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx, Tx only) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); stamp9g20_board_init(); /* USB Host */ at91_add_device_usbh(&usbh_data); @@ -286,6 +266,10 @@ static void __init portuxg20_board_init(void) static void __init stamp9g20evb_board_init(void) { + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); stamp9g20_board_init(); /* USB Host */ at91_add_device_usbh(&usbh_data); @@ -303,7 +287,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20") /* Maintainer: taskit GmbH */ .timer = &at91sam926x_timer, .map_io = at91_map_io, - .init_early = portuxg20_init_early, + .init_early = stamp9g20_init_early, .init_irq = at91_init_irq_default, .init_machine = portuxg20_board_init, MACHINE_END @@ -312,7 +296,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20") /* Maintainer: taskit GmbH */ .timer = &at91sam926x_timer, .map_io = at91_map_io, - .init_early = stamp9g20evb_init_early, + .init_early = stamp9g20_init_early, .init_irq = at91_init_irq_default, .init_machine = stamp9g20evb_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c index b7483a3d0980..332ecd40bd02 100644 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ b/arch/arm/mach-at91/board-usb-a926x.c @@ -53,12 +53,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.00 MHz crystal */ at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -325,6 +319,8 @@ static void __init ek_add_device_leds(void) static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index 38dd279d30b2..d56665ea4b55 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -58,26 +58,6 @@ static void __init yl9200_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ - at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART0 on ttyS2. (Rx & Tx only to JP3) */ - at91_register_uart(AT91RM9200_ID_US0, 2, 0); - - /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ - at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -560,7 +540,23 @@ void __init yl9200_add_device_video(void) {} static void __init yl9200_board_init(void) { + /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ + at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART0 on ttyS2. (Rx & Tx only to JP3) */ + at91_register_uart(AT91RM9200_ID_US0, 2, 0); + + /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ + at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&yl9200_eth_data); diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c index ece1f9aefb47..0c6381516a5a 100644 --- a/arch/arm/mach-at91/cpuidle.c +++ b/arch/arm/mach-at91/cpuidle.c @@ -21,6 +21,7 @@ #include <linux/export.h> #include <asm/proc-fns.h> #include <asm/cpuidle.h> +#include <mach/cpu.h> #include "pm.h" @@ -33,7 +34,12 @@ static int at91_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - at91_standby(); + if (cpu_is_at91rm9200()) + at91rm9200_standby(); + else if (cpu_is_at91sam9g45()) + at91sam9g45_standby(); + else + at91sam9_standby(); return index; } diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index dd9b346c451d..0a60bf837037 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -40,17 +40,6 @@ extern struct sys_timer at91sam926x_timer; extern struct sys_timer at91x40_timer; /* Clocks */ -/* - * function to specify the clock of the default console. As we do not - * use the device/driver bus, the dev_name is not intialize. So we need - * to link the clock to a specific con_id only "usart" - */ -extern void __init at91rm9200_set_console_clock(int id); -extern void __init at91sam9260_set_console_clock(int id); -extern void __init at91sam9261_set_console_clock(int id); -extern void __init at91sam9263_set_console_clock(int id); -extern void __init at91sam9rl_set_console_clock(int id); -extern void __init at91sam9g45_set_console_clock(int id); #ifdef CONFIG_AT91_PMC_UNIT extern int __init at91_clock_init(unsigned long main_clock); extern int __init at91_dt_clock_init(void); diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index 603e6aac2a4f..e67317c67761 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -88,11 +88,6 @@ #define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ #define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ -#define AT91_USART0 AT91RM9200_BASE_US0 -#define AT91_USART1 AT91RM9200_BASE_US1 -#define AT91_USART2 AT91RM9200_BASE_US2 -#define AT91_USART3 AT91RM9200_BASE_US3 - /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 08ae9afd00fe..416c7b6c56d3 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -95,13 +95,6 @@ #define AT91SAM9260_BASE_WDT 0xfffffd40 #define AT91SAM9260_BASE_GPBR 0xfffffd50 -#define AT91_USART0 AT91SAM9260_BASE_US0 -#define AT91_USART1 AT91SAM9260_BASE_US1 -#define AT91_USART2 AT91SAM9260_BASE_US2 -#define AT91_USART3 AT91SAM9260_BASE_US3 -#define AT91_USART4 AT91SAM9260_BASE_US4 -#define AT91_USART5 AT91SAM9260_BASE_US5 - /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 44fbdc12ee62..a041406d06ee 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -79,10 +79,6 @@ #define AT91SAM9261_BASE_WDT 0xfffffd40 #define AT91SAM9261_BASE_GPBR 0xfffffd50 -#define AT91_USART0 AT91SAM9261_BASE_US0 -#define AT91_USART1 AT91SAM9261_BASE_US1 -#define AT91_USART2 AT91SAM9261_BASE_US2 - /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index d96cbb2e03c4..d201029d60b3 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -95,10 +95,6 @@ #define AT91SAM9263_BASE_RTT1 0xfffffd50 #define AT91SAM9263_BASE_GPBR 0xfffffd60 -#define AT91_USART0 AT91SAM9263_BASE_US0 -#define AT91_USART1 AT91SAM9263_BASE_US1 -#define AT91_USART2 AT91SAM9263_BASE_US2 - #define AT91_SMC AT91_SMC0 /* diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index d052abcff852..3a4da24d5911 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -106,11 +106,6 @@ #define AT91SAM9G45_BASE_RTC 0xfffffdb0 #define AT91SAM9G45_BASE_GPBR 0xfffffd60 -#define AT91_USART0 AT91SAM9G45_BASE_US0 -#define AT91_USART1 AT91SAM9G45_BASE_US1 -#define AT91_USART2 AT91SAM9G45_BASE_US2 -#define AT91_USART3 AT91SAM9G45_BASE_US3 - /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index e0073eb10144..a15db56d33fa 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -89,11 +89,6 @@ #define AT91SAM9RL_BASE_GPBR 0xfffffd60 #define AT91SAM9RL_BASE_RTC 0xfffffe00 -#define AT91_USART0 AT91SAM9RL_BASE_US0 -#define AT91_USART1 AT91SAM9RL_BASE_US1 -#define AT91_USART2 AT91SAM9RL_BASE_US2 -#define AT91_USART3 AT91SAM9RL_BASE_US3 - /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 88e43d534cdf..c75ee19b58d3 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -55,14 +55,6 @@ #define AT91SAM9X5_BASE_USART2 0xf8024000 /* - * Base addresses for early serial code (uncompress.h) - */ -#define AT91_DBGU AT91_BASE_DBGU0 -#define AT91_USART0 AT91SAM9X5_BASE_USART0 -#define AT91_USART1 AT91SAM9X5_BASE_USART1 -#define AT91_USART2 AT91SAM9X5_BASE_USART2 - -/* * Internal Memory. */ #define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 49a821192c65..369afc2ffc5b 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -121,7 +121,6 @@ extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_de #define ATMEL_UART_RI 0x20 extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins); -extern void __init at91_set_serial_console(unsigned portnr); extern struct platform_device *atmel_default_console_device; diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 0118c3338552..73d2fd209ce4 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -54,6 +54,7 @@ #define ARCH_REVISON_9200_BGA (0 << 0) #define ARCH_REVISON_9200_PQFP (1 << 0) +#ifndef __ASSEMBLY__ enum at91_soc_type { /* 920T */ AT91_SOC_RM9200, @@ -106,7 +107,7 @@ static inline int at91_soc_is_detected(void) return at91_soc_initdata.type != AT91_SOC_NONE; } -#ifdef CONFIG_ARCH_AT91RM9200 +#ifdef CONFIG_SOC_AT91RM9200 #define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) @@ -116,45 +117,37 @@ static inline int at91_soc_is_detected(void) #define cpu_is_at91rm9200_pqfp() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9260 +#ifdef CONFIG_SOC_AT91SAM9260 #define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) #define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) +#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) #else #define cpu_is_at91sam9xe() (0) #define cpu_is_at91sam9260() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9G20 -#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) -#else #define cpu_is_at91sam9g20() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9261 +#ifdef CONFIG_SOC_AT91SAM9261 #define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) -#else -#define cpu_is_at91sam9261() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9G10 #define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) #else +#define cpu_is_at91sam9261() (0) #define cpu_is_at91sam9g10() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9263 +#ifdef CONFIG_SOC_AT91SAM9263 #define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) #else #define cpu_is_at91sam9263() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9RL +#ifdef CONFIG_SOC_AT91SAM9RL #define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) #else #define cpu_is_at91sam9rl() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9G45 +#ifdef CONFIG_SOC_AT91SAM9G45 #define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) #define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) #define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) @@ -168,7 +161,7 @@ static inline int at91_soc_is_detected(void) #define cpu_is_at91sam9m11() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9X5 +#ifdef CONFIG_SOC_AT91SAM9X5 #define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) #define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) #define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) @@ -189,5 +182,6 @@ static inline int at91_soc_is_detected(void) * definitions may reduce clutter in common drivers. */ #define cpu_is_at32ap7000() (0) +#endif /* __ASSEMBLY__ */ #endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index e9e29a6c3868..ef5786299c60 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -22,27 +22,17 @@ /* 9263, 9g45 */ #define AT91_BASE_DBGU1 0xffffee00 -#if defined(CONFIG_ARCH_AT91RM9200) +#if defined(CONFIG_ARCH_AT91X40) +#include <mach/at91x40.h> +#else #include <mach/at91rm9200.h> -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) #include <mach/at91sam9260.h> -#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) #include <mach/at91sam9261.h> -#elif defined(CONFIG_ARCH_AT91SAM9263) #include <mach/at91sam9263.h> -#elif defined(CONFIG_ARCH_AT91SAM9RL) #include <mach/at91sam9rl.h> -#elif defined(CONFIG_ARCH_AT91SAM9G45) #include <mach/at91sam9g45.h> -#elif defined(CONFIG_ARCH_AT91SAM9X5) #include <mach/at91sam9x5.h> -#elif defined(CONFIG_ARCH_AT91X40) -#include <mach/at91x40.h> -#else -#error "Unsupported AT91 processor" -#endif -#if !defined(CONFIG_ARCH_AT91X40) /* * On all at91 except rm9200 and x40 have the System Controller starts * at address 0xffffc000 and has a size of 16KiB. @@ -94,7 +84,6 @@ * Virtual to Physical Address mapping for IO devices. */ #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) -#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) /* Internal SRAM is mapped below the IO devices */ #define AT91_SRAM_MAX SZ_1M diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h index 4218647c1fcd..6f6118d1576a 100644 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ b/arch/arm/mach-at91/include/mach/uncompress.h @@ -1,7 +1,8 @@ /* * arch/arm/mach-at91/include/mach/uncompress.h * - * Copyright (C) 2003 SAN People + * Copyright (C) 2003 SAN People + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,22 +26,147 @@ #include <linux/atmel_serial.h> #include <mach/hardware.h> -#if defined(CONFIG_AT91_EARLY_DBGU0) -#define UART_OFFSET AT91_BASE_DBGU0 -#elif defined(CONFIG_AT91_EARLY_DBGU1) -#define UART_OFFSET AT91_BASE_DBGU1 -#elif defined(CONFIG_AT91_EARLY_USART0) -#define UART_OFFSET AT91_USART0 -#elif defined(CONFIG_AT91_EARLY_USART1) -#define UART_OFFSET AT91_USART1 -#elif defined(CONFIG_AT91_EARLY_USART2) -#define UART_OFFSET AT91_USART2 -#elif defined(CONFIG_AT91_EARLY_USART3) -#define UART_OFFSET AT91_USART3 -#elif defined(CONFIG_AT91_EARLY_USART4) -#define UART_OFFSET AT91_USART4 -#elif defined(CONFIG_AT91_EARLY_USART5) -#define UART_OFFSET AT91_USART5 +#include <mach/at91_dbgu.h> +#include <mach/cpu.h> + +void __iomem *at91_uart; + +#if !defined(CONFIG_ARCH_AT91X40) +static const u32 uarts_rm9200[] = { + AT91_BASE_DBGU0, + AT91RM9200_BASE_US0, + AT91RM9200_BASE_US1, + AT91RM9200_BASE_US2, + AT91RM9200_BASE_US3, + 0, +}; + +static const u32 uarts_sam9260[] = { + AT91_BASE_DBGU0, + AT91SAM9260_BASE_US0, + AT91SAM9260_BASE_US1, + AT91SAM9260_BASE_US2, + AT91SAM9260_BASE_US3, + AT91SAM9260_BASE_US4, + AT91SAM9260_BASE_US5, + 0, +}; + +static const u32 uarts_sam9261[] = { + AT91_BASE_DBGU0, + AT91SAM9261_BASE_US0, + AT91SAM9261_BASE_US1, + AT91SAM9261_BASE_US2, + 0, +}; + +static const u32 uarts_sam9263[] = { + AT91_BASE_DBGU1, + AT91SAM9263_BASE_US0, + AT91SAM9263_BASE_US1, + AT91SAM9263_BASE_US2, + 0, +}; + +static const u32 uarts_sam9g45[] = { + AT91_BASE_DBGU1, + AT91SAM9G45_BASE_US0, + AT91SAM9G45_BASE_US1, + AT91SAM9G45_BASE_US2, + AT91SAM9G45_BASE_US3, + 0, +}; + +static const u32 uarts_sam9rl[] = { + AT91_BASE_DBGU0, + AT91SAM9RL_BASE_US0, + AT91SAM9RL_BASE_US1, + AT91SAM9RL_BASE_US2, + AT91SAM9RL_BASE_US3, + 0, +}; + +static const u32 uarts_sam9x5[] = { + AT91_BASE_DBGU0, + AT91SAM9X5_BASE_USART0, + AT91SAM9X5_BASE_USART1, + AT91SAM9X5_BASE_USART2, + 0, +}; + +static inline const u32* decomp_soc_detect(u32 dbgu_base) +{ + u32 cidr, socid; + + cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); + socid = cidr & ~AT91_CIDR_VERSION; + + switch (socid) { + case ARCH_ID_AT91RM9200: + return uarts_rm9200; + + case ARCH_ID_AT91SAM9G20: + case ARCH_ID_AT91SAM9260: + return uarts_sam9260; + + case ARCH_ID_AT91SAM9261: + return uarts_sam9261; + + case ARCH_ID_AT91SAM9263: + return uarts_sam9263; + + case ARCH_ID_AT91SAM9G45: + return uarts_sam9g45; + + case ARCH_ID_AT91SAM9RL64: + return uarts_sam9rl; + + case ARCH_ID_AT91SAM9X5: + return uarts_sam9x5; + } + + /* at91sam9g10 */ + if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { + return uarts_sam9261; + } + /* at91sam9xe */ + else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { + return uarts_sam9260; + } + + return NULL; +} + +static inline void arch_decomp_setup(void) +{ + int i = 0; + const u32* usarts; + + usarts = decomp_soc_detect(AT91_BASE_DBGU0); + + if (!usarts) + usarts = decomp_soc_detect(AT91_BASE_DBGU1); + if (!usarts) { + at91_uart = NULL; + return; + } + + do { + /* physical address */ + at91_uart = (void __iomem *)usarts[i]; + + if (__raw_readl(at91_uart + ATMEL_US_BRGR)) + return; + i++; + } while (usarts[i]); + + at91_uart = NULL; +} +#else +static inline void arch_decomp_setup(void) +{ + at91_uart = NULL; +} #endif /* @@ -52,28 +178,24 @@ */ static void putc(int c) { -#ifdef UART_OFFSET - void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ + if (!at91_uart) + return; - while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY)) + while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY)) barrier(); - __raw_writel(c, sys + ATMEL_US_THR); -#endif + __raw_writel(c, at91_uart + ATMEL_US_THR); } static inline void flush(void) { -#ifdef UART_OFFSET - void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ + if (!at91_uart) + return; /* wait for transmission to complete */ - while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) + while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) barrier(); -#endif } -#define arch_decomp_setup() - #define arch_decomp_wdog() #endif diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index f630250c6b87..1bfaad628731 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -261,7 +261,12 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ - at91_standby(); + if (cpu_is_at91rm9200()) + at91rm9200_standby(); + else if (cpu_is_at91sam9g45()) + at91sam9g45_standby(); + else + at91sam9_standby(); break; case PM_SUSPEND_ON: @@ -307,10 +312,9 @@ static int __init at91_pm_init(void) pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); -#ifdef CONFIG_ARCH_AT91RM9200 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ - at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); -#endif + if (cpu_is_at91rm9200()) + at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); suspend_set_ops(&at91_pm_ops); diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 89f56f3a802e..38f467c6b710 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -12,7 +12,6 @@ #define __ARCH_ARM_MACH_AT91_PM #include <mach/at91_ramc.h> -#ifdef CONFIG_ARCH_AT91RM9200 #include <mach/at91rm9200_sdramc.h> /* @@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void) "r" (lpr)); } -#define at91_standby at91rm9200_standby - -#elif defined(CONFIG_ARCH_AT91SAM9G45) - /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ @@ -75,11 +70,7 @@ static inline void at91sam9g45_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } -#define at91_standby at91sam9g45_standby - -#else - -#ifdef CONFIG_ARCH_AT91SAM9263 +#ifdef CONFIG_SOC_AT91SAM9263 /* * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. @@ -102,8 +93,4 @@ static inline void at91sam9_standby(void) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr); } -#define at91_standby at91sam9_standby - -#endif - #endif diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index db5452123f17..098c28ddf025 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -18,7 +18,7 @@ #include <mach/at91_ramc.h> -#ifdef CONFIG_ARCH_AT91SAM9263 +#ifdef CONFIG_SOC_AT91SAM9263 /* * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 5db4aa45404a..683dddfd8b13 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -26,30 +26,30 @@ static inline int at91_soc_is_enabled(void) return at91_boot_soc.init != NULL; } -#if !defined(CONFIG_ARCH_AT91RM9200) +#if !defined(CONFIG_SOC_AT91RM9200) #define at91rm9200_soc at91_boot_soc #endif -#if !(defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)) +#if !defined(CONFIG_SOC_AT91SAM9260) #define at91sam9260_soc at91_boot_soc #endif -#if !(defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)) +#if !defined(CONFIG_SOC_AT91SAM9261) #define at91sam9261_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9263) +#if !defined(CONFIG_SOC_AT91SAM9263) #define at91sam9263_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9G45) +#if !defined(CONFIG_SOC_AT91SAM9G45) #define at91sam9g45_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9RL) +#if !defined(CONFIG_SOC_AT91SAM9RL) #define at91sam9rl_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9X5) +#if !defined(CONFIG_SOC_AT91SAM9X5) #define at91sam9x5_soc at91_boot_soc #endif diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index eb34bd1251d4..ea036d621581 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -1,6 +1,6 @@ if ARCH_CLPS711X -menu "CLPS711X/EP721X Implementations" +menu "CLPS711X/EP721X/EP731X Implementations" config ARCH_AUTCPU12 bool "AUTCPU12" @@ -45,26 +45,13 @@ config ARCH_P720T config ARCH_FORTUNET bool "FORTUNET" -# XXX Maybe these should indicate register compatibility -# instead of being mutually exclusive. -config ARCH_EP7211 - bool - depends on ARCH_EDB7211 - default y - -config ARCH_EP7212 - bool - depends on ARCH_P720T || ARCH_CEIVA - default y - config EP72XX_ROM_BOOT - bool "EP72xx ROM boot" - depends on ARCH_EP7211 || ARCH_EP7212 - ---help--- + bool "EP721x/EP731x ROM boot" + help If you say Y here, your CLPS711x-based kernel will use the bootstrap mode memory map instead of the normal memory map. - Processors derived from the Cirrus CLPS-711X core support two boot + Processors derived from the Cirrus CLPS711X core support two boot modes. Normal mode boots from the external memory device at CS0. Bootstrap mode rearranges parts of the memory map, placing an internal 128 byte bootstrap ROM at CS0. This option performs the diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 3c5b5bbf24e5..c965fd8eb31a 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -36,7 +36,6 @@ #include <asm/page.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/hardware/clps7111.h> #include <asm/system_misc.h> /* @@ -44,8 +43,8 @@ */ static struct map_desc clps711x_io_desc[] __initdata = { { - .virtual = CLPS7111_VIRT_BASE, - .pfn = __phys_to_pfn(CLPS7111_PHYS_BASE), + .virtual = (unsigned long)CLPS711X_VIRT_BASE, + .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE), .length = SZ_1M, .type = MT_DEVICE } @@ -67,12 +66,6 @@ static void int1_mask(struct irq_data *d) static void int1_ack(struct irq_data *d) { - u32 intmr1; - - intmr1 = clps_readl(INTMR1); - intmr1 &= ~(1 << d->irq); - clps_writel(intmr1, INTMR1); - switch (d->irq) { case IRQ_CSINT: clps_writel(0, COEOI); break; case IRQ_TC1OI: clps_writel(0, TC1EOI); break; @@ -109,12 +102,6 @@ static void int2_mask(struct irq_data *d) static void int2_ack(struct irq_data *d) { - u32 intmr2; - - intmr2 = clps_readl(INTMR2); - intmr2 &= ~(1 << (d->irq - 16)); - clps_writel(intmr2, INTMR2); - switch (d->irq) { case IRQ_KBDINT: clps_writel(0, KBDEOI); break; } diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 44477225aed6..1dd806f2847e 100644 --- a/arch/arm/include/asm/hardware/clps7111.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -1,8 +1,6 @@ /* - * arch/arm/include/asm/hardware/clps7111.h - * - * This file contains the hardware definitions of the CLPS7111 internal - * registers. + * This file contains the hardware definitions of the Cirrus Logic + * ARM7 CLPS711X internal registers. * * Copyright (C) 2000 Deep Blue Solutions Ltd. * @@ -20,25 +18,18 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_HARDWARE_CLPS7111_H -#define __ASM_HARDWARE_CLPS7111_H - -#define CLPS7111_PHYS_BASE (0x80000000) +#ifndef __MACH_CLPS711X_H +#define __MACH_CLPS711X_H -#ifndef __ASSEMBLY__ -#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) -#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off)) -#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) -#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) -#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off)) -#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) -#endif +#define CLPS711X_PHYS_BASE (0x80000000) #define PADR (0x0000) #define PBDR (0x0001) +#define PCDR (0x0002) #define PDDR (0x0003) #define PADDR (0x0040) #define PBDDR (0x0041) +#define PCDDR (0x0042) #define PDDDR (0x0043) #define PEDR (0x0080) #define PEDDR (0x00c0) @@ -50,7 +41,7 @@ #define INTSR1 (0x0240) #define INTMR1 (0x0280) #define LCDCON (0x02c0) -#define TC1D (0x0300) +#define TC1D (0x0300) #define TC2D (0x0340) #define RTCDR (0x0380) #define RTCMR (0x03c0) @@ -85,6 +76,26 @@ #define SS2POP (0x16c0) #define KBDEOI (0x1700) +#define DAIR (0x2000) +#define DAIR0 (0x2040) +#define DAIDR1 (0x2080) +#define DAIDR2 (0x20c0) +#define DAISR (0x2100) +#define SYSCON3 (0x2200) +#define INTSR3 (0x2240) +#define INTMR3 (0x2280) +#define LEDFLSH (0x22c0) +#define SDCONF (0x2300) +#define SDRFPR (0x2340) +#define UNIQID (0x2440) +#define DAI64FS (0x2600) +#define PLLW (0x2610) +#define PLLR (0xa5a8) +#define RANDID0 (0x2700) +#define RANDID1 (0x2704) +#define RANDID2 (0x2708) +#define RANDID3 (0x270c) + /* common bits: SYSCON1 / SYSCON2 */ #define SYSCON_UARTEN (1 << 8) @@ -131,6 +142,8 @@ #define SYSFLG1_CTXFF (1 << 25) #define SYSFLG1_SSIBUSY (1 << 26) #define SYSFLG1_ID (1 << 29) +#define SYSFLG1_VERID(x) (((x) >> 30) & 3) +#define SYSFLG1_VERID_MASK (3 << 30) #define SYSFLG2_SSRXOF (1 << 0) #define SYSFLG2_RESVAL (1 << 1) @@ -178,7 +191,88 @@ #define UBRLCR_WRDLEN8 (3 << 17) #define UBRLCR_WRDLEN_MASK (3 << 17) +#define SYNCIO_FRMLEN(x) (((x) & 0x3f) << 7) +#define SYNCIO_CFGLEN(x) ((x) & 0x7f) #define SYNCIO_SMCKEN (1 << 13) #define SYNCIO_TXFRMEN (1 << 14) -#endif /* __ASM_HARDWARE_CLPS7111_H */ +#define DAIR_RESERVED (0x0404) +#define DAIR_DAIEN (1 << 16) +#define DAIR_ECS (1 << 17) +#define DAIR_LCTM (1 << 19) +#define DAIR_LCRM (1 << 20) +#define DAIR_RCTM (1 << 21) +#define DAIR_RCRM (1 << 22) +#define DAIR_LBM (1 << 23) + +#define DAIDR2_FIFOEN (1 << 15) +#define DAIDR2_FIFOLEFT (0x0d << 16) +#define DAIDR2_FIFORIGHT (0x11 << 16) + +#define DAISR_RCTS (1 << 0) +#define DAISR_RCRS (1 << 1) +#define DAISR_LCTS (1 << 2) +#define DAISR_LCRS (1 << 3) +#define DAISR_RCTU (1 << 4) +#define DAISR_RCRO (1 << 5) +#define DAISR_LCTU (1 << 6) +#define DAISR_LCRO (1 << 7) +#define DAISR_RCNF (1 << 8) +#define DAISR_RCNE (1 << 9) +#define DAISR_LCNF (1 << 10) +#define DAISR_LCNE (1 << 11) +#define DAISR_FIFO (1 << 12) + +#define DAI64FS_I2SF64 (1 << 0) +#define DAI64FS_AUDIOCLKEN (1 << 1) +#define DAI64FS_AUDIOCLKSRC (1 << 2) +#define DAI64FS_MCLK256EN (1 << 3) +#define DAI64FS_LOOPBACK (1 << 5) + +#define SYSCON3_ADCCON (1 << 0) +#define SYSCON3_CLKCTL0 (1 << 1) +#define SYSCON3_CLKCTL1 (1 << 2) +#define SYSCON3_DAISEL (1 << 3) +#define SYSCON3_ADCCKNSEN (1 << 4) +#define SYSCON3_VERSN(x) (((x) >> 5) & 7) +#define SYSCON3_VERSN_MASK (7 << 5) +#define SYSCON3_FASTWAKE (1 << 8) +#define SYSCON3_DAIEN (1 << 9) +#define SYSCON3_128FS SYSCON3_DAIEN +#define SYSCON3_ENPD67 (1 << 10) + +#define SDCONF_ACTIVE (1 << 10) +#define SDCONF_CLKCTL (1 << 9) +#define SDCONF_WIDTH_4 (0 << 7) +#define SDCONF_WIDTH_8 (1 << 7) +#define SDCONF_WIDTH_16 (2 << 7) +#define SDCONF_WIDTH_32 (3 << 7) +#define SDCONF_SIZE_16 (0 << 5) +#define SDCONF_SIZE_64 (1 << 5) +#define SDCONF_SIZE_128 (2 << 5) +#define SDCONF_SIZE_256 (3 << 5) +#define SDCONF_CASLAT_2 (2) +#define SDCONF_CASLAT_3 (3) + +#define MEMCFG_BUS_WIDTH_32 (1) +#define MEMCFG_BUS_WIDTH_16 (0) +#define MEMCFG_BUS_WIDTH_8 (3) + +#define MEMCFG_WAITSTATE_8_3 (0 << 2) +#define MEMCFG_WAITSTATE_7_3 (1 << 2) +#define MEMCFG_WAITSTATE_6_3 (2 << 2) +#define MEMCFG_WAITSTATE_5_3 (3 << 2) +#define MEMCFG_WAITSTATE_4_2 (4 << 2) +#define MEMCFG_WAITSTATE_3_2 (5 << 2) +#define MEMCFG_WAITSTATE_2_2 (6 << 2) +#define MEMCFG_WAITSTATE_1_2 (7 << 2) +#define MEMCFG_WAITSTATE_8_1 (8 << 2) +#define MEMCFG_WAITSTATE_7_1 (9 << 2) +#define MEMCFG_WAITSTATE_6_1 (10 << 2) +#define MEMCFG_WAITSTATE_5_1 (11 << 2) +#define MEMCFG_WAITSTATE_4_0 (12 << 2) +#define MEMCFG_WAITSTATE_3_0 (13 << 2) +#define MEMCFG_WAITSTATE_2_0 (14 << 2) +#define MEMCFG_WAITSTATE_1_0 (15 << 2) + +#endif /* __MACH_CLPS711X_H */ diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S index b802e8a51831..118b3d930573 100644 --- a/arch/arm/mach-clps711x/include/mach/debug-macro.S +++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S @@ -12,7 +12,6 @@ */ #include <mach/hardware.h> -#include <asm/hardware/clps7111.h> .macro addruart, rp, rv, tmp #ifndef CONFIG_DEBUG_CLPS711X_UART2 @@ -20,8 +19,8 @@ #else mov \rp, #0x1000 @ UART2 #endif - orr \rv, \rp, #CLPS7111_VIRT_BASE - orr \rp, \rp, #CLPS7111_PHYS_BASE + orr \rv, \rp, #CLPS711X_VIRT_BASE + orr \rp, \rp, #CLPS711X_PHYS_BASE .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S index 125af59d7a29..56e5c2c23504 100644 --- a/arch/arm/mach-clps711x/include/mach/entry-macro.S +++ b/arch/arm/mach-clps711x/include/mach/entry-macro.S @@ -8,7 +8,6 @@ * warranty of any kind, whether express or implied. */ #include <mach/hardware.h> -#include <asm/hardware/clps7111.h> .macro get_irqnr_preamble, base, tmp .endm @@ -18,7 +17,7 @@ #endif .macro get_irqnr_and_base, irqnr, stat, base, mask - mov \base, #CLPS7111_BASE + mov \base, #CLPS711X_VIRT_BASE ldr \stat, [\base, #INTSR1] ldr \mask, [\base, #INTMR1] mov \irqnr, #4 diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index d0b7d870be9c..13a64fcd7dd1 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -19,12 +19,21 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H +#include <mach/clps711x.h> -#define CLPS7111_VIRT_BASE 0xff000000 -#define CLPS7111_BASE CLPS7111_VIRT_BASE +#define CLPS711X_VIRT_BASE IOMEM(0xff000000) + +#ifndef __ASSEMBLY__ +#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off)) +#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off)) +#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off)) +#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off)) +#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off)) +#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off)) +#endif /* * The physical addresses that the external chip select signals map to is @@ -52,46 +61,11 @@ #define CS7_PHYS_BASE (0x00000000) #endif -#if defined (CONFIG_ARCH_EP7211) - -#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE -#define EP7211_BASE CLPS7111_VIRT_BASE -#include <asm/hardware/ep7211.h> - -#elif defined (CONFIG_ARCH_EP7212) - -#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE -#define EP7212_BASE CLPS7111_VIRT_BASE -#include <asm/hardware/ep7212.h> - -#endif - #define SYSPLD_VIRT_BASE 0xfe000000 #define SYSPLD_BASE SYSPLD_VIRT_BASE -#if defined (CONFIG_ARCH_AUTCPU12) - -#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE -#define CS89712_BASE CLPS7111_VIRT_BASE - -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> -#include <asm/hardware/cs89712.h> - -#endif - - #if defined (CONFIG_ARCH_CDB89712) -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> -#include <asm/hardware/cs89712.h> - -/* static cdb89712_map_io() areas */ -#define REGISTER_START 0x80000000 -#define REGISTER_SIZE 0x4000 -#define REGISTER_BASE 0xff000000 - #define ETHER_START 0x20000000 #define ETHER_SIZE 0x1000 #define ETHER_BASE 0xfe000000 @@ -154,13 +128,6 @@ #if defined (CONFIG_ARCH_CEIVA) -#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE -#define CEIVA_BASE CLPS7111_VIRT_BASE - -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> - - /* * The two flash banks are wired to chip selects 0 and 1. This is the mapping * for them. diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h index 30b7e97285a4..14d215f8ca81 100644 --- a/arch/arm/mach-clps711x/include/mach/irqs.h +++ b/arch/arm/mach-clps711x/include/mach/irqs.h @@ -35,7 +35,6 @@ #define IRQ_SSEOTI 15 #define INT1_IRQS (0x0000fff0) -#define INT1_ACK_IRQS (0x00004f10) /* * Interrupts from INTSR2 @@ -47,7 +46,5 @@ #define IRQ_URXINT2 (16+13) /* bit 13 */ #define INT2_IRQS (0x30070000) -#define INT2_ACK_IRQS (0x00010000) - -#define NR_IRQS 30 +#define NR_IRQS 30 diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h deleted file mode 100644 index 61fef9129c6a..000000000000 --- a/arch/arm/mach-clps711x/include/mach/time.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/time.h - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <asm/leds.h> -#include <asm/hardware/clps7111.h> - -extern void clps711x_setup_timer(void); - -/* - * IRQ handler for the timer - */ -static irqreturn_t -p720t_timer_interrupt(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - do_leds(); - xtime_update(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(regs)); -#endif - do_profile(regs); - return IRQ_HANDLED; -} - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -void __init time_init(void) -{ - clps711x_setup_timer(); - timer_irq.handler = p720t_timer_interrupt; - setup_irq(IRQ_TC2OI, &timer_irq); -} diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h index 35ed731b9f16..7b28d6a47690 100644 --- a/arch/arm/mach-clps711x/include/mach/uncompress.h +++ b/arch/arm/mach-clps711x/include/mach/uncompress.h @@ -17,14 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <mach/hardware.h> -#include <asm/hardware/clps7111.h> - -#undef CLPS7111_BASE -#define CLPS7111_BASE CLPS7111_PHYS_BASE - -#define __raw_readl(p) (*(unsigned long *)(p)) -#define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) +#include <mach/clps711x.h> #ifdef CONFIG_DEBUG_CLPS711X_UART2 #define SYSFLGx SYSFLG2 @@ -34,19 +27,25 @@ #define UARTDRx UARTDR1 #endif +#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x))) + /* + * The following code assumes the serial port has already been + * initialized by the bootloader. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * * This does not append a newline */ static inline void putc(int c) { - while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) + while (phys_reg(SYSFLGx) & SYSFLG_UTXFF) barrier(); - clps_writel(c, UARTDRx); + phys_reg(UARTDRx) = c; } static inline void flush(void) { - while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) + while (phys_reg(SYSFLGx) & SYSFLG_UBUSY) barrier(); } diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c index dd9a6cdbeb02..bbc449fbe14a 100644 --- a/arch/arm/mach-clps711x/p720t-leds.c +++ b/arch/arm/mach-clps711x/p720t-leds.c @@ -27,9 +27,6 @@ #include <asm/leds.h> #include <asm/mach-types.h> -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> - static void p720t_leds_event(led_event_t ledevt) { unsigned long flags; diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 79d001f831e0..311328314163 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -166,12 +166,6 @@ static struct pci_ops cns3xxx_pcie_ops = { .write = cns3xxx_pci_write_config, }; -static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys, - &sys->resources); -} - static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); @@ -221,10 +215,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = { .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, .hw_pci = { .domain = 0, - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &cns3xxx_pcie_ops, .setup = cns3xxx_pci_setup, - .scan = cns3xxx_pci_scan_bus, .map_irq = cns3xxx_pcie_map_irq, }, }, @@ -264,10 +257,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = { .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, .hw_pci = { .domain = 1, - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &cns3xxx_pcie_ops, .setup = cns3xxx_pci_setup, - .scan = cns3xxx_pci_scan_bus, .map_irq = cns3xxx_pcie_map_irq, }, }, diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index bda7aca04ca0..42ab1e7c4ecc 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -181,7 +181,7 @@ static int get_tclk(void) return 166666667; } -static void dove_timer_init(void) +static void __init dove_timer_init(void) { orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_DOVE_BRIDGE, get_tclk()); diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 51e0e411c9cb..7f70afc26f91 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -56,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) /* Dump all the extra MPP registers. The platform code will dump the registers for pins 0-23. */ -static void dove_mpp_dump_regs(void) +static void __init dove_mpp_dump_regs(void) { pr_debug("PMU_CTRL4_CTRL: %08x\n", readl(DOVE_MPP_CTRL4_VIRT_BASE)); @@ -67,7 +67,7 @@ static void dove_mpp_dump_regs(void) pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); } -static void dove_mpp_cfg_nfc(int sel) +static void __init dove_mpp_cfg_nfc(int sel) { u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); @@ -78,7 +78,7 @@ static void dove_mpp_cfg_nfc(int sel) dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); } -static void dove_mpp_cfg_au1(int sel) +static void __init dove_mpp_cfg_au1(int sel) { u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); @@ -118,7 +118,7 @@ static void dove_mpp_cfg_au1(int sel) /* Configure the group registers, enabling GPIO if sel indicates the pin is to be used for GPIO */ -static void dove_mpp_conf_grp(unsigned int *mpp_grp_list) +static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list) { u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); int gpio_mode; diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index 48a032005ea3..47921b0cdc65 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -43,6 +43,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) return 0; pp = &pcie_port[nr]; + sys->private_data = pp; pp->root_bus_nr = sys->busnr; /* @@ -93,19 +94,6 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static struct pcie_port *bus_to_port(int bus) -{ - int i; - - for (i = num_pcie_ports - 1; i >= 0; i--) { - int rbus = pcie_port[i].root_bus_nr; - if (rbus != -1 && rbus <= bus) - break; - } - - return i >= 0 ? pcie_port + i : NULL; -} - static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) { /* @@ -121,7 +109,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -140,7 +129,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -194,14 +184,14 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus->number); + struct pci_sys_data *sys = dev->sysdata; + struct pcie_port *pp = sys->private_data; return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; } static struct hw_pci dove_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = dove_pcie_setup, .scan = dove_pcie_scan_bus, .map_irq = dove_pcie_map_irq, diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 97a249395b5a..fe3c1fa5462b 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -2,6 +2,11 @@ if ARCH_EP93XX menu "Cirrus EP93xx Implementation Options" +config EP93XX_SOC_COMMON + bool + default y + select LEDS_GPIO_REGISTER + config CRUNCH bool "Support for MaverickCrunch" help diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 8d2589588713..66b1494f23a6 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -241,11 +241,7 @@ unsigned int ep93xx_chip_revision(void) * EP93xx GPIO *************************************************************************/ static struct resource ep93xx_gpio_resource[] = { - { - .start = EP93XX_GPIO_PHYS_BASE, - .end = EP93XX_GPIO_PHYS_BASE + 0xcc - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), }; static struct platform_device ep93xx_gpio_device = { @@ -288,11 +284,7 @@ static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE, { IRQ_EP93XX_UART3 }, &ep93xx_uart_data); static struct resource ep93xx_rtc_resource[] = { - { - .start = EP93XX_RTC_PHYS_BASE, - .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), }; static struct platform_device ep93xx_rtc_device = { @@ -304,16 +296,8 @@ static struct platform_device ep93xx_rtc_device = { static struct resource ep93xx_ohci_resources[] = { - [0] = { - .start = EP93XX_USB_PHYS_BASE, - .end = EP93XX_USB_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_EP93XX_USB, - .end = IRQ_EP93XX_USB, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), + DEFINE_RES_IRQ(IRQ_EP93XX_USB), }; @@ -372,15 +356,8 @@ void __init ep93xx_register_flash(unsigned int width, static struct ep93xx_eth_data ep93xx_eth_data; static struct resource ep93xx_eth_resource[] = { - { - .start = EP93XX_ETHERNET_PHYS_BASE, - .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_EP93XX_ETHERNET, - .end = IRQ_EP93XX_ETHERNET, - .flags = IORESOURCE_IRQ, - } + DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000), + DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET), }; static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32); @@ -461,16 +438,8 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, static struct ep93xx_spi_info ep93xx_spi_master_data; static struct resource ep93xx_spi_resources[] = { - { - .start = EP93XX_SPI_PHYS_BASE, - .end = EP93XX_SPI_PHYS_BASE + 0x18 - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_EP93XX_SSP, - .end = IRQ_EP93XX_SSP, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18), + DEFINE_RES_IRQ(IRQ_EP93XX_SSP), }; static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32); @@ -513,7 +482,7 @@ void __init ep93xx_register_spi(struct ep93xx_spi_info *info, /************************************************************************* * EP93xx LEDs *************************************************************************/ -static struct gpio_led ep93xx_led_pins[] = { +static const struct gpio_led ep93xx_led_pins[] __initconst = { { .name = "platform:grled", .gpio = EP93XX_GPIO_LINE_GRLED, @@ -523,29 +492,16 @@ static struct gpio_led ep93xx_led_pins[] = { }, }; -static struct gpio_led_platform_data ep93xx_led_data = { +static const struct gpio_led_platform_data ep93xx_led_data __initconst = { .num_leds = ARRAY_SIZE(ep93xx_led_pins), .leds = ep93xx_led_pins, }; -static struct platform_device ep93xx_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &ep93xx_led_data, - }, -}; - - /************************************************************************* * EP93xx pwm peripheral handling *************************************************************************/ static struct resource ep93xx_pwm0_resource[] = { - { - .start = EP93XX_PWM_PHYS_BASE, - .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10), }; static struct platform_device ep93xx_pwm0_device = { @@ -556,11 +512,7 @@ static struct platform_device ep93xx_pwm0_device = { }; static struct resource ep93xx_pwm1_resource[] = { - { - .start = EP93XX_PWM_PHYS_BASE + 0x20, - .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10), }; static struct platform_device ep93xx_pwm1_device = { @@ -628,11 +580,7 @@ EXPORT_SYMBOL(ep93xx_pwm_release_gpio); static struct ep93xxfb_mach_info ep93xxfb_data; static struct resource ep93xx_fb_resource[] = { - { - .start = EP93XX_RASTER_PHYS_BASE, - .end = EP93XX_RASTER_PHYS_BASE + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800), }; static struct platform_device ep93xx_fb_device = { @@ -680,15 +628,8 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) static struct ep93xx_keypad_platform_data ep93xx_keypad_data; static struct resource ep93xx_keypad_resource[] = { - { - .start = EP93XX_KEY_MATRIX_PHYS_BASE, - .end = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_EP93XX_KEY, - .end = IRQ_EP93XX_KEY, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c), + DEFINE_RES_IRQ(IRQ_EP93XX_KEY), }; static struct platform_device ep93xx_keypad_device = { @@ -761,11 +702,7 @@ EXPORT_SYMBOL(ep93xx_keypad_release_gpio); * EP93xx I2S audio peripheral handling *************************************************************************/ static struct resource ep93xx_i2s_resource[] = { - { - .start = EP93XX_I2S_PHYS_BASE, - .end = EP93XX_I2S_PHYS_BASE + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), }; static struct platform_device ep93xx_i2s_device = { @@ -824,16 +761,8 @@ EXPORT_SYMBOL(ep93xx_i2s_release); * EP93xx AC97 audio peripheral handling *************************************************************************/ static struct resource ep93xx_ac97_resources[] = { - { - .start = EP93XX_AAC_PHYS_BASE, - .end = EP93XX_AAC_PHYS_BASE + 0xac - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_EP93XX_AACINTR, - .end = IRQ_EP93XX_AACINTR, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac), + DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR), }; static struct platform_device ep93xx_ac97_device = { @@ -889,8 +818,9 @@ void __init ep93xx_init_devices(void) platform_device_register(&ep93xx_rtc_device); platform_device_register(&ep93xx_ohci_device); - platform_device_register(&ep93xx_leds); platform_device_register(&ep93xx_wdt_device); + + gpio_led_register_device(-1, &ep93xx_led_data); } void ep93xx_restart(char mode, const char *cmd) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index e81c35f936b5..b8df521fb68e 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -232,6 +232,9 @@ config MACH_ARMLEX4210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_EXYNOS4210 + select S5P_HRT + select CLKSRC_MMIO + select HAVE_SCHED_CLOCK select S5P_GPIO_INT select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 5cd7a8b8868c..7ac6ff4c46bd 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -678,7 +678,7 @@ static struct clk exynos5_clk_pdma1 = { .name = "dma", .devname = "dma-pl330.1", .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 1), + .ctrlbit = (1 << 2), }; static struct clk exynos5_clk_mdma1 = { diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 33ab4e7558af..26dac2893b8e 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -20,6 +20,7 @@ #include <asm/smp_scu.h> #include <asm/suspend.h> #include <asm/unified.h> +#include <asm/cpuidle.h> #include <mach/regs-pmu.h> #include <mach/pmu.h> @@ -34,22 +35,12 @@ #define S5P_CHECK_AFTR 0xFCBA0D10 -static int exynos4_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); static int exynos4_enter_lowpower(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); static struct cpuidle_state exynos4_cpuidle_set[] __initdata = { - [0] = { - .enter = exynos4_enter_idle, - .exit_latency = 1, - .target_residency = 100000, - .flags = CPUIDLE_FLAG_TIME_VALID, - .name = "C0", - .desc = "ARM clock gating(WFI)", - }, + [0] = ARM_CPUIDLE_WFI_STATE, [1] = { .enter = exynos4_enter_lowpower, .exit_latency = 300, @@ -63,8 +54,9 @@ static struct cpuidle_state exynos4_cpuidle_set[] __initdata = { static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); static struct cpuidle_driver exynos4_idle_driver = { - .name = "exynos4_idle", - .owner = THIS_MODULE, + .name = "exynos4_idle", + .owner = THIS_MODULE, + .en_core_tk_irqen = 1, }; /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ @@ -103,13 +95,8 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct timeval before, after; - int idle_time; unsigned long tmp; - local_irq_disable(); - do_gettimeofday(&before); - exynos4_set_wakeupmask(); /* Set value of power down register for aftr mode */ @@ -150,34 +137,6 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, /* Clear wakeup state register */ __raw_writel(0x0, S5P_WAKEUP_STAT); - do_gettimeofday(&after); - - local_irq_enable(); - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - - dev->last_residency = idle_time; - return index; -} - -static int exynos4_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - struct timeval before, after; - int idle_time; - - local_irq_disable(); - do_gettimeofday(&before); - - cpu_do_idle(); - - do_gettimeofday(&after); - local_irq_enable(); - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - - dev->last_residency = idle_time; return index; } @@ -192,7 +151,7 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev, new_index = drv->safe_state_index; if (new_index == 0) - return exynos4_enter_idle(dev, drv, new_index); + return arm_cpuidle_simple_enter(dev, drv, new_index); else return exynos4_enter_core0_aftr(dev, drv, new_index); } diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c index 50ce5b0adcf1..ce1aad3eeeb9 100644 --- a/arch/arm/mach-exynos/dev-ahci.c +++ b/arch/arm/mach-exynos/dev-ahci.c @@ -236,16 +236,8 @@ static struct ahci_platform_data exynos4_ahci_pdata = { }; static struct resource exynos4_ahci_resource[] = { - [0] = { - .start = EXYNOS4_PA_SATA, - .end = EXYNOS4_PA_SATA + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = EXYNOS4_IRQ_SATA, - .end = EXYNOS4_IRQ_SATA, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K), + [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA), }; static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32); diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c index 7199e1ae79b4..b33a5b67b547 100644 --- a/arch/arm/mach-exynos/dev-audio.c +++ b/arch/arm/mach-exynos/dev-audio.c @@ -62,26 +62,10 @@ static struct s3c_audio_pdata i2sv5_pdata = { }; static struct resource exynos4_i2s0_resource[] = { - [0] = { - .start = EXYNOS4_PA_I2S0, - .end = EXYNOS4_PA_I2S0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_TX, - .end = DMACH_I2S0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_RX, - .end = DMACH_I2S0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_I2S0S_TX, - .end = DMACH_I2S0S_TX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), + [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), }; struct platform_device exynos4_device_i2s0 = { @@ -110,21 +94,9 @@ static struct s3c_audio_pdata i2sv3_pdata = { }; static struct resource exynos4_i2s1_resource[] = { - [0] = { - .start = EXYNOS4_PA_I2S1, - .end = EXYNOS4_PA_I2S1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_TX, - .end = DMACH_I2S1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_RX, - .end = DMACH_I2S1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), }; struct platform_device exynos4_device_i2s1 = { @@ -138,21 +110,9 @@ struct platform_device exynos4_device_i2s1 = { }; static struct resource exynos4_i2s2_resource[] = { - [0] = { - .start = EXYNOS4_PA_I2S2, - .end = EXYNOS4_PA_I2S2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S2_TX, - .end = DMACH_I2S2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S2_RX, - .end = DMACH_I2S2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), }; struct platform_device exynos4_device_i2s2 = { @@ -192,21 +152,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = { }; static struct resource exynos4_pcm0_resource[] = { - [0] = { - .start = EXYNOS4_PA_PCM0, - .end = EXYNOS4_PA_PCM0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), }; struct platform_device exynos4_device_pcm0 = { @@ -220,21 +168,9 @@ struct platform_device exynos4_device_pcm0 = { }; static struct resource exynos4_pcm1_resource[] = { - [0] = { - .start = EXYNOS4_PA_PCM1, - .end = EXYNOS4_PA_PCM1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM1_TX, - .end = DMACH_PCM1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM1_RX, - .end = DMACH_PCM1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), }; struct platform_device exynos4_device_pcm1 = { @@ -248,21 +184,9 @@ struct platform_device exynos4_device_pcm1 = { }; static struct resource exynos4_pcm2_resource[] = { - [0] = { - .start = EXYNOS4_PA_PCM2, - .end = EXYNOS4_PA_PCM2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM2_TX, - .end = DMACH_PCM2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM2_RX, - .end = DMACH_PCM2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM2_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM2_RX), }; struct platform_device exynos4_device_pcm2 = { @@ -283,31 +207,11 @@ static int exynos4_ac97_cfg_gpio(struct platform_device *pdev) } static struct resource exynos4_ac97_resource[] = { - [0] = { - .start = EXYNOS4_PA_AC97, - .end = EXYNOS4_PA_AC97 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_AC97_PCMOUT, - .end = DMACH_AC97_PCMOUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_AC97_PCMIN, - .end = DMACH_AC97_PCMIN, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_AC97_MICIN, - .end = DMACH_AC97_MICIN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .start = EXYNOS4_IRQ_AC97, - .end = EXYNOS4_IRQ_AC97, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), + [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), + [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), + [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97), }; static struct s3c_audio_pdata s3c_ac97_pdata = { @@ -338,16 +242,8 @@ static int exynos4_spdif_cfg_gpio(struct platform_device *pdev) } static struct resource exynos4_spdif_resource[] = { - [0] = { - .start = EXYNOS4_PA_SPDIF, - .end = EXYNOS4_PA_SPDIF + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPDIF, - .end = DMACH_SPDIF, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_SPDIF), }; static struct s3c_audio_pdata samsung_spdif_pdata = { diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c index d726fcd3acf9..fed7116418eb 100644 --- a/arch/arm/mach-exynos/mach-armlex4210.c +++ b/arch/arm/mach-exynos/mach-armlex4210.c @@ -77,7 +77,6 @@ static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = { static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = { .cd_type = S3C_SDHCI_CD_PERMANENT, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -88,13 +87,11 @@ static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = EXYNOS4_GPX2(5), .ext_cd_gpio_invert = 1, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, .max_width = 4, }; static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = { .cd_type = S3C_SDHCI_CD_PERMANENT, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, .max_width = 4, }; @@ -121,16 +118,9 @@ static void __init armlex4210_wlan_init(void) } static struct resource armlex4210_smsc911x_resources[] = { - [0] = { - .start = EXYNOS4_PA_SROM_BANK(3), - .end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_EINT(27), - .end = IRQ_EINT(27), - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K), + [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \ + | IRQF_TRIGGER_HIGH), }; static struct smsc911x_platform_config smsc9215_config = { diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index ed90aef404c3..021dc68e89b5 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -114,7 +114,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { MMC_CAP_ERASE), .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct regulator_consumer_supply emmc_supplies[] = { @@ -155,7 +154,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = { .ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */ .ext_cd_gpio_invert = 1, .cd_type = S3C_SDHCI_CD_GPIO, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; /* WLAN */ @@ -164,7 +162,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = { .host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, .cd_type = S3C_SDHCI_CD_EXTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static void __init nuri_sdhci_init(void) diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 878d4c99142d..827cb990c316 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -472,12 +472,10 @@ static struct i2c_board_info i2c0_devs[] __initdata = { static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; /* USB EHCI */ diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index d00e4f016a68..4be083acf994 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c @@ -85,7 +85,6 @@ static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = { static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -94,7 +93,6 @@ static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = { static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct regulator_consumer_supply max8997_buck1 = diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index 83b91fa777c1..ea39f614f2db 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -93,7 +93,6 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -104,12 +103,10 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = EXYNOS4_GPK0(2), .ext_cd_gpio_invert = 1, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -120,7 +117,6 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = EXYNOS4_GPK2(2), .ext_cd_gpio_invert = 1, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, @@ -183,16 +179,9 @@ static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = { }; static struct resource smdkv310_smsc911x_resources[] = { - [0] = { - .start = EXYNOS4_PA_SROM_BANK(1), - .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_EINT(5), - .end = IRQ_EINT(5), - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, - }, + [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K), + [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \ + | IRQF_TRIGGER_LOW), }; static struct smsc911x_platform_config smsc9215_config = { diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index cb2b027f09a6..57d524e03d63 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -40,6 +40,7 @@ #include <plat/pd.h> #include <plat/regs-fb-v4.h> #include <plat/fimc-core.h> +#include <plat/s5p-time.h> #include <plat/camport.h> #include <plat/mipi_csis.h> @@ -749,7 +750,6 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct regulator_consumer_supply mmc0_supplies[] = { @@ -789,7 +789,6 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = { .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */ .ext_cd_gpio_invert = 1, .cd_type = S3C_SDHCI_CD_GPIO, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; /* WiFi */ @@ -1063,6 +1062,7 @@ static void __init universal_map_io(void) exynos_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); + s5p_set_timer_source(S5P_PWM2, S5P_PWM4); } static void s5p_tv_setup(void) @@ -1113,7 +1113,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .map_io = universal_map_io, .handle_irq = gic_handle_irq, .init_machine = universal_machine_init, - .timer = &exynos4_timer, + .timer = &s5p_timer, .reserve = &universal_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-footbridge/cats-pci.c b/arch/arm/mach-footbridge/cats-pci.c index 32321f66dec4..5cec2567c9c5 100644 --- a/arch/arm/mach-footbridge/cats-pci.c +++ b/arch/arm/mach-footbridge/cats-pci.c @@ -16,6 +16,11 @@ /* cats host-specific stuff */ static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 }; +static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin) +{ + return 0; +} + static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (dev->irq >= 255) @@ -39,11 +44,11 @@ static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) * cards being used (ie, pci-pci bridge based cards)? */ static struct hw_pci cats_pci __initdata = { - .swizzle = NULL, + .swizzle = cats_no_swizzle, .map_irq = cats_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index e17e11de4f5e..9d62e3381024 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -129,7 +129,7 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops dc21285_ops = { +struct pci_ops dc21285_ops = { .read = dc21285_read_config, .write = dc21285_write_config, }; @@ -284,11 +284,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) return 1; } -struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources); -} - #define dc21285_request_irq(_a, _b, _c, _d, _e) \ WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0) diff --git a/arch/arm/mach-footbridge/ebsa285-pci.c b/arch/arm/mach-footbridge/ebsa285-pci.c index 511c673ffa9d..fd12d8a36dc5 100644 --- a/arch/arm/mach-footbridge/ebsa285-pci.c +++ b/arch/arm/mach-footbridge/ebsa285-pci.c @@ -29,11 +29,10 @@ static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci ebsa285_pci __initdata = { - .swizzle = pci_std_swizzle, .map_irq = ebsa285_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-footbridge/netwinder-pci.c b/arch/arm/mach-footbridge/netwinder-pci.c index 62187610e17e..0fba5134e4fe 100644 --- a/arch/arm/mach-footbridge/netwinder-pci.c +++ b/arch/arm/mach-footbridge/netwinder-pci.c @@ -43,11 +43,10 @@ static int __init netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci netwinder_pci __initdata = { - .swizzle = pci_std_swizzle, .map_irq = netwinder_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-footbridge/personal-pci.c b/arch/arm/mach-footbridge/personal-pci.c index aeb651d914a6..5c9ee54613b2 100644 --- a/arch/arm/mach-footbridge/personal-pci.c +++ b/arch/arm/mach-footbridge/personal-pci.c @@ -41,8 +41,8 @@ static int __init personal_server_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci personal_server_pci __initdata = { .map_irq = personal_server_map_irq, .nr_controllers = 1, + .ops = &dc21285_ops, .setup = dc21285_setup, - .scan = dc21285_scan_bus, .preinit = dc21285_preinit, .postinit = dc21285_postinit, }; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7561eca131b0..f72d399ff3d6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -571,8 +571,10 @@ config MACH_MX35_3DS select MXC_DEBUG_BOARD select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 5f2f91d1798b..b46cab0ced53 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -243,7 +243,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = { static void __maybe_unused ads7846_dev_init(void) { if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) { - printk(KERN_ERR "can't get ads746 pen down GPIO\n"); + printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); return; } gpio_direction_input(ADS7846_PENDOWN); diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 8ecc872b2547..c515f8ede1a1 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c @@ -194,7 +194,7 @@ static void __init eukrea_cpuimx35_timer_init(void) mx35_clocks_init(); } -struct sys_timer eukrea_cpuimx35_timer = { +static struct sys_timer eukrea_cpuimx35_timer = { .init = eukrea_cpuimx35_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 97046088ff1a..7274e7928136 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -134,7 +134,7 @@ static void __init mx1ads_timer_init(void) mx1_clocks_init(32000); } -struct sys_timer mx1ads_timer = { +static struct sys_timer mx1ads_timer = { .init = mx1ads_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index e432d4acee1f..d14bbe949a4f 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -304,8 +304,7 @@ static void __init mx21ads_board_init(void) imx21_add_mxc_nand(&mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - platform_device_register_full( - (struct platform_device_info *)&mx21ads_cs8900_devinfo); + platform_device_register_full(&mx21ads_cs8900_devinfo); } static void __init mx21ads_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index 0abef5f13df5..686c60587980 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -283,7 +283,7 @@ static void __init mx31lite_timer_init(void) mx31_clocks_init(26000000); } -struct sys_timer mx31lite_timer = { +static struct sys_timer mx31lite_timer = { .init = mx31lite_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index f17a15f28316..1dfe3c7a7be1 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c @@ -580,7 +580,7 @@ static void __init mx31moboard_timer_init(void) mx31_clocks_init(26000000); } -struct sys_timer mx31moboard_timer = { +static struct sys_timer mx31moboard_timer = { .init = mx31moboard_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index 6ae51c6b95b7..c433187988a2 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c @@ -419,7 +419,7 @@ static void __init mx35pdk_timer_init(void) mx35_clocks_init(); } -struct sys_timer mx35pdk_timer = { +static struct sys_timer mx35pdk_timer = { .init = mx35pdk_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c index 586e9f822124..86e96ef11f9d 100644 --- a/arch/arm/mach-imx/mach-mx51_efikamx.c +++ b/arch/arm/mach-imx/mach-mx51_efikamx.c @@ -284,8 +284,7 @@ static struct sys_timer mx51_efikamx_timer = { .init = mx51_efikamx_timer_init, }; -MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") - /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */ +MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)") .atag_offset = 0x100, .map_io = mx51_map_io, .init_early = imx51_init_early, diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c index 24aded9e109f..88f837a6cc76 100644 --- a/arch/arm/mach-imx/mach-mx51_efikasb.c +++ b/arch/arm/mach-imx/mach-mx51_efikasb.c @@ -280,7 +280,7 @@ static struct sys_timer mx51_efikasb_timer = { .init = mx51_efikasb_timer_init, }; -MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook") +MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)") .atag_offset = 0x100, .map_io = mx51_map_io, .init_early = imx51_init_early, diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 5fddf94cc969..10c9795934a3 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -683,7 +683,7 @@ static void __init pcm037_timer_init(void) mx31_clocks_init(26000000); } -struct sys_timer pcm037_timer = { +static struct sys_timer pcm037_timer = { .init = pcm037_timer_init, }; diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 237474fcca23..73585f55cca0 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -399,7 +399,7 @@ static void __init pcm043_timer_init(void) mx35_clocks_init(); } -struct sys_timer pcm043_timer = { +static struct sys_timer pcm043_timer = { .init = pcm043_timer_init, }; diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 033257e553ef..add8c69c6c1a 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -310,7 +310,7 @@ static void __init vpr200_timer_init(void) mx35_clocks_init(); } -struct sys_timer vpr200_timer = { +static struct sys_timer vpr200_timer = { .init = vpr200_timer_init, }; diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index 3e538da6cb1f..e428f3ab15c7 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c @@ -398,24 +398,16 @@ static int impd1_probe(struct lm_device *dev) struct impd1_device *idev = impd1_devs + i; struct amba_device *d; unsigned long pc_base; + char devname[32]; pc_base = dev->resource.start + idev->offset; - - d = amba_device_alloc(NULL, pc_base, SZ_4K); - if (!d) + snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12); + d = amba_ahb_device_add(&dev->dev, devname, pc_base, SZ_4K, + dev->irq, dev->irq, + idev->platform_data, idev->id); + if (IS_ERR(d)) { + dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d)); continue; - - dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12); - d->dev.parent = &dev->dev; - d->irq[0] = dev->irq; - d->irq[1] = dev->irq; - d->periphid = idev->id; - d->dev.platform_data = idev->platform_data; - - ret = amba_device_add(d, &dev->resource); - if (ret) { - dev_err(&d->dev, "unable to register device: %d\n", ret); - amba_device_put(d); } } diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S deleted file mode 100644 index 5cc7b85ad9df..000000000000 --- a/arch/arm/mach-integrator/include/mach/entry-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Integrator platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> -#include <mach/platform.h> -#include <mach/irqs.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -/* FIXME: should not be using soo many LDRs here */ - ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE) - mov \irqnr, #IRQ_PIC_START - ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status - ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE) - teq \irqstat, #0 - ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)] - moveq \irqnr, #IRQ_CIC_START - -1001: tst \irqstat, #15 - bne 1002f - add \irqnr, \irqnr, #4 - movs \irqstat, \irqstat, lsr #4 - bne 1001b -1002: tst \irqstat, #1 - bne 1003f - add \irqnr, \irqnr, #1 - movs \irqstat, \irqstat, lsr #1 - bne 1002b -1003: /* EQ will be set if no irqs pending */ - .endm - diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h index a19a1a2fcf6b..7371018455d2 100644 --- a/arch/arm/mach-integrator/include/mach/irqs.h +++ b/arch/arm/mach-integrator/include/mach/irqs.h @@ -22,37 +22,37 @@ /* * Interrupt numbers */ -#define IRQ_PIC_START 0 -#define IRQ_SOFTINT 0 -#define IRQ_UARTINT0 1 -#define IRQ_UARTINT1 2 -#define IRQ_KMIINT0 3 -#define IRQ_KMIINT1 4 -#define IRQ_TIMERINT0 5 -#define IRQ_TIMERINT1 6 -#define IRQ_TIMERINT2 7 -#define IRQ_RTCINT 8 -#define IRQ_AP_EXPINT0 9 -#define IRQ_AP_EXPINT1 10 -#define IRQ_AP_EXPINT2 11 -#define IRQ_AP_EXPINT3 12 -#define IRQ_AP_PCIINT0 13 -#define IRQ_AP_PCIINT1 14 -#define IRQ_AP_PCIINT2 15 -#define IRQ_AP_PCIINT3 16 -#define IRQ_AP_V3INT 17 -#define IRQ_AP_CPINT0 18 -#define IRQ_AP_CPINT1 19 -#define IRQ_AP_LBUSTIMEOUT 20 -#define IRQ_AP_APCINT 21 -#define IRQ_CP_CLCDCINT 22 -#define IRQ_CP_MMCIINT0 23 -#define IRQ_CP_MMCIINT1 24 -#define IRQ_CP_AACIINT 25 -#define IRQ_CP_CPPLDINT 26 -#define IRQ_CP_ETHINT 27 -#define IRQ_CP_TSPENINT 28 -#define IRQ_PIC_END 31 +#define IRQ_PIC_START 1 +#define IRQ_SOFTINT 1 +#define IRQ_UARTINT0 2 +#define IRQ_UARTINT1 3 +#define IRQ_KMIINT0 4 +#define IRQ_KMIINT1 5 +#define IRQ_TIMERINT0 6 +#define IRQ_TIMERINT1 7 +#define IRQ_TIMERINT2 8 +#define IRQ_RTCINT 9 +#define IRQ_AP_EXPINT0 10 +#define IRQ_AP_EXPINT1 11 +#define IRQ_AP_EXPINT2 12 +#define IRQ_AP_EXPINT3 13 +#define IRQ_AP_PCIINT0 14 +#define IRQ_AP_PCIINT1 15 +#define IRQ_AP_PCIINT2 16 +#define IRQ_AP_PCIINT3 17 +#define IRQ_AP_V3INT 18 +#define IRQ_AP_CPINT0 19 +#define IRQ_AP_CPINT1 20 +#define IRQ_AP_LBUSTIMEOUT 21 +#define IRQ_AP_APCINT 22 +#define IRQ_CP_CLCDCINT 23 +#define IRQ_CP_MMCIINT0 24 +#define IRQ_CP_MMCIINT1 25 +#define IRQ_CP_AACIINT 26 +#define IRQ_CP_CPPLDINT 27 +#define IRQ_CP_ETHINT 28 +#define IRQ_CP_TSPENINT 29 +#define IRQ_PIC_END 29 #define IRQ_CIC_START 32 #define IRQ_CM_SOFTINT 32 @@ -80,4 +80,3 @@ #define NR_IRQS_INTEGRATOR_AP 34 #define NR_IRQS_INTEGRATOR_CP 47 - diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 871f148ffd72..c857501c5783 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -162,12 +162,6 @@ static void __init ap_map_io(void) #define INTEGRATOR_SC_VALID_INT 0x003fffff -static struct fpga_irq_data sc_irq_data = { - .base = VA_IC_BASE, - .irq_start = 0, - .chip.name = "SC", -}; - static void __init ap_init_irq(void) { /* Disable all interrupts initially. */ @@ -178,7 +172,8 @@ static void __init ap_init_irq(void) writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); - fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data); + fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, + -1, INTEGRATOR_SC_VALID_INT, NULL); } #ifdef CONFIG_PM @@ -478,6 +473,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator") .nr_irqs = NR_IRQS_INTEGRATOR_AP, .init_early = integrator_init_early, .init_irq = ap_init_irq, + .handle_irq = fpga_handle_irq, .timer = &ap_timer, .init_machine = ap_init, .restart = integrator_restart, diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 48a115a91d9d..a56c53608939 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -143,30 +143,14 @@ static void __init intcp_map_io(void) iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); } -static struct fpga_irq_data cic_irq_data = { - .base = INTCP_VA_CIC_BASE, - .irq_start = IRQ_CIC_START, - .chip.name = "CIC", -}; - -static struct fpga_irq_data pic_irq_data = { - .base = INTCP_VA_PIC_BASE, - .irq_start = IRQ_PIC_START, - .chip.name = "PIC", -}; - -static struct fpga_irq_data sic_irq_data = { - .base = INTCP_VA_SIC_BASE, - .irq_start = IRQ_SIC_START, - .chip.name = "SIC", -}; - static void __init intcp_init_irq(void) { - u32 pic_mask, sic_mask; + u32 pic_mask, cic_mask, sic_mask; + /* These masks are for the HW IRQ registers */ pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); pic_mask |= (~((~0u) << (29 - 22))) << 22; + cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); /* @@ -179,12 +163,14 @@ static void __init intcp_init_irq(void) writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); - fpga_irq_init(-1, pic_mask, &pic_irq_data); + fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, + -1, pic_mask, NULL); - fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)), - &cic_irq_data); + fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, + -1, cic_mask, NULL); - fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data); + fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, + IRQ_CP_CPPLDINT, sic_mask, NULL); } /* @@ -467,6 +453,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") .nr_irqs = NR_IRQS_INTEGRATOR_CP, .init_early = intcp_init_early, .init_irq = intcp_init_irq, + .handle_irq = fpga_handle_irq, .timer = &cp_timer, .init_machine = intcp_init, .restart = integrator_restart, diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c index f1ca9c122861..6c1667e728f5 100644 --- a/arch/arm/mach-integrator/pci.c +++ b/arch/arm/mach-integrator/pci.c @@ -70,21 +70,10 @@ */ static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp) { - int pin = *pinp; + if (*pinp == 0) + *pinp = 1; - if (pin == 0) - pin = 1; - - while (dev->bus->self) { - pin = pci_swizzle_interrupt_pin(dev, pin); - /* - * move up the chain of bridges, swizzling as we go. - */ - dev = dev->bus->self; - } - *pinp = pin; - - return PCI_SLOT(dev->devfn); + return pci_common_swizzle(dev, pinp); } static int irq_tab[4] __initdata = { @@ -109,7 +98,7 @@ static struct hw_pci integrator_pci __initdata = { .map_irq = integrator_map_irq, .setup = pci_v3_setup, .nr_controllers = 1, - .scan = pci_v3_scan_bus, + .ops = &pci_v3_ops, .preinit = pci_v3_preinit, .postinit = pci_v3_postinit, }; diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 67e6f9a9d1a0..b866880e82ac 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -340,7 +340,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops pci_v3_ops = { +struct pci_ops pci_v3_ops = { .read = v3_read_config, .write = v3_write_config, }; @@ -488,12 +488,6 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) return ret; } -struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys, - &sys->resources); -} - /* * V3_LB_BASE? - local bus address * V3_LB_MAP? - pci bus address diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 5c96b73e6964..e3f3e7daa79e 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -54,7 +54,6 @@ iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) } static struct hw_pci iq81340mc_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 0, .setup = iop13xx_pci_setup, .map_irq = iq81340mc_pcix_map_irq, diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index aa4dd750135a..060cddde2fd4 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -56,7 +56,6 @@ iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) } static struct hw_pci iq81340sc_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 0, .setup = iop13xx_pci_setup, .scan = iop13xx_scan_bus, diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 24069e03fdc1..9f369f09c29d 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c @@ -103,11 +103,10 @@ em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci em7210_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = em7210_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 204e1d1cd766..c15a100ba779 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -96,11 +96,10 @@ glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci glantank_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = glantank_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 3eb642af1cdc..ddd1c7ecfe57 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -130,11 +130,10 @@ ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci ep80219_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = ep80219_pci_map_irq, }; @@ -166,11 +165,10 @@ iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq31244_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = iq31244_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 2ec724b58a2c..bf155e6a3b45 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -101,11 +101,10 @@ iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq80321_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit_cond, - .scan = iop3xx_pci_scan_bus, .map_irq = iq80321_pci_map_irq, }; diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 6b6d55912444..5a7ae91e8849 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -114,11 +114,10 @@ n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci n2100_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit, - .scan = iop3xx_pci_scan_bus, .map_irq = n2100_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index abce934f3816..e74a7debe793 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -84,11 +84,10 @@ iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq80331_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit_cond, - .scan = iop3xx_pci_scan_bus, .map_irq = iq80331_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 7513559e25bb..e2f5beece6e8 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -84,11 +84,10 @@ iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci iq80332_pci __initdata = { - .swizzle = pci_std_swizzle, .nr_controllers = 1, + .ops = &iop3xx_ops, .setup = iop3xx_pci_setup, .preinit = iop3xx_pci_preinit_cond, - .scan = iop3xx_pci_scan_bus, .map_irq = iq80332_pci_map_irq, }; diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig deleted file mode 100644 index 08d2707f6ca8..000000000000 --- a/arch/arm/mach-ixp2000/Kconfig +++ /dev/null @@ -1,72 +0,0 @@ - -if ARCH_IXP2000 - -config ARCH_SUPPORTS_BIG_ENDIAN - bool - default y - -menu "Intel IXP2400/2800 Implementation Options" - -comment "IXP2400/2800 Platforms" - -config ARCH_ENP2611 - bool "Support Radisys ENP-2611" - help - Say 'Y' here if you want your kernel to support the Radisys - ENP2611 PCI network processing card. For more information on - this card, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2400 - bool "Support Intel IXDP2400" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2400 reference platform. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2800 - bool "Support Intel IXDP2800" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2800 reference platform. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2X00 - bool - depends on ARCH_IXDP2400 || ARCH_IXDP2800 - default y - -config ARCH_IXDP2401 - bool "Support Intel IXDP2401" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2401 reference platform. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2801 - bool "Support Intel IXDP2801 and IXDP28x5" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2801/2805/2855 reference platforms. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config MACH_IXDP28X5 - bool - depends on ARCH_IXDP2801 - default y - -config ARCH_IXDP2X01 - bool - depends on ARCH_IXDP2401 || ARCH_IXDP2801 - default y - -config IXP2000_SUPPORT_BROKEN_PCI_IO - bool "Support broken PCI I/O on older IXP2000s" - default y - help - Say 'N' here if you only intend to run your kernel on an - IXP2000 B0 or later model and do not need the PCI I/O - byteswap workaround. Say 'Y' otherwise. - -endmenu - -endif diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile deleted file mode 100644 index 1e6139d42a92..000000000000 --- a/arch/arm/mach-ixp2000/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Makefile for the linux kernel. -# -obj-y := core.o pci.o -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_ARCH_ENP2611) += enp2611.o -obj-$(CONFIG_ARCH_IXDP2400) += ixdp2400.o -obj-$(CONFIG_ARCH_IXDP2800) += ixdp2800.o -obj-$(CONFIG_ARCH_IXDP2X00) += ixdp2x00.o -obj-$(CONFIG_ARCH_IXDP2X01) += ixdp2x01.o - diff --git a/arch/arm/mach-ixp2000/Makefile.boot b/arch/arm/mach-ixp2000/Makefile.boot deleted file mode 100644 index 9c7af91d93da..000000000000 --- a/arch/arm/mach-ixp2000/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 - diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c deleted file mode 100644 index f214cdff01cb..000000000000 --- a/arch/arm/mach-ixp2000/core.c +++ /dev/null @@ -1,520 +0,0 @@ -/* - * arch/arm/mach-ixp2000/core.c - * - * Common routines used by all IXP2400/2800 based platforms. - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (C) MontaVista Software, Inc. - * - * Based on work Copyright (C) 2002-2003 Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/serial_8250.h> -#include <linux/mm.h> -#include <linux/export.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/time.h> -#include <asm/mach/irq.h> - -#include <mach/gpio-ixp2000.h> - -static DEFINE_SPINLOCK(ixp2000_slowport_lock); -static unsigned long ixp2000_slowport_irq_flags; - -/************************************************************************* - * Slowport access routines - *************************************************************************/ -void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg) -{ - spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags); - - old_cfg->CCR = *IXP2000_SLOWPORT_CCR; - old_cfg->WTC = *IXP2000_SLOWPORT_WTC2; - old_cfg->RTC = *IXP2000_SLOWPORT_RTC2; - old_cfg->PCR = *IXP2000_SLOWPORT_PCR; - old_cfg->ADC = *IXP2000_SLOWPORT_ADC; - - ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR); - ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC); - ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC); - ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR); - ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC); -} - -void ixp2000_release_slowport(struct slowport_cfg *old_cfg) -{ - ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR); - ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC); - ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC); - ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR); - ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC); - - spin_unlock_irqrestore(&ixp2000_slowport_lock, - ixp2000_slowport_irq_flags); -} - -/************************************************************************* - * Chip specific mappings shared by all IXP2000 systems - *************************************************************************/ -static struct map_desc ixp2000_io_desc[] __initdata = { - { - .virtual = IXP2000_CAP_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE), - .length = IXP2000_CAP_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_INTCTL_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE), - .length = IXP2000_INTCTL_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CREG_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE), - .length = IXP2000_PCI_CREG_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CSR_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE), - .length = IXP2000_PCI_CSR_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_MSF_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE), - .length = IXP2000_MSF_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_SCRATCH_RING_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE), - .length = IXP2000_SCRATCH_RING_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_SRAM0_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE), - .length = IXP2000_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE), - .length = IXP2000_PCI_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CFG0_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE), - .length = IXP2000_PCI_CFG0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CFG1_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE), - .length = IXP2000_PCI_CFG1_SIZE, - .type = MT_DEVICE, - } -}; - -void __init ixp2000_map_io(void) -{ - iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); - - /* Set slowport to 8-bit mode. */ - ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1); -} - - -/************************************************************************* - * Serial port support for IXP2000 - *************************************************************************/ -static struct plat_serial8250_port ixp2000_serial_port[] = { - { - .mapbase = IXP2000_UART_PHYS_BASE, - .membase = (char *)(IXP2000_UART_VIRT_BASE + 3), - .irq = IRQ_IXP2000_UART, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 50000000, - }, - { }, -}; - -static struct resource ixp2000_uart_resource = { - .start = IXP2000_UART_PHYS_BASE, - .end = IXP2000_UART_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixp2000_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = ixp2000_serial_port, - }, - .num_resources = 1, - .resource = &ixp2000_uart_resource, -}; - -void __init ixp2000_uart_init(void) -{ - platform_device_register(&ixp2000_serial_device); -} - - -/************************************************************************* - * Timer-tick functions for IXP2000 - *************************************************************************/ -static unsigned ticks_per_jiffy; -static unsigned ticks_per_usec; -static unsigned next_jiffy_time; -static volatile unsigned long *missing_jiffy_timer_csr; - -unsigned long ixp2000_gettimeoffset (void) -{ - unsigned long offset; - - offset = next_jiffy_time - *missing_jiffy_timer_csr; - - return offset / ticks_per_usec; -} - -static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id) -{ - /* clear timer 1 */ - ixp2000_reg_wrb(IXP2000_T1_CLR, 1); - - while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr) - >= ticks_per_jiffy) { - timer_tick(); - next_jiffy_time -= ticks_per_jiffy; - } - - return IRQ_HANDLED; -} - -static struct irqaction ixp2000_timer_irq = { - .name = "IXP2000 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = ixp2000_timer_interrupt, -}; - -void __init ixp2000_init_time(unsigned long tick_rate) -{ - ticks_per_jiffy = (tick_rate + HZ/2) / HZ; - ticks_per_usec = tick_rate / 1000000; - - /* - * We use timer 1 as our timer interrupt. - */ - ixp2000_reg_write(IXP2000_T1_CLR, 0); - ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1); - ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7)); - - /* - * We use a second timer as a monotonic counter for tracking - * missed jiffies. The IXP2000 has four timers, but if we're - * on an A-step IXP2800, timer 2 and 3 don't work, so on those - * chips we use timer 4. Timer 4 is the only timer that can - * be used for the watchdog, so we use timer 2 if we're on a - * non-buggy chip. - */ - if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) { - printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n"); - - ixp2000_reg_write(IXP2000_T4_CLR, 0); - ixp2000_reg_write(IXP2000_T4_CLD, -1); - ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7)); - missing_jiffy_timer_csr = IXP2000_T4_CSR; - } else { - ixp2000_reg_write(IXP2000_T2_CLR, 0); - ixp2000_reg_write(IXP2000_T2_CLD, -1); - ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7)); - missing_jiffy_timer_csr = IXP2000_T2_CSR; - } - next_jiffy_time = 0xffffffff; - - /* register for interrupt */ - setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq); -} - -/************************************************************************* - * GPIO helpers - *************************************************************************/ -static unsigned long GPIO_IRQ_falling_edge; -static unsigned long GPIO_IRQ_rising_edge; -static unsigned long GPIO_IRQ_level_low; -static unsigned long GPIO_IRQ_level_high; - -static void update_gpio_int_csrs(void) -{ - ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge); - ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge); - ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low); - ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high); -} - -void gpio_line_config(int line, int direction) -{ - unsigned long flags; - - local_irq_save(flags); - if (direction == GPIO_OUT) { - /* if it's an output, it ain't an interrupt anymore */ - GPIO_IRQ_falling_edge &= ~(1 << line); - GPIO_IRQ_rising_edge &= ~(1 << line); - GPIO_IRQ_level_low &= ~(1 << line); - GPIO_IRQ_level_high &= ~(1 << line); - update_gpio_int_csrs(); - - ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line); - } else if (direction == GPIO_IN) { - ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line); - } - local_irq_restore(flags); -} -EXPORT_SYMBOL(gpio_line_config); - - -/************************************************************************* - * IRQ handling IXP2000 - *************************************************************************/ -static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - int i; - unsigned long status = *IXP2000_GPIO_INST; - - for (i = 0; i <= 7; i++) { - if (status & (1<<i)) { - generic_handle_irq(i + IRQ_IXP2000_GPIO0); - } - } -} - -static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type) -{ - int line = d->irq - IRQ_IXP2000_GPIO0; - - /* - * First, configure this GPIO line as an input. - */ - ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line); - - /* - * Then, set the proper trigger type. - */ - if (type & IRQ_TYPE_EDGE_FALLING) - GPIO_IRQ_falling_edge |= 1 << line; - else - GPIO_IRQ_falling_edge &= ~(1 << line); - if (type & IRQ_TYPE_EDGE_RISING) - GPIO_IRQ_rising_edge |= 1 << line; - else - GPIO_IRQ_rising_edge &= ~(1 << line); - if (type & IRQ_TYPE_LEVEL_LOW) - GPIO_IRQ_level_low |= 1 << line; - else - GPIO_IRQ_level_low &= ~(1 << line); - if (type & IRQ_TYPE_LEVEL_HIGH) - GPIO_IRQ_level_high |= 1 << line; - else - GPIO_IRQ_level_high &= ~(1 << line); - update_gpio_int_csrs(); - - return 0; -} - -static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d) -{ - unsigned int irq = d->irq; - - ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); - - ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); - ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); - ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0))); -} - -static void ixp2000_GPIO_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); -} - -static void ixp2000_GPIO_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); -} - -static struct irq_chip ixp2000_GPIO_irq_chip = { - .irq_ack = ixp2000_GPIO_irq_mask_ack, - .irq_mask = ixp2000_GPIO_irq_mask, - .irq_unmask = ixp2000_GPIO_irq_unmask, - .irq_set_type = ixp2000_GPIO_irq_type, -}; - -static void ixp2000_pci_irq_mask(struct irq_data *d) -{ - unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; - if (d->irq == IRQ_IXP2000_PCIA) - ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26))); - else if (d->irq == IRQ_IXP2000_PCIB) - ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27))); -} - -static void ixp2000_pci_irq_unmask(struct irq_data *d) -{ - unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; - if (d->irq == IRQ_IXP2000_PCIA) - ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26))); - else if (d->irq == IRQ_IXP2000_PCIB) - ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27))); -} - -/* - * Error interrupts. These are used extensively by the microengine drivers - */ -static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - int i; - unsigned long status = *IXP2000_IRQ_ERR_STATUS; - - for(i = 31; i >= 0; i--) { - if(status & (1 << i)) { - generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i); - } - } -} - -static void ixp2000_err_irq_mask(struct irq_data *d) -{ - ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR, - (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); -} - -static void ixp2000_err_irq_unmask(struct irq_data *d) -{ - ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET, - (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); -} - -static struct irq_chip ixp2000_err_irq_chip = { - .irq_ack = ixp2000_err_irq_mask, - .irq_mask = ixp2000_err_irq_mask, - .irq_unmask = ixp2000_err_irq_unmask -}; - -static struct irq_chip ixp2000_pci_irq_chip = { - .irq_ack = ixp2000_pci_irq_mask, - .irq_mask = ixp2000_pci_irq_mask, - .irq_unmask = ixp2000_pci_irq_unmask -}; - -static void ixp2000_irq_mask(struct irq_data *d) -{ - ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq)); -} - -static void ixp2000_irq_unmask(struct irq_data *d) -{ - ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq)); -} - -static struct irq_chip ixp2000_irq_chip = { - .irq_ack = ixp2000_irq_mask, - .irq_mask = ixp2000_irq_mask, - .irq_unmask = ixp2000_irq_unmask -}; - -void __init ixp2000_init_irq(void) -{ - int irq; - - /* - * Mask all sources - */ - ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff); - ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff); - - /* clear all GPIO edge/level detects */ - ixp2000_reg_write(IXP2000_GPIO_REDR, 0); - ixp2000_reg_write(IXP2000_GPIO_FEDR, 0); - ixp2000_reg_write(IXP2000_GPIO_LSHR, 0); - ixp2000_reg_write(IXP2000_GPIO_LSLR, 0); - ixp2000_reg_write(IXP2000_GPIO_INCR, -1); - - /* clear PCI interrupt sources */ - ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0); - - /* - * Certain bits in the IRQ status register of the - * IXP2000 are reserved. Instead of trying to map - * things non 1:1 from bit position to IRQ number, - * we mark the reserved IRQs as invalid. This makes - * our mask/unmask code much simpler. - */ - for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { - if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { - irq_set_chip_and_handler(irq, &ixp2000_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } else set_irq_flags(irq, 0); - } - - for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { - if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & - IXP2000_VALID_ERR_IRQ_MASK) { - irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - else - set_irq_flags(irq, 0); - } - irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); - - for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { - irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); - - /* - * Enable PCI irqs. The actual PCI[AB] decoding is done in - * entry-macro.S, so we don't need a chained handler for the - * PCI interrupt source. - */ - ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); - for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { - irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } -} - -void ixp2000_restart(char mode, const char *cmd) -{ - ixp2000_reg_wrb(IXP2000_RESET0, RSTALL); -} diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c deleted file mode 100644 index 4867f408617c..000000000000 --- a/arch/arm/mach-ixp2000/enp2611.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * arch/arm/mach-ixp2000/enp2611.c - * - * Radisys ENP-2611 support. - * - * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The - * original version carries the following notices: - * - * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002-2003 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach/flash.h> - -/************************************************************************* - * ENP-2611 timer tick configuration - *************************************************************************/ -static void __init enp2611_timer_init(void) -{ - ixp2000_init_time(50 * 1000 * 1000); -} - -static struct sys_timer enp2611_timer = { - .init = enp2611_timer_init, - .offset = ixp2000_gettimeoffset, -}; - - -/************************************************************************* - * ENP-2611 I/O - *************************************************************************/ -static struct map_desc enp2611_io_desc[] __initdata = { - { - .virtual = ENP2611_CALEB_VIRT_BASE, - .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE), - .length = ENP2611_CALEB_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ENP2611_PM3386_0_VIRT_BASE, - .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE), - .length = ENP2611_PM3386_0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ENP2611_PM3386_1_VIRT_BASE, - .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE), - .length = ENP2611_PM3386_1_SIZE, - .type = MT_DEVICE, - } -}; - -void __init enp2611_map_io(void) -{ - ixp2000_map_io(); - iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc)); -} - - -/************************************************************************* - * ENP-2611 PCI - *************************************************************************/ -static int enp2611_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0xe0000000; - ixp2000_pci_setup(nr, sys); - return 1; -} - -static void __init enp2611_pci_preinit(void) -{ - ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000); - ixp2000_pci_preinit(); - pcibios_setup("firmware"); -} - -static inline int enp2611_pci_valid_device(struct pci_bus *bus, - unsigned int devfn) -{ - /* The 82559 ethernet controller appears at both PCI:1:0:0 and - * PCI:1:2:0, so let's pretend the second one isn't there. - */ - if (bus->number == 0x01 && devfn == 0x10) - return 0; - - return 1; -} - -static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *value) -{ - if (enp2611_pci_valid_device(bus, devfn)) - return ixp2000_pci_read_config(bus, devfn, where, size, value); - - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) -{ - if (enp2611_pci_valid_device(bus, devfn)) - return ixp2000_pci_write_config(bus, devfn, where, size, value); - - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static struct pci_ops enp2611_pci_ops = { - .read = enp2611_pci_read_config, - .write = enp2611_pci_write_config -}; - -static struct pci_bus * __init enp2611_pci_scan_bus(int nr, - struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys, - &sys->resources); -} - -static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 0) { - /* IXP2400. */ - irq = IRQ_IXP2000_PCIA; - } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 1) { - /* 21555 non-transparent bridge. */ - irq = IRQ_IXP2000_PCIB; - } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 4) { - /* PCI2050B transparent bridge. */ - irq = -1; - } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) { - /* 82559 ethernet. */ - irq = IRQ_IXP2000_PCIA; - } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 1) { - /* SPI-3 option board. */ - irq = IRQ_IXP2000_PCIB; - } else { - printk(KERN_ERR "enp2611_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -struct hw_pci enp2611_pci __initdata = { - .nr_controllers = 1, - .setup = enp2611_pci_setup, - .preinit = enp2611_pci_preinit, - .scan = enp2611_pci_scan_bus, - .map_irq = enp2611_pci_map_irq, -}; - -int __init enp2611_pci_init(void) -{ - if (machine_is_enp2611()) - pci_common_init(&enp2611_pci); - - return 0; -} - -subsys_initcall(enp2611_pci_init); - - -/************************************************************************* - * ENP-2611 Machine Initialization - *************************************************************************/ -static struct flash_platform_data enp2611_flash_platform_data = { - .map_name = "cfi_probe", - .width = 1, -}; - -static struct ixp2000_flash_data enp2611_flash_data = { - .platform_data = &enp2611_flash_platform_data, - .nr_banks = 1 -}; - -static struct resource enp2611_flash_resource = { - .start = 0xc4000000, - .end = 0xc4000000 + 0x00ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device enp2611_flash = { - .name = "IXP2000-Flash", - .id = 0, - .dev = { - .platform_data = &enp2611_flash_data, - }, - .num_resources = 1, - .resource = &enp2611_flash_resource, -}; - -static struct ixp2000_i2c_pins enp2611_i2c_gpio_pins = { - .sda_pin = ENP2611_GPIO_SDA, - .scl_pin = ENP2611_GPIO_SCL, -}; - -static struct platform_device enp2611_i2c_controller = { - .name = "IXP2000-I2C", - .id = 0, - .dev = { - .platform_data = &enp2611_i2c_gpio_pins - }, - .num_resources = 0 -}; - -static struct platform_device *enp2611_devices[] __initdata = { - &enp2611_flash, - &enp2611_i2c_controller -}; - -static void __init enp2611_init_machine(void) -{ - platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices)); - ixp2000_uart_init(); -} - - -MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board") - /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ - .atag_offset = 0x100, - .map_io = enp2611_map_io, - .init_irq = ixp2000_init_irq, - .timer = &enp2611_timer, - .init_machine = enp2611_init_machine, - .restart = ixp2000_restart, -MACHINE_END - - diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S deleted file mode 100644 index bdd3ccdc2890..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-ixp2000/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00030000 -#ifdef __ARMEB__ - orr \rp, \rp, #0x00000003 -#endif - orr \rv, \rp, #0xfe000000 @ virtual base - orr \rv, \rv, #0x00f00000 - orr \rp, \rp, #0xc0000000 @ Physical base - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h deleted file mode 100644 index 9ce3690061d5..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/enp2611.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/enp2611.h - * - * Register and other defines for Radisys ENP-2611 - * - * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The - * original version carries the following notices: - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ENP2611_H -#define __ENP2611_H - -#define ENP2611_CALEB_PHYS_BASE 0xc5000000 -#define ENP2611_CALEB_VIRT_BASE 0xfe000000 -#define ENP2611_CALEB_SIZE 0x00100000 - -#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000 -#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000 -#define ENP2611_PM3386_0_SIZE 0x00100000 - -#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000 -#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000 -#define ENP2611_PM3386_1_SIZE 0x00100000 - -#define ENP2611_GPIO_SCL 7 -#define ENP2611_GPIO_SDA 6 - -#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4 -#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3 -#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2 -#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1 -#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0 - - -#endif diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S deleted file mode 100644 index c4444dff9202..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/entry-macro.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for IXP2000-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/irqs.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \irqnr, #0x0 @clear out irqnr as default - mov \base, #0xfe000000 - orr \base, \base, #0x00e00000 - orr \base, \base, #0x08 - ldr \irqstat, [\base] @ get interrupts - - cmp \irqstat, #0 - beq 1001f - - clz \irqnr, \irqstat - mov \base, #31 - subs \irqnr, \base, \irqnr - - /* - * We handle PCIA and PCIB here so we don't have an - * extra layer of code just to check these two bits. - */ - cmp \irqnr, #IRQ_IXP2000_PCI - bne 1001f - - mov \base, #0xfe000000 - orr \base, \base, #0x00c00000 - orr \base, \base, #0x00000100 - orr \base, \base, #0x00000058 - ldr \irqstat, [\base] - - mov \tmp, #(1<<26) - tst \irqstat, \tmp - movne \irqnr, #IRQ_IXP2000_PCIA - bne 1001f - - mov \tmp, #(1<<27) - tst \irqstat, \tmp - movne \irqnr, #IRQ_IXP2000_PCIB - -1001: - .endm - diff --git a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h b/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h deleted file mode 100644 index af836c76c3f1..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/gpio.h - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software, you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * IXP2000 GPIO in/out, edge/level detection for IRQs: - * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High - * or both Falling-edge and Rising-edge. - * This must be called *before* the corresponding IRQ is registerd. - * Use this instead of directly setting the GPIO registers. - * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb) - */ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#ifndef __ASSEMBLY__ - -#define GPIO_IN 0 -#define GPIO_OUT 1 - -#define IXP2000_GPIO_LOW 0 -#define IXP2000_GPIO_HIGH 1 - -extern void gpio_line_config(int line, int direction); - -static inline int gpio_line_get(int line) -{ - return (((*IXP2000_GPIO_PLR) >> line) & 1); -} - -static inline void gpio_line_set(int line, int value) -{ - if (value == IXP2000_GPIO_HIGH) { - ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line); - } else if (value == IXP2000_GPIO_LOW) { - ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line); - } -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* ASM_ARCH_IXP2000_GPIO_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h deleted file mode 100644 index cdaf1db84003..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/hardware.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/hardware.h - * - * Hardware definitions for IXP2400/2800 based systems - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * - * Maintainer: Deepak Saxena <dsaxena@mvista.com> - * - * Copyright (C) 2001-2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ - -#include "ixp2000-regs.h" /* Chipset Registers */ - -/* - * Platform helper functions - */ -#include "platform.h" - -/* - * Platform-specific bits - */ -#include "enp2611.h" /* ENP-2611 */ -#include "ixdp2x00.h" /* IXDP2400/2800 */ -#include "ixdp2x01.h" /* IXDP2401/2801 */ - -#endif /* _ASM_ARCH_HARDWARE_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h deleted file mode 100644 index f6552d6f35ab..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/io.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/io.h - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyrgiht (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * The A? revisions of the IXP2000s assert byte lanes for PCI I/O - * transactions the other way round (MEM transactions don't have this - * issue), so if we want to support those models, we need to override - * the standard I/O functions. - * - * B0 and later have a bit that can be set to 1 to get the proper - * behavior for I/O transactions, which then allows us to use the - * standard I/O functions. This is what we do if the user does not - * explicitly ask for support for pre-B0. - */ -#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO -#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) - -#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3) -#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2) - -#define outb(v,p) __raw_writeb((v),alignb(___io(p))) -#define outw(v,p) __raw_writew((v),alignw(___io(p))) -#define outl(v,p) __raw_writel((v),___io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; }) -#define inw(p) \ - ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; }) -#define inl(p) \ - ({ unsigned int __v = (__raw_readl(___io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l) -#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l) -#define outsl(p,d,l) __raw_writesl(___io(p),d,l) - -#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l) -#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) -#define insl(p,d,l) __raw_readsl(___io(p),d,l) - -#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE) - -#define ioread8(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readb(alignb(p)); \ - } else { \ - __v = __raw_readb(p); \ - } \ - \ - __v; \ - }) \ - -#define ioread16(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readw(alignw(p)); \ - } else { \ - __v = le16_to_cpu(__raw_readw(p)); \ - } \ - \ - __v; \ - }) - -#define ioread32(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readl(p); \ - } else { \ - __v = le32_to_cpu(__raw_readl(p)); \ - } \ - \ - __v; \ - }) - -#define iowrite8(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writeb((v), alignb(p)); \ - } else { \ - __raw_writeb((v), p); \ - } \ - }) - -#define iowrite16(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writew((v), alignw(p)); \ - } else { \ - __raw_writew(cpu_to_le16(v), p); \ - } \ - }) - -#define iowrite32(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writel((v), p); \ - } else { \ - __raw_writel(cpu_to_le32(v), p); \ - } \ - }) - -#define ioport_map(port, nr) ___io(port) - -#define ioport_unmap(addr) -#else -#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) -#endif - - -#endif diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h deleted file mode 100644 index bee96bcafdca..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/irqs.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/irqs.h - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IRQS_H -#define _IRQS_H - -/* - * Do NOT add #ifdef MACHINE_FOO in here. - * Simpy add your machine IRQs here and increase NR_IRQS if needed to - * hold your machine's IRQ table. - */ - -/* - * Some interrupt numbers go unused b/c the IRQ mask/ummask/status - * register has those bit reserved. We just mark those interrupts - * as invalid and this allows us to do mask/unmask with a single - * shift operation instead of having to map the IRQ number to - * a HW IRQ number. - */ -#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */ -#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/ -#define IRQ_IXP2000_UART 2 -#define IRQ_IXP2000_GPIO 3 -#define IRQ_IXP2000_TIMER1 4 -#define IRQ_IXP2000_TIMER2 5 -#define IRQ_IXP2000_TIMER3 6 -#define IRQ_IXP2000_TIMER4 7 -#define IRQ_IXP2000_PMU 8 -#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */ -#define IRQ_IXP2000_DMA1 10 -#define IRQ_IXP2000_DMA2 11 -#define IRQ_IXP2000_DMA3 12 -#define IRQ_IXP2000_PCI_DOORBELL 13 -#define IRQ_IXP2000_ME_ATTN 14 -#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */ -#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */ -#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */ -#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */ -#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */ -#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */ -#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */ -#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */ -#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */ - -/* define generic GPIOs */ -#define IRQ_IXP2000_GPIO0 32 -#define IRQ_IXP2000_GPIO1 33 -#define IRQ_IXP2000_GPIO2 34 -#define IRQ_IXP2000_GPIO3 35 -#define IRQ_IXP2000_GPIO4 36 -#define IRQ_IXP2000_GPIO5 37 -#define IRQ_IXP2000_GPIO6 38 -#define IRQ_IXP2000_GPIO7 39 - -/* split off the 2 PCI sources */ -#define IRQ_IXP2000_PCIA 40 -#define IRQ_IXP2000_PCIB 41 - -/* Int sources from IRQ_ERROR_STATUS */ -#define IRQ_IXP2000_DRAM0_MIN_ERR 42 -#define IRQ_IXP2000_DRAM0_MAJ_ERR 43 -#define IRQ_IXP2000_DRAM1_MIN_ERR 44 -#define IRQ_IXP2000_DRAM1_MAJ_ERR 45 -#define IRQ_IXP2000_DRAM2_MIN_ERR 46 -#define IRQ_IXP2000_DRAM2_MAJ_ERR 47 -/* 48-57 reserved */ -#define IRQ_IXP2000_SRAM0_ERR 58 -#define IRQ_IXP2000_SRAM1_ERR 59 -#define IRQ_IXP2000_SRAM2_ERR 60 -#define IRQ_IXP2000_SRAM3_ERR 61 -/* 62-65 reserved */ -#define IRQ_IXP2000_MEDIA_ERR 66 -#define IRQ_IXP2000_PCI_ERR 67 -#define IRQ_IXP2000_SP_INT 68 - -#define NR_IXP2000_IRQS 69 - -#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x)) - -#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS)) - -#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) -#define IXP2000_VALID_ERR_IRQ_MASK (\ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) ) - -/* - * This allows for all the on-chip sources plus up to 32 CPLD based - * IRQs. Should be more than enough. - */ -#define IXP2000_BOARD_IRQS 32 -#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS) - - -/* - * IXDP2400 specific IRQs - */ -#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1) -#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5) -#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6) -#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7) - -#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1) -#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS - -/* IXDP2800 specific IRQs */ -#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1) -#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5) - -#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1) -#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS - -/* - * IRQs on both IXDP2x01 boards - */ -#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5) -#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6) -#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7) -#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8) -#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16) -#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17) -#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18) -#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19) -#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21) -#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22) -#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24) -#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25) -#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26) - -#define IXDP2X01_VALID_IRQ_MASK ( \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) ) - -/* - * IXDP2401 specific IRQs - */ -#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1) - -#define IXDP2401_VALID_IRQ_MASK ( \ - IXDP2X01_VALID_IRQ_MASK | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546)) - -/* - * IXDP2801-specific IRQs - */ -#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27) -#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28) - -#define IXDP2801_VALID_IRQ_MASK ( \ - IXDP2X01_VALID_IRQ_MASK | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF)) - -#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1) - -#endif /*_IRQS_H*/ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h deleted file mode 100644 index 5df8479d9481..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h - * - * Register and other defines for IXDP2[48]00 platforms - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _IXDP2X00_H_ -#define _IXDP2X00_H_ - -/* - * On board CPLD memory map - */ -#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000 -#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000 -#define IXDP2X00_CPLD_SIZE 0x00100000 - - -#define IXDP2X00_CPLD_REG(x) \ - (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x) - -/* - * IXDP2400 CPLD registers - */ -#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0) -#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4) -#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8) -#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc) -#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10) -#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14) -#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18) -#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48) - -/* - * IXDP2800 CPLD registers - */ -#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0) -#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140) - - -#define IXDP2X00_GPIO_I2C_ENABLE 0x02 -#define IXDP2X00_GPIO_SCL 0x07 -#define IXDP2X00_GPIO_SDA 0x06 - -/* - * PCI devfns for on-board devices. We need these to be able to - * properly translate IRQs and for device removal. - */ -#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */ -#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */ -#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */ -#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ - -#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */ -#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */ -#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ - -#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */ -#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */ -#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */ -#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */ -#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */ - -#ifndef __ASSEMBLY__ -/* - * The master NPU is always PCI master. - */ -static inline unsigned int ixdp2x00_master_npu(void) -{ - return !!ixp2000_is_pcimaster(); -} - -/* - * Helper functions used by ixdp2400 and ixdp2800 specific code - */ -void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long); -void ixdp2x00_slave_pci_postinit(void); -void ixdp2x00_init_machine(void); -void ixdp2x00_map_io(void); - -#endif - -#endif /*_IXDP2X00_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h deleted file mode 100644 index 4c1f04083e54..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h - * - * Platform definitions for IXDP2X01 && IXDP2801 systems - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (c) MontaVista Software, Inc. - * - * Based on original code Copyright (c) 2002-2003 Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __IXDP2X01_H__ -#define __IXDP2X01_H__ - -#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000 -#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000 -#define IXDP2X01_CPLD_REGION_SIZE 0x00100000 - -#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg) -#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg) - -#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40) -#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40) - -#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60) -#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60) - -#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80) -#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16) - -#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00) -#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08) -#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C) -#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10) -#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG -#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14) - -#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20) - -#define IXDP2X01_CPLD_FLASH_INTERN 0x8000 -#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF -#define IXDP2X01_FLASH_WINDOW_BITS 25 -#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS) -#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1) - -#define IXDP2X01_UART_CLK 1843200 - -#define IXDP2X01_GPIO_I2C_ENABLE 0x02 -#define IXDP2X01_GPIO_SCL 0x07 -#define IXDP2X01_GPIO_SDA 0x06 - -#endif /* __IXDP2x01_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h deleted file mode 100644 index 822f63f2f4a2..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h - * - * Chipset register definitions for IXP2400/2800 based systems. - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _IXP2000_REGS_H_ -#define _IXP2000_REGS_H_ - -/* - * IXP2000 linux memory map: - * - * virt phys size - * fb000000 db000000 16M PCI CFG1 - * fc000000 da000000 16M PCI CFG0 - * fd000000 d8000000 16M PCI I/O - * fe[0-7]00000 8M per-platform mappings - * fe900000 80000000 1M SRAM #0 (first MB) - * fea00000 cb400000 1M SCRATCH ring get/put - * feb00000 c8000000 1M MSF - * fec00000 df000000 1M PCI CSRs - * fed00000 de000000 1M PCI CREG - * fee00000 d6000000 1M INTCTL - * fef00000 c0000000 1M CAP - */ - -/* - * Static I/O regions. - * - * Most of the registers are clumped in 4K regions spread throughout - * the 0xc0000000 -> 0xc0100000 address range, but we just map in - * the whole range using a single 1 MB section instead of small - * 4K pages. - * - * CAP stands for CSR Access Proxy. - * - * If you change the virtual address of this mapping, please propagate - * the change to arch/arm/kernel/debug.S, which hardcodes the virtual - * address of the UART located in this region. - */ - -#define IXP2000_CAP_PHYS_BASE 0xc0000000 -#define IXP2000_CAP_VIRT_BASE 0xfef00000 -#define IXP2000_CAP_SIZE 0x00100000 - -/* - * Addresses for specific on-chip peripherals. - */ -#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 -#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 -#define IXP2000_UART_PHYS_BASE 0xc0030000 -#define IXP2000_UART_VIRT_BASE 0xfef30000 -#define IXP2000_TIMER_VIRT_BASE 0xfef20000 -#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000 -#define IXP2000_GPIO_VIRT_BASE 0xfef10000 - -/* - * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual - * addresses of the INTCTL and PCI_CSR mappings are hardcoded in - * entry-macro.S, so if you ever change these please propagate - * the change. - */ -#define IXP2000_INTCTL_PHYS_BASE 0xd6000000 -#define IXP2000_INTCTL_VIRT_BASE 0xfee00000 -#define IXP2000_INTCTL_SIZE 0x00100000 - -#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 -#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 -#define IXP2000_PCI_CREG_SIZE 0x00100000 - -#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 -#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 -#define IXP2000_PCI_CSR_SIZE 0x00100000 - -#define IXP2000_MSF_PHYS_BASE 0xc8000000 -#define IXP2000_MSF_VIRT_BASE 0xfeb00000 -#define IXP2000_MSF_SIZE 0x00100000 - -#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000 -#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000 -#define IXP2000_SCRATCH_RING_SIZE 0x00100000 - -#define IXP2000_SRAM0_PHYS_BASE 0x80000000 -#define IXP2000_SRAM0_VIRT_BASE 0xfe900000 -#define IXP2000_SRAM0_SIZE 0x00100000 - -#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 -#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 -#define IXP2000_PCI_IO_SIZE 0x01000000 - -#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000 -#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000 -#define IXP2000_PCI_CFG0_SIZE 0x01000000 - -#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000 -#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 -#define IXP2000_PCI_CFG1_SIZE 0x01000000 - -/* - * Timers - */ -#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x))) -/* Timer control */ -#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00) -#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04) -#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08) -#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c) -/* Store initial value */ -#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10) -#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14) -#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18) -#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c) -/* Read current value */ -#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20) -#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24) -#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28) -#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c) -/* Clear associated timer interrupt */ -#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30) -#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34) -#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38) -#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c) -/* Timer watchdog enable for T4 */ -#define IXP2000_TWDE IXP2000_TIMER_REG(0x40) - -#define WDT_ENABLE 0x00000001 -#define TIMER_DIVIDER_256 0x00000008 -#define TIMER_ENABLE 0x00000080 -#define IRQ_MASK_TIMER1 (1 << 4) - -/* - * Interrupt controller registers - */ -#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x)) -#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08) -#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10) -#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10) -#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18) -#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14) -#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24) -#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) -#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) -#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) -#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) -#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) -#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) -#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) -#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) -#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) -#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) -#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) -#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0) -#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4) -#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8) -#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec) -#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100) -#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104) -#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108) -#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c) -#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) -#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) -#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) -#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) -#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) -#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) -#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) -#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) - -/* - * Mask of valid IRQs in the 32-bit IRQ register. We use - * this to mark certain IRQs as being invalid. - */ -#define IXP2000_VALID_IRQ_MASK 0x0f0fffff - -/* - * PCI config register access from core - */ -#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x)) -#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04) -#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10) -#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14) -#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18) - -/* - * PCI CSRs - */ -#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x)) - -/* - * PCI outbound interrupts - */ -#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30) -#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34) -/* - * PCI communications - */ -#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50) -#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54) -#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58) -#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C) -#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60) -#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64) -#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70) -#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74) - -/* - * DMA engines - */ -#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80) -#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84) -#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88) -#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C) -#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90) -#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94) -#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0) -#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4) -#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8) -#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC) -#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0) -#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4) -#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0) -#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4) -#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8) -#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC) -#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0) -#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4) -#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0) -/* - * Size masks for BARs - */ -#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC) -#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100) -/* - * Control and uEngine related - */ -#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C) -#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140) -#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148) -#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C) -#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150) -#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154) -/* - * Inbound PCI interrupt control - */ -#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158) -#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) - -#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ -#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */ -#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ - -/* These are from the IRQ register in the PCI ISR register */ -#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */ -#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ -#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ -#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ -#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */ - -#define IXP2000_PCI_RST_REL (1 << 2) -#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) -#define CFG_PCI_BOOT_HOST (1 << 2) -#define CFG_BOOT_PROM (1 << 1) - -/* - * SlowPort CSRs - * - * The slowport is used to access things like flash, SONET framer control - * ports, slave microprocessors, CPLDs, and others of chip memory mapped - * peripherals. - */ -#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x)) - -#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00) -#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04) -#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08) -#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c) -#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10) -#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14) -#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18) -#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C) -#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20) -#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24) -#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28) - -/* - * CCR values. - * The CCR configures the clock division for the slowport interface. - */ -#define SLOWPORT_CCR_DIV_1 0x00 -#define SLOWPORT_CCR_DIV_2 0x01 -#define SLOWPORT_CCR_DIV_4 0x02 -#define SLOWPORT_CCR_DIV_6 0x03 -#define SLOWPORT_CCR_DIV_8 0x04 -#define SLOWPORT_CCR_DIV_10 0x05 -#define SLOWPORT_CCR_DIV_12 0x06 -#define SLOWPORT_CCR_DIV_14 0x07 -#define SLOWPORT_CCR_DIV_16 0x08 -#define SLOWPORT_CCR_DIV_18 0x09 -#define SLOWPORT_CCR_DIV_20 0x0a -#define SLOWPORT_CCR_DIV_22 0x0b -#define SLOWPORT_CCR_DIV_24 0x0c -#define SLOWPORT_CCR_DIV_26 0x0d -#define SLOWPORT_CCR_DIV_28 0x0e -#define SLOWPORT_CCR_DIV_30 0x0f - -/* - * PCR values. PCR configure the mode of the interface. - */ -#define SLOWPORT_MODE_FLASH 0x00 -#define SLOWPORT_MODE_LUCENT 0x01 -#define SLOWPORT_MODE_PMC_SIERRA 0x02 -#define SLOWPORT_MODE_INTEL_UP 0x03 -#define SLOWPORT_MODE_MOTOROLA_UP 0x04 - -/* - * ADC values. Defines data and address bus widths. - */ -#define SLOWPORT_ADDR_WIDTH_8 0x00 -#define SLOWPORT_ADDR_WIDTH_16 0x01 -#define SLOWPORT_ADDR_WIDTH_24 0x02 -#define SLOWPORT_ADDR_WIDTH_32 0x03 -#define SLOWPORT_DATA_WIDTH_8 0x00 -#define SLOWPORT_DATA_WIDTH_16 0x10 -#define SLOWPORT_DATA_WIDTH_24 0x20 -#define SLOWPORT_DATA_WIDTH_32 0x30 - -/* - * Masks and shifts for various fields in the WTC and RTC registers. - */ -#define SLOWPORT_WRTC_MASK_HD 0x0003 -#define SLOWPORT_WRTC_MASK_PW 0x003c -#define SLOWPORT_WRTC_MASK_SU 0x03c0 - -#define SLOWPORT_WRTC_SHIFT_HD 0x00 -#define SLOWPORT_WRTC_SHIFT_SU 0x02 -#define SLOWPORT_WRTC_SHFIT_PW 0x06 - - -/* - * GPIO registers & GPIO interface. - */ -#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x))) -#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00) -#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04) -#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08) -#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c) -#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10) -#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14) -#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18) -#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c) -#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20) -#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24) -#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28) -#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c) -#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30) -#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34) -#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38) -#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c) -#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40) - -/* - * "Global" registers...whatever that's supposed to mean. - */ -#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00) -#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x)) - -#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000 -#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000 -#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00 -#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200 -#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100 -#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000 -#define IXP2000_MAJ_REV_MASK 0x000000F0 -#define IXP2000_MIN_REV_MASK 0x0000000F -#define IXP2000_PROD_ID_MASK 0xFFFFFFFF - -#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00) -#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) -#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) -#define IXP2000_RESET0 GLOBAL_REG(0x0c) -#define IXP2000_RESET1 GLOBAL_REG(0x10) -#define IXP2000_CCR GLOBAL_REG(0x14) -#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18) - -#define RSTALL (1 << 16) -#define WDT_RESET_ENABLE 0x01000000 - - -/* - * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF - * units, but the registers that differ between the two don't overlap, - * so we can have one register list for both. - */ -#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x))) -#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000) -#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004) -#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008) -#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c) -#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010) -#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014) -#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018) -#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024) -#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028) -#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c) -#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040) -#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044) -#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048) -#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058) -#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060) -#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064) -#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068) -#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070) -#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070) -#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080) -#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084) -#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088) -#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c) -#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090) -#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094) -#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098) -#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c) -#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0) -#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4) -#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8) -#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000) -#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400) - - -#endif /* _IXP2000_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h deleted file mode 100644 index 5f0c4fd4076a..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/memory.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/memory.h - * - * Copyright (c) 2002 Intel Corp. - * Copyright (c) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#define PLAT_PHYS_OFFSET UL(0x00000000) - -#include <mach/ixp2000-regs.h> - -#define IXP2000_PCI_SDRAM_OFFSET (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0) - -#define __phys_to_bus(x) ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) -#define __bus_to_phys(x) ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) - -#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) -#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) -#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) -#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) - -#endif - diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h deleted file mode 100644 index bb0f8dcf9ee1..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/platform.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/platform.h - * - * Various bits of code used by platform-level code. - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - - -#ifndef __ASSEMBLY__ - -static inline unsigned long ixp2000_reg_read(volatile void *reg) -{ - return *((volatile unsigned long *)reg); -} - -static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) -{ - *((volatile unsigned long *)reg) = val; -} - -/* - * On the IXP2400, we can't use XCB=000 due to chip bugs. We use - * XCB=101 instead, but that makes all I/O accesses bufferable. This - * is not a problem in general, but we do have to be slightly more - * careful because I/O writes are no longer automatically flushed out - * of the write buffer. - * - * In cases where we want to make sure that a write has been flushed - * out of the write buffer before we proceed, for example when masking - * a device interrupt before re-enabling IRQs in CPSR, we can use this - * function, ixp2000_reg_wrb, which performs a write, a readback, and - * issues a dummy instruction dependent on the value of the readback - * (mov rX, rX) to make sure that the readback has completed before we - * continue. - */ -static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) -{ - unsigned long dummy; - - *((volatile unsigned long *)reg) = val; - - dummy = *((volatile unsigned long *)reg); - __asm__ __volatile__("mov %0, %0" : "+r" (dummy)); -} - -/* - * Boards may multiplex different devices on the 2nd channel of - * the slowport interface that each need different configuration - * settings. For example, the IXDP2400 uses channel 2 on the interface - * to access the CPLD, the switch fabric card, and the media card. Each - * one needs a different mode so drivers must save/restore the mode - * before and after each operation. - * - * acquire_slowport(&your_config); - * ... - * do slowport operations - * ... - * release_slowport(); - * - * Note that while you have the slowport, you are holding a spinlock, - * so your code should be written as if you explicitly acquired a lock. - * - * The configuration only affects device 2 on the slowport, so the - * MTD map driver does not acquire/release the slowport. - */ -struct slowport_cfg { - unsigned long CCR; /* Clock divide */ - unsigned long WTC; /* Write Timing Control */ - unsigned long RTC; /* Read Timing Control */ - unsigned long PCR; /* Protocol Control Register */ - unsigned long ADC; /* Address/Data Width Control */ -}; - - -void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *); -void ixp2000_release_slowport(struct slowport_cfg *); - -/* - * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires - * tweaking of addresses in the MTD driver. - */ -static inline unsigned ixp2000_has_broken_slowport(void) -{ - unsigned long id = *IXP2000_PRODUCT_ID; - unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK | - IXP2000_MIN_PROD_TYPE_MASK); - return (((id_prod == - /* fixed in IXP2400-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2400)) && - ((id & IXP2000_MAJ_REV_MASK) == 0)) || - ((id_prod == - /* fixed in IXP2800-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2800)) && - ((id & IXP2000_MAJ_REV_MASK) == 0)) || - ((id_prod == - /* fixed in IXP2850-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2850)) && - ((id & IXP2000_MAJ_REV_MASK) == 0))); -} - -static inline unsigned int ixp2000_has_flash(void) -{ - return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM)); -} - -static inline unsigned int ixp2000_is_pcimaster(void) -{ - return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST)); -} - -void ixp2000_map_io(void); -void ixp2000_uart_init(void); -void ixp2000_init_irq(void); -void ixp2000_init_time(unsigned long); -void ixp2000_restart(char, const char *); -unsigned long ixp2000_gettimeoffset(void); - -struct pci_sys_data; - -u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where); -void ixp2000_pci_preinit(void); -int ixp2000_pci_setup(int, struct pci_sys_data*); -struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*); -int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *); -int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32); - -/* - * Several of the IXP2000 systems have banked flash so we need to extend the - * flash_platform_data structure with some private pointers - */ -struct ixp2000_flash_data { - struct flash_platform_data *platform_data; - int nr_banks; - unsigned long (*bank_setup)(unsigned long); -}; - -struct ixp2000_i2c_pins { - unsigned long sda_pin; - unsigned long scl_pin; -}; - - -#endif /* !__ASSEMBLY__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h deleted file mode 100644 index 835e659f93d4..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/timex.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/timex.h - * - * IXP2000 architecture timex specifications - */ - - -/* - * Default clock is 50MHz APB, but platform code can override this - */ -#define CLOCK_TICK_RATE 50000000 - - diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h deleted file mode 100644 index ce363087df78..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/uncompress.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/uncompress.h - * - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2002 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/serial_reg.h> - -#define UART_BASE 0xc0030000 - -#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x)) - -#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */ -#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/ -#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/ -#define UARTIER PHYS(0x04) /* Interrupt enable reg */ -#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/ -#define UARTLCR PHYS(0x0c) /* Control reg */ -#define UARTSR PHYS(0x14) /* Status reg */ - - -static inline void putc(int c) -{ - int j = 0x1000; - - while (--j && !(*UARTSR & UART_LSR_THRE)) - barrier(); - - *UARTDR = c; -} - -static inline void flush(void) -{ -} - -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c deleted file mode 100644 index 915ad49e3b8f..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2400.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2400.c - * - * IXDP2400 platform support - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/device.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/flash.h> -#include <asm/mach/arch.h> - -/************************************************************************* - * IXDP2400 timer tick - *************************************************************************/ -static void __init ixdp2400_timer_init(void) -{ - int numerator, denominator; - int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8}; - - numerator = (*(IXDP2400_CPLD_SYS_CLK_M) & 0xFF) *2; - denominator = denom_array[(*(IXDP2400_CPLD_SYS_CLK_N) & 0x7)]; - - ixp2000_init_time(((3125000 * numerator) / (denominator)) / 2); -} - -static struct sys_timer ixdp2400_timer = { - .init = ixdp2400_timer_init, - .offset = ixp2000_gettimeoffset, -}; - -/************************************************************************* - * IXDP2400 PCI - *************************************************************************/ -void __init ixdp2400_pci_preinit(void) -{ - ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000); - ixp2000_pci_preinit(); - pcibios_setup("firmware"); -} - -int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0xe0000000; - - ixp2000_pci_setup(nr, sys); - - return 1; -} - -static int __init ixdp2400_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - if (ixdp2x00_master_npu()) { - - /* - * Root bus devices. Slave NPU is only one with interrupt. - * Everything else, we just return -1 b/c nothing else - * on the root bus has interrupts. - */ - if(!dev->bus->self) { - if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) - return IRQ_IXDP2400_INGRESS_NPU; - - return -1; - } - - /* - * Bridge behind the PMC slot. - * NOTE: Only INTA from the PMC slot is routed. VERY BAD. - */ - if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && - dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && - !dev->bus->parent->self->bus->parent) - return IRQ_IXDP2400_PMC; - - /* - * Device behind the first bridge - */ - if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { - switch(dev->devfn) { - case IXDP2400_MASTER_ENET_DEVFN: - return IRQ_IXDP2400_ENET; - - case IXDP2400_MEDIA_DEVFN: - return IRQ_IXDP2400_MEDIA_PCI; - - case IXDP2400_SWITCH_FABRIC_DEVFN: - return IRQ_IXDP2400_SF_PCI; - - case IXDP2X00_PMC_DEVFN: - return IRQ_IXDP2400_PMC; - } - } - - return -1; - } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ -} - - -static void ixdp2400_pci_postinit(void) -{ - struct pci_dev *dev; - - if (ixdp2x00_master_npu()) { - dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - } else { - dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - - ixdp2x00_slave_pci_postinit(); - } -} - -static struct hw_pci ixdp2400_pci __initdata = { - .nr_controllers = 1, - .setup = ixdp2400_pci_setup, - .preinit = ixdp2400_pci_preinit, - .postinit = ixdp2400_pci_postinit, - .scan = ixp2000_pci_scan_bus, - .map_irq = ixdp2400_pci_map_irq, -}; - -int __init ixdp2400_pci_init(void) -{ - if (machine_is_ixdp2400()) - pci_common_init(&ixdp2400_pci); - - return 0; -} - -subsys_initcall(ixdp2400_pci_init); - -void __init ixdp2400_init_irq(void) -{ - ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS); -} - -MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x00_map_io, - .init_irq = ixdp2400_init_irq, - .timer = &ixdp2400_timer, - .init_machine = ixdp2x00_init_machine, - .restart = ixp2000_restart, -MACHINE_END - diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c deleted file mode 100644 index a9f1819ea049..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2800.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2800.c - * - * IXDP2800 platform support - * - * Original Author: Jeffrey Daly <jeffrey.daly@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/device.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/flash.h> -#include <asm/mach/arch.h> - -/************************************************************************* - * IXDP2800 timer tick - *************************************************************************/ - -static void __init ixdp2800_timer_init(void) -{ - ixp2000_init_time(50000000); -} - -static struct sys_timer ixdp2800_timer = { - .init = ixdp2800_timer_init, - .offset = ixp2000_gettimeoffset, -}; - -/************************************************************************* - * IXDP2800 PCI - *************************************************************************/ -static void __init ixdp2800_slave_disable_pci_master(void) -{ - *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -} - -static void __init ixdp2800_master_wait_for_slave(void) -{ - volatile u32 *addr; - - printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure " - "its BAR sizes\n"); - - addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, - PCI_BASE_ADDRESS_1); - do { - *addr = 0xffffffff; - cpu_relax(); - } while (*addr != 0xfe000008); - - addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, - PCI_BASE_ADDRESS_2); - do { - *addr = 0xffffffff; - cpu_relax(); - } while (*addr != 0xc0000008); - - /* - * Configure the slave's SDRAM BAR by hand. - */ - *addr = 0x40000008; -} - -static void __init ixdp2800_slave_wait_for_master_enable(void) -{ - printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n"); - - while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0) - cpu_relax(); -} - -void __init ixdp2800_pci_preinit(void) -{ - printk("ixdp2x00_pci_preinit called\n"); - - *IXP2000_PCI_ADDR_EXT = 0x0001e000; - - if (!ixdp2x00_master_npu()) - ixdp2800_slave_disable_pci_master(); - - *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff; - *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff; - - ixp2000_pci_preinit(); - - if (ixdp2x00_master_npu()) { - /* - * Wait until the slave set its SRAM/SDRAM BAR sizes - * correctly before we proceed to scan and enumerate - * the bus. - */ - ixdp2800_master_wait_for_slave(); - - /* - * We configure the SDRAM BARs by hand because they - * are 1G and fall outside of the regular allocated - * PCI address space. - */ - *IXP2000_PCI_SDRAM_BAR = 0x00000008; - } else { - /* - * Wait for the master to complete scanning the bus - * and assigning resources before we proceed to scan - * the bus ourselves. Set pci=firmware to honor the - * master's resource assignment. - */ - ixdp2800_slave_wait_for_master_enable(); - pcibios_setup("firmware"); - } -} - -/* - * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside - * of the regular PCI window, because there's only 512M of outbound PCI - * memory window on each IXP, while we need 1G for each of the BARs. - */ -static void __devinit ixp2800_pci_fixup(struct pci_dev *dev) -{ - if (machine_is_ixdp2800()) { - dev->resource[2].start = 0; - dev->resource[2].end = 0; - dev->resource[2].flags = 0; - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup); - -static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0x00000000; - - ixp2000_pci_setup(nr, sys); - - return 1; -} - -static int __init ixdp2800_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - if (ixdp2x00_master_npu()) { - - /* - * Root bus devices. Slave NPU is only one with interrupt. - * Everything else, we just return -1 which is invalid. - */ - if(!dev->bus->self) { - if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) - return IRQ_IXDP2800_INGRESS_NPU; - - return -1; - } - - /* - * Bridge behind the PMC slot. - */ - if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && - dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && - !dev->bus->parent->self->bus->parent) - return IRQ_IXDP2800_PMC; - - /* - * Device behind the first bridge - */ - if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { - switch(dev->devfn) { - case IXDP2X00_PMC_DEVFN: - return IRQ_IXDP2800_PMC; - - case IXDP2800_MASTER_ENET_DEVFN: - return IRQ_IXDP2800_EGRESS_ENET; - - case IXDP2800_SWITCH_FABRIC_DEVFN: - return IRQ_IXDP2800_FABRIC; - } - } - - return -1; - } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ -} - -static void __init ixdp2800_master_enable_slave(void) -{ - volatile u32 *addr; - - printk(KERN_INFO "IXDP2800: enabling slave NPU\n"); - - addr = (volatile u32 *)ixp2000_pci_config_addr(0, - IXDP2X00_SLAVE_NPU_DEVFN, - PCI_COMMAND); - - *addr |= PCI_COMMAND_MASTER; -} - -static void __init ixdp2800_master_wait_for_slave_bus_scan(void) -{ - volatile u32 *addr; - - printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n"); - - addr = (volatile u32 *)ixp2000_pci_config_addr(0, - IXDP2X00_SLAVE_NPU_DEVFN, - PCI_COMMAND); - while ((*addr & PCI_COMMAND_MEMORY) == 0) - cpu_relax(); -} - -static void __init ixdp2800_slave_signal_bus_scan_completion(void) -{ - printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n"); - *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY; -} - -static void __init ixdp2800_pci_postinit(void) -{ - if (!ixdp2x00_master_npu()) { - ixdp2x00_slave_pci_postinit(); - ixdp2800_slave_signal_bus_scan_completion(); - } -} - -struct __initdata hw_pci ixdp2800_pci __initdata = { - .nr_controllers = 1, - .setup = ixdp2800_pci_setup, - .preinit = ixdp2800_pci_preinit, - .postinit = ixdp2800_pci_postinit, - .scan = ixp2000_pci_scan_bus, - .map_irq = ixdp2800_pci_map_irq, -}; - -int __init ixdp2800_pci_init(void) -{ - if (machine_is_ixdp2800()) { - struct pci_dev *dev; - - pci_common_init(&ixdp2800_pci); - if (ixdp2x00_master_npu()) { - dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - - ixdp2800_master_enable_slave(); - ixdp2800_master_wait_for_slave_bus_scan(); - } else { - dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - } - } - - return 0; -} - -subsys_initcall(ixdp2800_pci_init); - -void __init ixdp2800_init_irq(void) -{ - ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS); -} - -MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x00_map_io, - .init_irq = ixdp2800_init_irq, - .timer = &ixdp2800_timer, - .init_machine = ixdp2x00_init_machine, - .restart = ixp2000_restart, -MACHINE_END - diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c deleted file mode 100644 index 421e38dc0fac..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2x00.c - * - * Code common to IXDP2400 and IXDP2800 platforms. - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/flash.h> -#include <asm/mach/arch.h> - -#include <mach/gpio-ixp2000.h> - -/************************************************************************* - * IXDP2x00 IRQ Initialization - *************************************************************************/ -static volatile unsigned long *board_irq_mask; -static volatile unsigned long *board_irq_stat; -static unsigned long board_irq_count; - -#ifdef CONFIG_ARCH_IXDP2400 -/* - * Slowport configuration for accessing CPLD registers on IXDP2x00 - */ -static struct slowport_cfg slowport_cpld_cfg = { - .CCR = SLOWPORT_CCR_DIV_2, - .WTC = 0x00000070, - .RTC = 0x00000070, - .PCR = SLOWPORT_MODE_FLASH, - .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8 -}; -#endif - -static void ixdp2x00_irq_mask(struct irq_data *d) -{ - unsigned long dummy; - static struct slowport_cfg old_cfg; - - /* - * This is ugly in common code but really don't know - * of a better way to handle it. :( - */ -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); -#endif - - dummy = *board_irq_mask; - dummy |= IXP2000_BOARD_IRQ_MASK(d->irq); - ixp2000_reg_wrb(board_irq_mask, dummy); - -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_release_slowport(&old_cfg); -#endif -} - -static void ixdp2x00_irq_unmask(struct irq_data *d) -{ - unsigned long dummy; - static struct slowport_cfg old_cfg; - -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); -#endif - - dummy = *board_irq_mask; - dummy &= ~IXP2000_BOARD_IRQ_MASK(d->irq); - ixp2000_reg_wrb(board_irq_mask, dummy); - - if (machine_is_ixdp2400()) - ixp2000_release_slowport(&old_cfg); -} - -static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - volatile u32 ex_interrupt = 0; - static struct slowport_cfg old_cfg; - int i; - - desc->irq_data.chip->irq_mask(&desc->irq_data); - -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); -#endif - ex_interrupt = *board_irq_stat & 0xff; - if (machine_is_ixdp2400()) - ixp2000_release_slowport(&old_cfg); - - if(!ex_interrupt) { - printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n"); - return; - } - - for(i = 0; i < board_irq_count; i++) { - if(ex_interrupt & (1 << i)) { - int cpld_irq = IXP2000_BOARD_IRQ(0) + i; - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2x00_cpld_irq_chip = { - .irq_ack = ixdp2x00_irq_mask, - .irq_mask = ixdp2x00_irq_mask, - .irq_unmask = ixdp2x00_irq_unmask -}; - -void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs) -{ - unsigned int irq; - - ixp2000_init_irq(); - - if (!ixdp2x00_master_npu()) - return; - - board_irq_stat = stat_reg; - board_irq_mask = mask_reg; - board_irq_count = nr_of_irqs; - - *board_irq_mask = 0xffffffff; - - for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { - irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - /* Hook into PCI interrupt */ - irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); -} - -/************************************************************************* - * IXDP2x00 memory map - *************************************************************************/ -static struct map_desc ixdp2x00_io_desc __initdata = { - .virtual = IXDP2X00_VIRT_CPLD_BASE, - .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE), - .length = IXDP2X00_CPLD_SIZE, - .type = MT_DEVICE -}; - -void __init ixdp2x00_map_io(void) -{ - ixp2000_map_io(); - - iotable_init(&ixdp2x00_io_desc, 1); -} - -/************************************************************************* - * IXDP2x00-common PCI init - * - * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board - * contains two NPUs (ingress and egress) connected over PCI, both running - * instances of the kernel. So far so good. Peers on the PCI bus running - * Linux is a common design in telecom systems. The problem is that instead - * of all the devices being controlled by a single host, different - * devices are controlled by different NPUs on the same bus, leading to - * multiple hosts on the bus. The exact bus layout looks like: - * - * Bus 0 - * Master NPU <-------------------+-------------------> Slave NPU - * | - * | - * P2P - * | - * - * Bus 1 | - * <--+------+---------+---------+------+--> - * | | | | | - * | | | | | - * ... Dev PMC Media Eth0 Eth1 ... - * - * The master controls all but Eth1, which is controlled by the - * slave. What this means is that the both the master and the slave - * have to scan the bus, but only one of them can enumerate the bus. - * In addition, after the bus is scanned, each kernel must remove - * the device(s) it does not control from the PCI dev list otherwise - * a driver on each NPU will try to manage it and we will have horrible - * conflicts. Oh..and the slave NPU needs to see the master NPU - * for Intel's drivers to work properly. Closed source drivers... - * - * The way we deal with this is fairly simple but ugly: - * - * 1) Let master scan and enumerate the bus completely. - * 2) Master deletes Eth1 from device list. - * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave) - * from device list. - * 4) Find HW designers and LART them. - * - * The boards also do not do normal PCI IRQ routing, or any sort of - * sensical swizzling, so we just need to check where on the bus a - * device sits and figure out to which CPLD pin the interrupt is routed. - * See ixdp2[48]00.c files. - * - *************************************************************************/ -void ixdp2x00_slave_pci_postinit(void) -{ - struct pci_dev *dev; - - /* - * Remove PMC device is there is one - */ - if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) { - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - } - - dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); -} - -/************************************************************************** - * IXDP2x00 Machine Setup - *************************************************************************/ -static struct flash_platform_data ixdp2x00_platform_data = { - .map_name = "cfi_probe", - .width = 1, -}; - -static struct ixp2000_flash_data ixdp2x00_flash_data = { - .platform_data = &ixdp2x00_platform_data, - .nr_banks = 1 -}; - -static struct resource ixdp2x00_flash_resource = { - .start = 0xc4000000, - .end = 0xc4000000 + 0x00ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x00_flash = { - .name = "IXP2000-Flash", - .id = 0, - .dev = { - .platform_data = &ixdp2x00_flash_data, - }, - .num_resources = 1, - .resource = &ixdp2x00_flash_resource, -}; - -static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = { - .sda_pin = IXDP2X00_GPIO_SDA, - .scl_pin = IXDP2X00_GPIO_SCL, -}; - -static struct platform_device ixdp2x00_i2c_controller = { - .name = "IXP2000-I2C", - .id = 0, - .dev = { - .platform_data = &ixdp2x00_i2c_gpio_pins, - }, - .num_resources = 0 -}; - -static struct platform_device *ixdp2x00_devices[] __initdata = { - &ixdp2x00_flash, - &ixdp2x00_i2c_controller -}; - -void __init ixdp2x00_init_machine(void) -{ - gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1); - gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT); - - platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices)); - ixp2000_uart_init(); -} - diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c deleted file mode 100644 index 5196c39cdba4..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ /dev/null @@ -1,483 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2x01.c - * - * Code common to Intel IXDP2401 and IXDP2801 platforms - * - * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002-2003 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach/flash.h> - -/************************************************************************* - * IXDP2x01 IRQ Handling - *************************************************************************/ -static void ixdp2x01_irq_mask(struct irq_data *d) -{ - ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG, - IXP2000_BOARD_IRQ_MASK(d->irq)); -} - -static void ixdp2x01_irq_unmask(struct irq_data *d) -{ - ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG, - IXP2000_BOARD_IRQ_MASK(d->irq)); -} - -static u32 valid_irq_mask; - -static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 ex_interrupt; - int i; - - desc->irq_data.chip->irq_mask(&desc->irq_data); - - ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask; - - if (!ex_interrupt) { - printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n"); - return; - } - - for (i = 0; i < IXP2000_BOARD_IRQS; i++) { - if (ex_interrupt & (1 << i)) { - int cpld_irq = IXP2000_BOARD_IRQ(0) + i; - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2x01_irq_chip = { - .irq_mask = ixdp2x01_irq_mask, - .irq_ack = ixdp2x01_irq_mask, - .irq_unmask = ixdp2x01_irq_unmask -}; - -/* - * We only do anything if we are the master NPU on the board. - * The slave NPU only has the ethernet chip going directly to - * the PCIB interrupt input. - */ -void __init ixdp2x01_init_irq(void) -{ - int irq = 0; - - /* initialize chip specific interrupts */ - ixp2000_init_irq(); - - if (machine_is_ixdp2401()) - valid_irq_mask = IXDP2401_VALID_IRQ_MASK; - else - valid_irq_mask = IXDP2801_VALID_IRQ_MASK; - - /* Mask all interrupts from CPLD, disable simulation */ - ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff); - ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0); - - for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { - if (irq & valid_irq_mask) { - irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } else { - set_irq_flags(irq, 0); - } - } - - /* Hook into PCI interrupts */ - irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); -} - - -/************************************************************************* - * IXDP2x01 memory map - *************************************************************************/ -static struct map_desc ixdp2x01_io_desc __initdata = { - .virtual = IXDP2X01_VIRT_CPLD_BASE, - .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE), - .length = IXDP2X01_CPLD_REGION_SIZE, - .type = MT_DEVICE -}; - -static void __init ixdp2x01_map_io(void) -{ - ixp2000_map_io(); - iotable_init(&ixdp2x01_io_desc, 1); -} - - -/************************************************************************* - * IXDP2x01 serial ports - *************************************************************************/ -static struct plat_serial8250_port ixdp2x01_serial_port1[] = { - { - .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE, - .membase = (char *)IXDP2X01_UART1_VIRT_BASE, - .irq = IRQ_IXDP2X01_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM32, - .regshift = 2, - .uartclk = IXDP2X01_UART_CLK, - }, - { } -}; - -static struct resource ixdp2x01_uart_resource1 = { - .start = IXDP2X01_UART1_PHYS_BASE, - .end = IXDP2X01_UART1_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x01_serial_device1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = ixdp2x01_serial_port1, - }, - .num_resources = 1, - .resource = &ixdp2x01_uart_resource1, -}; - -static struct plat_serial8250_port ixdp2x01_serial_port2[] = { - { - .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE, - .membase = (char *)IXDP2X01_UART2_VIRT_BASE, - .irq = IRQ_IXDP2X01_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM32, - .regshift = 2, - .uartclk = IXDP2X01_UART_CLK, - }, - { } -}; - -static struct resource ixdp2x01_uart_resource2 = { - .start = IXDP2X01_UART2_PHYS_BASE, - .end = IXDP2X01_UART2_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x01_serial_device2 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = ixdp2x01_serial_port2, - }, - .num_resources = 1, - .resource = &ixdp2x01_uart_resource2, -}; - -static void ixdp2x01_uart_init(void) -{ - platform_device_register(&ixdp2x01_serial_device1); - platform_device_register(&ixdp2x01_serial_device2); -} - - -/************************************************************************* - * IXDP2x01 timer tick configuration - *************************************************************************/ -static unsigned int ixdp2x01_clock; - -static int __init ixdp2x01_clock_setup(char *str) -{ - ixdp2x01_clock = simple_strtoul(str, NULL, 10); - - return 1; -} - -__setup("ixdp2x01_clock=", ixdp2x01_clock_setup); - -static void __init ixdp2x01_timer_init(void) -{ - if (!ixdp2x01_clock) - ixdp2x01_clock = 50000000; - - ixp2000_init_time(ixdp2x01_clock); -} - -static struct sys_timer ixdp2x01_timer = { - .init = ixdp2x01_timer_init, - .offset = ixp2000_gettimeoffset, -}; - -/************************************************************************* - * IXDP2x01 PCI - *************************************************************************/ -void __init ixdp2x01_pci_preinit(void) -{ - ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000); - ixp2000_pci_preinit(); - pcibios_setup("firmware"); -} - -#define DEVPIN(dev, pin) ((pin) | ((dev) << 3)) - -static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - u8 bus = dev->bus->number; - u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin); - struct pci_bus *tmp_bus = dev->bus; - - /* Primary bus, no interrupts here */ - if (bus == 0) { - return -1; - } - - /* Lookup first leaf in bus tree */ - while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) { - tmp_bus = tmp_bus->parent; - } - - /* Select between known bridges */ - switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) { - /* Device is located after first MB bridge */ - case 0x0008: - if (tmp_bus == dev->bus) { - /* Device is located directly after first MB bridge */ - switch (devpin) { - case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ - if (machine_is_ixdp2401()) - return IRQ_IXDP2401_INTA_82546; - return -1; - case DEVPIN(1, 2): /* Onboard 82546 ch 1 */ - if (machine_is_ixdp2401()) - return IRQ_IXDP2401_INTB_82546; - return -1; - case DEVPIN(0, 1): /* PMC INTA# */ - return IRQ_IXDP2X01_SPCI_PMC_INTA; - case DEVPIN(0, 2): /* PMC INTB# */ - return IRQ_IXDP2X01_SPCI_PMC_INTB; - case DEVPIN(0, 3): /* PMC INTC# */ - return IRQ_IXDP2X01_SPCI_PMC_INTC; - case DEVPIN(0, 4): /* PMC INTD# */ - return IRQ_IXDP2X01_SPCI_PMC_INTD; - } - } - break; - case 0x0010: - if (tmp_bus == dev->bus) { - /* Device is located directly after second MB bridge */ - /* Secondary bus of second bridge */ - switch (devpin) { - case DEVPIN(0, 1): /* DB#0 */ - return IRQ_IXDP2X01_SPCI_DB_0; - case DEVPIN(1, 1): /* DB#1 */ - return IRQ_IXDP2X01_SPCI_DB_1; - } - } else { - /* Device is located indirectly after second MB bridge */ - /* Not supported now */ - } - break; - } - - return -1; -} - - -static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0xe0000000; - - if (machine_is_ixdp2801() || machine_is_ixdp28x5()) - sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16); - - return ixp2000_pci_setup(nr, sys); -} - -struct hw_pci ixdp2x01_pci __initdata = { - .nr_controllers = 1, - .setup = ixdp2x01_pci_setup, - .preinit = ixdp2x01_pci_preinit, - .scan = ixp2000_pci_scan_bus, - .map_irq = ixdp2x01_pci_map_irq, -}; - -int __init ixdp2x01_pci_init(void) -{ - if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\ - machine_is_ixdp28x5()) - pci_common_init(&ixdp2x01_pci); - - return 0; -} - -subsys_initcall(ixdp2x01_pci_init); - -/************************************************************************* - * IXDP2x01 Machine Initialization - *************************************************************************/ -static struct flash_platform_data ixdp2x01_flash_platform_data = { - .map_name = "cfi_probe", - .width = 1, -}; - -static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs) -{ - ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG, - ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN)); - return (ofs & IXDP2X01_FLASH_WINDOW_MASK); -} - -static struct ixp2000_flash_data ixdp2x01_flash_data = { - .platform_data = &ixdp2x01_flash_platform_data, - .bank_setup = ixdp2x01_flash_bank_setup -}; - -static struct resource ixdp2x01_flash_resource = { - .start = 0xc4000000, - .end = 0xc4000000 + 0x01ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x01_flash = { - .name = "IXP2000-Flash", - .id = 0, - .dev = { - .platform_data = &ixdp2x01_flash_data, - }, - .num_resources = 1, - .resource = &ixdp2x01_flash_resource, -}; - -static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = { - .sda_pin = IXDP2X01_GPIO_SDA, - .scl_pin = IXDP2X01_GPIO_SCL, -}; - -static struct platform_device ixdp2x01_i2c_controller = { - .name = "IXP2000-I2C", - .id = 0, - .dev = { - .platform_data = &ixdp2x01_i2c_gpio_pins, - }, - .num_resources = 0 -}; - -static struct platform_device *ixdp2x01_devices[] __initdata = { - &ixdp2x01_flash, - &ixdp2x01_i2c_controller -}; - -static void __init ixdp2x01_init_machine(void) -{ - ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG, - (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN)); - - ixdp2x01_flash_data.nr_banks = - ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1); - - platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices)); - ixp2000_uart_init(); - ixdp2x01_uart_init(); -} - -static void ixdp2401_restart(char mode, const char *cmd) -{ - /* - * Reset flash banking register so that we are pointing at - * RedBoot bank. - */ - ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, - ((0 >> IXDP2X01_FLASH_WINDOW_BITS) - | IXDP2X01_CPLD_FLASH_INTERN)); - ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff); - - ixp2000_restart(mode, cmd); -} - -static void ixdp280x_restart(char mode, const char *cmd) -{ - /* - * On IXDP2801 we need to write this magic sequence to the CPLD - * to cause a complete reset of the CPU and all external devices - * and move the flash bank register back to 0. - */ - unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; - - reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); - ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg); - ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000); - - ixp2000_restart(mode, cmd); -} - -#ifdef CONFIG_ARCH_IXDP2401 -MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x01_map_io, - .init_irq = ixdp2x01_init_irq, - .timer = &ixdp2x01_timer, - .init_machine = ixdp2x01_init_machine, - .restart = ixdp2401_restart, -MACHINE_END -#endif - -#ifdef CONFIG_ARCH_IXDP2801 -MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x01_map_io, - .init_irq = ixdp2x01_init_irq, - .timer = &ixdp2x01_timer, - .init_machine = ixdp2x01_init_machine, - .restart = ixdp280x_restart, -MACHINE_END - -/* - * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel - * changed the machine ID in the bootloader - */ -MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x01_map_io, - .init_irq = ixdp2x01_init_irq, - .timer = &ixdp2x01_timer, - .init_machine = ixdp2x01_init_machine, - .restart = ixdp280x_restart, -MACHINE_END -#endif - - diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c deleted file mode 100644 index 9c02de932fac..000000000000 --- a/arch/arm/mach-ixp2000/pci.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * arch/arm/mach-ixp2000/pci.c - * - * PCI routines for IXDP2400/IXDP2800 boards - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintained by: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <mach/hardware.h> - -#include <asm/mach/pci.h> - -static volatile int pci_master_aborts = 0; - -static int clear_master_aborts(void); - -u32 * -ixp2000_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where) -{ - u32 *paddress; - - if (PCI_SLOT(devfn) > 7) - return 0; - - /* Must be dword aligned */ - where &= ~3; - - /* - * For top bus, generate type 0, else type 1 - */ - if (!bus_nr) { - /* only bits[23:16] are used for IDSEL */ - paddress = (u32 *) (IXP2000_PCI_CFG0_VIRT_BASE - | (1 << (PCI_SLOT(devfn) + 16)) - | (PCI_FUNC(devfn) << 8) | where); - } else { - paddress = (u32 *) (IXP2000_PCI_CFG1_VIRT_BASE - | (bus_nr << 16) - | (PCI_SLOT(devfn) << 11) - | (PCI_FUNC(devfn) << 8) | where); - } - - return paddress; -} - -/* - * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. - * 0 and 3 are not valid indexes... - */ -static u32 bytemask[] = { - /*0*/ 0, - /*1*/ 0xff, - /*2*/ 0xffff, - /*3*/ 0, - /*4*/ 0xffffffff, -}; - - -int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - u32 n; - u32 *addr; - - n = where % 4; - - addr = ixp2000_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - - pci_master_aborts = 0; - *value = (*addr >> (8*n)) & bytemask[size]; - if (pci_master_aborts) { - pci_master_aborts = 0; - *value = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return PCIBIOS_SUCCESSFUL; -} - -/* - * We don't do error checks by calling clear_master_aborts() b/c the - * assumption is that the caller did a read first to make sure a device - * exists. - */ -int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - u32 mask; - u32 *addr; - u32 temp; - - mask = ~(bytemask[size] << ((where % 0x4) * 8)); - addr = ixp2000_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - temp = (u32) (value) << ((where % 0x4) * 8); - *addr = (*addr & mask) | temp; - - clear_master_aborts(); - - return PCIBIOS_SUCCESSFUL; -} - - -static struct pci_ops ixp2000_pci_ops = { - .read = ixp2000_pci_read_config, - .write = ixp2000_pci_write_config -}; - -struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops, - sysdata, &sysdata->resources); -} - - -int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - - volatile u32 temp; - unsigned long flags; - - pci_master_aborts = 1; - - local_irq_save(flags); - temp = *(IXP2000_PCI_CONTROL); - if (temp & ((1 << 8) | (1 << 5))) { - ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp); - } - - temp = *(IXP2000_PCI_CMDSTAT); - if (temp & (1 << 29)) { - while (temp & (1 << 29)) { - ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp); - temp = *(IXP2000_PCI_CMDSTAT); - } - } - local_irq_restore(flags); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -int -clear_master_aborts(void) -{ - volatile u32 temp; - unsigned long flags; - - local_irq_save(flags); - temp = *(IXP2000_PCI_CONTROL); - if (temp & ((1 << 8) | (1 << 5))) { - ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp); - } - - temp = *(IXP2000_PCI_CMDSTAT); - if (temp & (1 << 29)) { - while (temp & (1 << 29)) { - ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp); - temp = *(IXP2000_PCI_CMDSTAT); - } - } - local_irq_restore(flags); - - return 0; -} - -void __init -ixp2000_pci_preinit(void) -{ - pci_set_flags(0); - - pcibios_min_io = 0; - pcibios_min_mem = 0; - -#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO - /* - * Configure the PCI unit to properly byteswap I/O transactions, - * and verify that it worked. - */ - ixp2000_reg_write(IXP2000_PCI_CONTROL, - (*IXP2000_PCI_CONTROL | PCI_CONTROL_IEE)); - - if ((*IXP2000_PCI_CONTROL & PCI_CONTROL_IEE) == 0) - panic("IXP2000: PCI I/O is broken on this ixp model, and " - "the needed workaround has not been configured in"); -#endif - - hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0, - "PCI config cycle to non-existent device"); -} - - -/* - * IXP2000 systems often have large resource requirements, so we just - * use our own resource space. - */ -static struct resource ixp2000_pci_mem_space = { - .start = 0xe0000000, - .end = 0xffffffff, - .flags = IORESOURCE_MEM, - .name = "PCI Mem Space" -}; - -static struct resource ixp2000_pci_io_space = { - .start = 0x00010000, - .end = 0x0001ffff, - .flags = IORESOURCE_IO, - .name = "PCI I/O Space" -}; - -int ixp2000_pci_setup(int nr, struct pci_sys_data *sys) -{ - if (nr >= 1) - return 0; - - pci_add_resource_offset(&sys->resources, - &ixp2000_pci_io_space, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &ixp2000_pci_mem_space, sys->mem_offset); - - return 1; -} - diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig deleted file mode 100644 index 982670ec3866..000000000000 --- a/arch/arm/mach-ixp23xx/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if ARCH_IXP23XX - -config ARCH_SUPPORTS_BIG_ENDIAN - bool - default y - -menu "Intel IXP23xx Implementation Options" - -comment "IXP23xx Platforms" - -config MACH_ESPRESSO - bool "Support IP Fabrics Double Espresso platform" - help - -config MACH_IXDP2351 - bool "Support Intel IXDP2351 platform" - help - -config MACH_ROADRUNNER - bool "Support ADI RoadRunner platform" - help - -endmenu - -endif diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile deleted file mode 100644 index 288b371b6d03..000000000000 --- a/arch/arm/mach-ixp23xx/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the linux kernel. -# -obj-y := core.o pci.o -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_MACH_ESPRESSO) += espresso.o -obj-$(CONFIG_MACH_IXDP2351) += ixdp2351.o -obj-$(CONFIG_MACH_ROADRUNNER) += roadrunner.o diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot deleted file mode 100644 index 44fb4a717c3f..000000000000 --- a/arch/arm/mach-ixp23xx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c deleted file mode 100644 index d34542425990..000000000000 --- a/arch/arm/mach-ixp23xx/core.c +++ /dev/null @@ -1,455 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/core.c - * - * Core routines for IXP23xx chips - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * Based on 2.4 code Copyright 2004 (c) Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/time.h> -#include <linux/timex.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> -#include <asm/system_misc.h> - -#include <asm/mach/map.h> -#include <asm/mach/time.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> - - -/************************************************************************* - * Chip specific mappings shared by all IXP23xx systems - *************************************************************************/ -static struct map_desc ixp23xx_io_desc[] __initdata = { - { /* XSI-CPP CSRs */ - .virtual = IXP23XX_XSI2CPP_CSR_VIRT, - .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS), - .length = IXP23XX_XSI2CPP_CSR_SIZE, - .type = MT_DEVICE, - }, { /* Expansion Bus Config */ - .virtual = IXP23XX_EXP_CFG_VIRT, - .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS), - .length = IXP23XX_EXP_CFG_SIZE, - .type = MT_DEVICE, - }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */ - .virtual = IXP23XX_PERIPHERAL_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS), - .length = IXP23XX_PERIPHERAL_SIZE, - .type = MT_DEVICE, - }, { /* CAP CSRs */ - .virtual = IXP23XX_CAP_CSR_VIRT, - .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS), - .length = IXP23XX_CAP_CSR_SIZE, - .type = MT_DEVICE, - }, { /* MSF CSRs */ - .virtual = IXP23XX_MSF_CSR_VIRT, - .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS), - .length = IXP23XX_MSF_CSR_SIZE, - .type = MT_DEVICE, - }, { /* PCI I/O Space */ - .virtual = IXP23XX_PCI_IO_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS), - .length = IXP23XX_PCI_IO_SIZE, - .type = MT_DEVICE, - }, { /* PCI Config Space */ - .virtual = IXP23XX_PCI_CFG_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS), - .length = IXP23XX_PCI_CFG_SIZE, - .type = MT_DEVICE, - }, { /* PCI local CFG CSRs */ - .virtual = IXP23XX_PCI_CREG_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS), - .length = IXP23XX_PCI_CREG_SIZE, - .type = MT_DEVICE, - }, { /* PCI MEM Space */ - .virtual = IXP23XX_PCI_MEM_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS), - .length = IXP23XX_PCI_MEM_SIZE, - .type = MT_DEVICE, - } -}; - -void __init ixp23xx_map_io(void) -{ - iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc)); -} - - -/*************************************************************************** - * IXP23xx Interrupt Handling - ***************************************************************************/ -enum ixp23xx_irq_type { - IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE -}; - -static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type); - -static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type) -{ - int line = d->irq - IRQ_IXP23XX_GPIO6 + 6; - u32 int_style; - enum ixp23xx_irq_type irq_type; - volatile u32 *int_reg; - - /* - * Only GPIOs 6-15 are wired to interrupts on IXP23xx - */ - if (line < 6 || line > 15) - return -EINVAL; - - switch (type) { - case IRQ_TYPE_EDGE_BOTH: - int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL; - irq_type = IXP23XX_IRQ_EDGE; - break; - case IRQ_TYPE_EDGE_RISING: - int_style = IXP23XX_GPIO_STYLE_RISING_EDGE; - irq_type = IXP23XX_IRQ_EDGE; - break; - case IRQ_TYPE_EDGE_FALLING: - int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE; - irq_type = IXP23XX_IRQ_EDGE; - break; - case IRQ_TYPE_LEVEL_HIGH: - int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH; - irq_type = IXP23XX_IRQ_LEVEL; - break; - case IRQ_TYPE_LEVEL_LOW: - int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW; - irq_type = IXP23XX_IRQ_LEVEL; - break; - default: - return -EINVAL; - } - - ixp23xx_config_irq(d->irq, irq_type); - - if (line >= 8) { /* pins 8-15 */ - line -= 8; - int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R; - } else { /* pins 0-7 */ - int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R; - } - - /* - * Clear pending interrupts - */ - *IXP23XX_GPIO_GPISR = (1 << line); - - /* Clear the style for the appropriate pin */ - *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK << - (line * IXP23XX_GPIO_STYLE_SIZE)); - - /* Set the new style */ - *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE)); - - return 0; -} - -static void ixp23xx_irq_mask(struct irq_data *d) -{ - volatile unsigned long *intr_reg; - unsigned int irq = d->irq; - - if (irq >= 56) - irq += 8; - - intr_reg = IXP23XX_INTR_EN1 + (irq / 32); - *intr_reg &= ~(1 << (irq % 32)); -} - -static void ixp23xx_irq_ack(struct irq_data *d) -{ - int line = d->irq - IRQ_IXP23XX_GPIO6 + 6; - - if ((line < 6) || (line > 15)) - return; - - *IXP23XX_GPIO_GPISR = (1 << line); -} - -/* - * Level triggered interrupts on GPIO lines can only be cleared when the - * interrupt condition disappears. - */ -static void ixp23xx_irq_level_unmask(struct irq_data *d) -{ - volatile unsigned long *intr_reg; - unsigned int irq = d->irq; - - ixp23xx_irq_ack(d); - - if (irq >= 56) - irq += 8; - - intr_reg = IXP23XX_INTR_EN1 + (irq / 32); - *intr_reg |= (1 << (irq % 32)); -} - -static void ixp23xx_irq_edge_unmask(struct irq_data *d) -{ - volatile unsigned long *intr_reg; - unsigned int irq = d->irq; - - if (irq >= 56) - irq += 8; - - intr_reg = IXP23XX_INTR_EN1 + (irq / 32); - *intr_reg |= (1 << (irq % 32)); -} - -static struct irq_chip ixp23xx_irq_level_chip = { - .irq_ack = ixp23xx_irq_mask, - .irq_mask = ixp23xx_irq_mask, - .irq_unmask = ixp23xx_irq_level_unmask, - .irq_set_type = ixp23xx_irq_set_type -}; - -static struct irq_chip ixp23xx_irq_edge_chip = { - .irq_ack = ixp23xx_irq_ack, - .irq_mask = ixp23xx_irq_mask, - .irq_unmask = ixp23xx_irq_edge_unmask, - .irq_set_type = ixp23xx_irq_set_type -}; - -static void ixp23xx_pci_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq)); -} - -static void ixp23xx_pci_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq)); -} - -/* - * TODO: Should this just be done at ASM level? - */ -static void pci_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 pci_interrupt; - unsigned int irqno; - - pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS; - - desc->irq_data.chip->irq_ack(&desc->irq_data); - - /* See which PCI_INTA, or PCI_INTB interrupted */ - if (pci_interrupt & (1 << 26)) { - irqno = IRQ_IXP23XX_INTB; - } else if (pci_interrupt & (1 << 27)) { - irqno = IRQ_IXP23XX_INTA; - } else { - BUG(); - } - - generic_handle_irq(irqno); - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixp23xx_pci_irq_chip = { - .irq_ack = ixp23xx_pci_irq_mask, - .irq_mask = ixp23xx_pci_irq_mask, - .irq_unmask = ixp23xx_pci_irq_unmask -}; - -static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) -{ - switch (type) { - case IXP23XX_IRQ_LEVEL: - irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip, - handle_level_irq); - break; - case IXP23XX_IRQ_EDGE: - irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip, - handle_edge_irq); - break; - } - set_irq_flags(irq, IRQF_VALID); -} - -void __init ixp23xx_init_irq(void) -{ - int irq; - - /* Route everything to IRQ */ - *IXP23XX_INTR_SEL1 = 0x0; - *IXP23XX_INTR_SEL2 = 0x0; - *IXP23XX_INTR_SEL3 = 0x0; - *IXP23XX_INTR_SEL4 = 0x0; - - /* Mask all sources */ - *IXP23XX_INTR_EN1 = 0x0; - *IXP23XX_INTR_EN2 = 0x0; - *IXP23XX_INTR_EN3 = 0x0; - *IXP23XX_INTR_EN4 = 0x0; - - /* - * Configure all IRQs for level-sensitive operation - */ - for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) { - ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL); - } - - for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { - irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); -} - - -/************************************************************************* - * Timer-tick functions for IXP23xx - *************************************************************************/ -#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC) - -static unsigned long next_jiffy_time; - -static unsigned long -ixp23xx_gettimeoffset(void) -{ - unsigned long elapsed; - - elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH); - - return elapsed / CLOCK_TICKS_PER_USEC; -} - -static irqreturn_t -ixp23xx_timer_interrupt(int irq, void *dev_id) -{ - /* Clear Pending Interrupt by writing '1' to it */ - *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND; - while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) { - timer_tick(); - next_jiffy_time += LATCH; - } - - return IRQ_HANDLED; -} - -static struct irqaction ixp23xx_timer_irq = { - .name = "IXP23xx Timer Tick", - .handler = ixp23xx_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, -}; - -void __init ixp23xx_init_timer(void) -{ - /* Clear Pending Interrupt by writing '1' to it */ - *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND; - - /* Setup the Timer counter value */ - *IXP23XX_TIMER1_RELOAD = - (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE; - - *IXP23XX_TIMER_CONT = 0; - next_jiffy_time = LATCH; - - /* Connect the interrupt handler and enable the interrupt */ - setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq); -} - -struct sys_timer ixp23xx_timer = { - .init = ixp23xx_init_timer, - .offset = ixp23xx_gettimeoffset, -}; - - -/************************************************************************* - * IXP23xx Platform Initialization - *************************************************************************/ -static struct resource ixp23xx_uart_resources[] = { - { - .start = IXP23XX_UART1_PHYS, - .end = IXP23XX_UART1_PHYS + 0x0fff, - .flags = IORESOURCE_MEM - }, { - .start = IXP23XX_UART2_PHYS, - .end = IXP23XX_UART2_PHYS + 0x0fff, - .flags = IORESOURCE_MEM - } -}; - -static struct plat_serial8250_port ixp23xx_uart_data[] = { - { - .mapbase = IXP23XX_UART1_PHYS, - .membase = (char *)(IXP23XX_UART1_VIRT + 3), - .irq = IRQ_IXP23XX_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP23XX_UART_XTAL, - }, { - .mapbase = IXP23XX_UART2_PHYS, - .membase = (char *)(IXP23XX_UART2_VIRT + 3), - .irq = IRQ_IXP23XX_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP23XX_UART_XTAL, - }, - { }, -}; - -static struct platform_device ixp23xx_uart = { - .name = "serial8250", - .id = 0, - .dev.platform_data = ixp23xx_uart_data, - .num_resources = 2, - .resource = ixp23xx_uart_resources, -}; - -static struct platform_device *ixp23xx_devices[] __initdata = { - &ixp23xx_uart, -}; - -void __init ixp23xx_sys_init(void) -{ - /* by default, the idle code is disabled */ - disable_hlt(); - - *IXP23XX_EXP_UNIT_FUSE |= 0xf; - platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices)); -} - -void ixp23xx_restart(char mode, const char *cmd) -{ - /* Use on-chip reset capability */ - *IXP23XX_RESET0 |= IXP23XX_RST_ALL; -} diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c deleted file mode 100644 index d142d45dea12..000000000000 --- a/arch/arm/mach-ixp23xx/espresso.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/espresso.c - * - * Double Espresso-specific routines - * - * Author: Lennert Buytenhek <buytenh@wantstofly.org> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/ioport.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/pci.h> -#include <linux/mtd/physmap.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> - -static int __init espresso_pci_init(void) -{ - if (machine_is_espresso()) - ixp23xx_pci_slave_init(); - - return 0; -}; -subsys_initcall(espresso_pci_init); - -static struct physmap_flash_data espresso_flash_data = { - .width = 2, -}; - -static struct resource espresso_flash_resource = { - .start = 0x90000000, - .end = 0x91ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device espresso_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &espresso_flash_data, - }, - .num_resources = 1, - .resource = &espresso_flash_resource, -}; - -static void __init espresso_init(void) -{ - platform_device_register(&espresso_flash); - - /* - * Mark flash as writeable. - */ - IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE; - - ixp23xx_sys_init(); -} - -MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso") - /* Maintainer: Lennert Buytenhek */ - .map_io = ixp23xx_map_io, - .init_irq = ixp23xx_init_irq, - .timer = &ixp23xx_timer, - .atag_offset = 0x100, - .init_machine = espresso_init, - .restart = ixp23xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S deleted file mode 100644 index 5ff524c13744..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <mach/ixp23xx.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =IXP23XX_PERIPHERAL_PHYS @ physical - ldr \rv, =IXP23XX_PERIPHERAL_VIRT @ virtual -#ifdef __ARMEB__ - orr \rp, \rp, #0x00000003 - orr \rv, \rv, #0x00000003 -#endif - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S deleted file mode 100644 index 3fd2cb984e42..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/entry-macro.S - */ - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET) - ldr \irqnr, [\irqnr] @ get interrupt number - cmp \irqnr, #0x0 @ spurious interrupt ? - movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits - subne \irqnr, \irqnr, #1 @ convert to 0 based - -#if 0 - cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH - bne 1001f - mov \irqnr, #IRQ_IXP23XX_INTA - - ldr \irqnr, =0xf5000030 - - mov \tmp, #(1<<26) - tst \irqnr, \tmp - movne \irqnr, #IRQ_IXP23XX_INTB - - mov \tmp, #(1<<27) - tst \irqnr, \tmp - movne \irqnr, #IRQ_IXP23XX_INTA -1001: -#endif - .endm diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h deleted file mode 100644 index 60e55fa10238..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/hardware.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/hardware.h - * - * Copyright (C) 2002-2004 Intel Corporation. - * Copyricht (C) 2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Hardware definitions for IXP23XX based systems - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* PCI IO info */ - -#include "ixp23xx.h" - -/* - * Platform helper functions - */ -#include "platform.h" - -/* - * Platform-specific headers - */ -#include "ixdp2351.h" - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h deleted file mode 100644 index a7aceb55c130..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/io.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/io.h - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2003-2005 Intel Corp. - * Copyright (C) 2005 MontaVista Software, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT)) - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/irqs.h b/arch/arm/mach-ixp23xx/include/mach/irqs.h deleted file mode 100644 index 3af33a04b8a2..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/irqs.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/irqs.h - * - * IRQ definitions for IXP23XX based systems - * - * Author: Naeem Afzal <naeem.m.afzal@intel.com> - * - * Copyright (C) 2003-2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1 -#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS - - -#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */ -#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */ -#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */ -#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */ -#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */ -#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */ -#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */ -#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */ -#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */ -#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */ -#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */ -#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */ -#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */ -#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */ -#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */ -#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */ -#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */ -#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */ -#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */ -#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */ -#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */ -#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */ -#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */ -#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */ -#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */ -#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */ -#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */ -#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */ -#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */ -#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */ -#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */ -#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */ -#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */ -#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */ -#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */ -#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */ -#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */ -#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */ -#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */ -#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */ -#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */ -#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */ -#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */ -#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */ -#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */ -#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */ -#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */ - -#define NUM_IXP23XX_RAW_IRQS 120 - -#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */ -#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */ - -#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1) - -/* - * We default to 32 per-board IRQs. Increase this number if you need - * more, but keep it realistic. - */ -#define NR_IXP23XX_MACH_IRQS 32 - -#define NR_IRQS (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS) - -#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq)) - - -/* - * IXDP2351-specific interrupts - */ - -/* - * External PCI interrupts signaled through INTB - * - */ -#define IXDP2351_INTB_IRQ_BASE 0 -#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0) -#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1) -#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2) -#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3) -#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4) -#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5) -#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6) -#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7) -#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8) - -#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0)) -#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq)) -#define IXDP2351_INTB_IRQ_VALID 0x01FF -#define IXDP2351_INTB_IRQ_NUM 16 - -/* - * Other external interrupts signaled through INTA - */ -#define IXDP2351_INTA_IRQ_BASE 16 -#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16) -#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17) -#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18) -#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19) -#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20) -#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21) -#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24) -#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25) -#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26) -#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27) -#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28) -#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29) -#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30) -#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31) - -#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16)) -#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq)) -#define IXDP2351_INTA_IRQ_VALID 0xFF3F -#define IXDP2351_INTA_IRQ_NUM 16 - - -/* - * ADI RoadRunner IRQs - */ -#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA -#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB -#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11 -#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12 - -/* - * Put new board definitions here - */ - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h deleted file mode 100644 index 663951027de5..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/ixdp2351.h - * - * Register and other defines for IXDP2351 - * - * Copyright (c) 2002-2004 Intel Corp. - * Copytight (c) 2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_IXDP2351_H -#define __ASM_ARCH_IXDP2351_H - -/* - * NP module memory map - */ -#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE) -#define IXDP2351_NP_PHYS_SIZE 0x00100000 -#define IXDP2351_NP_VIRT_BASE 0xeff00000 - -#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE) -#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16) - -#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000) - -#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg)) - -#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00) -#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02) -#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04) - -/* - * Base board module memory map - */ - -#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE) -#define IXDP2351_BB_SIZE 0x01000000 -#define IXDP2351_BB_BASE_VIRT (0xee000000) - -#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset) - -#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0) -#define IXDP2351_NVRAM_SIZE (0x20000) - -#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP2351_BB_AREA_BASE(0x00020000) -#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0) -#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000) -#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000) -#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000) -#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000) - -/* - * On board CPLD registers - */ -#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg)) - -#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00) -#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04) - -#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA -#define IXDP2351_CPLD_RESET1_ENABLE 0x8000 - -#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08) -#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10) -#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14) -#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18) -#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C) -#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */ -#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */ -#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */ -#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */ -#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28) -#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C) - /* Interrupt bits are defined in irqs.h */ -#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30) -#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34) - -/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */ -/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */ -/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */ -/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */ -/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */ - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h deleted file mode 100644 index 6d02481b1d6d..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/ixp23xx.h - * - * Register definitions for IXP23XX - * - * Copyright (C) 2003-2005 Intel Corporation. - * Copyright (C) 2005 MontaVista Software, Inc. - * - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_IXP23XX_H -#define __ASM_ARCH_IXP23XX_H - -/* - * IXP2300 linux memory map: - * - * virt phys size - * fffd0000 a0000000 64K XSI2CPP_CSR - * fffc0000 c4000000 4K EXP_CFG - * fff00000 c8000000 64K PERIPHERAL - * fe000000 1c0000000 16M CAP_CSR - * fd000000 1c8000000 16M MSF_CSR - * fb000000 16M --- - * fa000000 1d8000000 32M PCI_IO - * f8000000 1da000000 32M PCI_CFG - * f6000000 1de000000 32M PCI_CREG - * f4000000 32M --- - * f0000000 1e0000000 64M PCI_MEM - * e[c-f]000000 per-platform mappings - */ - - -/**************************************************************************** - * Static mappings. - ****************************************************************************/ -#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000 -#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000 -#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000 - -#define IXP23XX_EXP_CFG_PHYS 0xc4000000 -#define IXP23XX_EXP_CFG_VIRT 0xfffc0000 -#define IXP23XX_EXP_CFG_SIZE 0x00001000 - -#define IXP23XX_PERIPHERAL_PHYS 0xc8000000 -#define IXP23XX_PERIPHERAL_VIRT 0xfff00000 -#define IXP23XX_PERIPHERAL_SIZE 0x00010000 - -#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL -#define IXP23XX_CAP_CSR_VIRT 0xfe000000 -#define IXP23XX_CAP_CSR_SIZE 0x01000000 - -#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL -#define IXP23XX_MSF_CSR_VIRT 0xfd000000 -#define IXP23XX_MSF_CSR_SIZE 0x01000000 - -#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL -#define IXP23XX_PCI_IO_VIRT 0xfa000000 -#define IXP23XX_PCI_IO_SIZE 0x02000000 - -#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL -#define IXP23XX_PCI_CFG_VIRT 0xf8000000 -#define IXP23XX_PCI_CFG_SIZE 0x02000000 -#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT -#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000) - -#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL -#define IXP23XX_PCI_CREG_VIRT 0xf6000000 -#define IXP23XX_PCI_CREG_SIZE 0x02000000 -#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000) - -#define IXP23XX_PCI_MEM_START 0xe0000000 -#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL -#define IXP23XX_PCI_MEM_VIRT 0xf0000000 -#define IXP23XX_PCI_MEM_SIZE 0x04000000 - - -/**************************************************************************** - * XSI2CPP CSRs. - ****************************************************************************/ -#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x))) -#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8) -#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19) -#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20) -#define IXP23XX_CPP2XSI_COH_OFF (1 << 21) - - -/**************************************************************************** - * Expansion Bus Config. - ****************************************************************************/ -#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x))) -#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00) -#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04) -#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08) -#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c) -#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10) -#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14) -#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18) -#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c) -#define IXP23XX_FLASH_WRITABLE (0x2) -#define IXP23XX_FLASH_BUS8 (0x1) - -#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20) -#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24) -#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31) -#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22) -#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21) -#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19) -#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18) -#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16) -#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14) -#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13) -#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12) -#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5) -#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4) -#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3) -#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2) -#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1) -#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0) - -#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28) -#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30) -#define IXP23XX_EXP_CFG_FUSE IXP23XX_EXP_CFG_REG(0x34) - -#define IXP23XX_EXP_BUS_PHYS 0x90000000 -#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000 - -#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000) -#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000) -#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000) -#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000) -#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000) -#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000) -#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000) -#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000) - - -/**************************************************************************** - * Peripherals. - ****************************************************************************/ -#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000) -#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000) -#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000) -#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000) -#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000) -#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000) -#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000) -#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000) -#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000) -#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000) -#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000) -#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000) -#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000) -#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000) - -#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000) -#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000) -#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000) -#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000) -#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000) -#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000) -#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000) -#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000) -#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000) -#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000) -#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000) -#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000) -#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000) -#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000) - - -/**************************************************************************** - * Interrupt controller. - ****************************************************************************/ -#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x))) -#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00) -#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04) -#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08) -#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c) -#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10) -#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14) -#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18) -#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c) -#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20) -#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24) -#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28) -#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c) -#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30) -#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34) -#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38) -#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c) -#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54 - - -/**************************************************************************** - * GPIO. - ****************************************************************************/ -#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x))) -#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00) -#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04) -#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08) -#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c) -#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10) -#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14) -#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18) -#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c) - -#define IXP23XX_GPIO_STYLE_MASK 0x7 -#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0 -#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1 -#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2 -#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3 -#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4 - -#define IXP23XX_GPIO_STYLE_SIZE 3 - - -/**************************************************************************** - * Timer. - ****************************************************************************/ -#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x))) -#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00) -#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04) -#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08) -#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c) -#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10) -#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14) -#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18) -#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c) -#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e -#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20) -#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24) -#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28) - -#define IXP23XX_TIMER_ENABLE (1 << 0) -#define IXP23XX_TIMER_ONE_SHOT (1 << 1) -/* Low order bits of reload value ignored */ -#define IXP23XX_TIMER_RELOAD_MASK (0x3) -#define IXP23XX_TIMER_DISABLED (0x0) -#define IXP23XX_TIMER1_INT_PEND (1 << 0) -#define IXP23XX_TIMER2_INT_PEND (1 << 1) -#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2) -#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3) -#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4) - - -/**************************************************************************** - * CAP CSRs. - ****************************************************************************/ -#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x))) -#define IXP23XX_PRODUCT_ID IXP23XX_GLOBAL_REG(0x00) -#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04) -#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08) -#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c) -#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10) -#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18) - -#define IXP23XX_ENABLE_WATCHDOG (1 << 24) -#define IXP23XX_SHPC_INIT_COMP (1 << 21) -#define IXP23XX_RST_ALL (1 << 16) -#define IXP23XX_RESET_PCI (1 << 2) -#define IXP23XX_PCI_UNIT_RESET (1 << 1) -#define IXP23XX_XSCALE_RESET (1 << 0) - -#define IXP23XX_UENGINE_CSR_VIRT_BASE (IXP23XX_CAP_CSR_VIRT + 0x18000) - - -/**************************************************************************** - * PCI CSRs. - ****************************************************************************/ -#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x))) -#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04) -#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14) -#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18) - - -#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x))) -#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030) -#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034) -#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc) -#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100) -#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c) -#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140) -#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148) -#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c) -#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150) -#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150) -#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154) -#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158) -#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c) -#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160) - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h deleted file mode 100644 index 6cf0704e946a..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/memory.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/memory.h - * - * Copyright (c) 2003-2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <mach/hardware.h> - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET (0x00000000) - -#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0) - -#define __phys_to_bus(x) ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET)) -#define __bus_to_phys(x) ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET)) - -#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) -#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) -#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) -#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) - -#define arch_is_coherent() 1 - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h deleted file mode 100644 index 50de558e722e..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/platform.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/platform.h - * - * Various bits of code used by platform-level code. - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASSEMBLY__ - -static inline unsigned long ixp2000_reg_read(volatile void *reg) -{ - return *((volatile unsigned long *)reg); -} - -static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) -{ - *((volatile unsigned long *)reg) = val; -} - -static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) -{ - *((volatile unsigned long *)reg) = val; -} - -struct pci_sys_data; - -void ixp23xx_map_io(void); -void ixp23xx_init_irq(void); -void ixp23xx_sys_init(void); -void ixp23xx_restart(char, const char *); -int ixp23xx_pci_setup(int, struct pci_sys_data *); -void ixp23xx_pci_preinit(void); -struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); -void ixp23xx_pci_slave_init(void); - -extern struct sys_timer ixp23xx_timer; - -#define IXP23XX_UART_XTAL 14745600 - -#ifndef __ASSEMBLY__ -/* - * Is system memory on the XSI or CPP bus? - */ -static inline unsigned ixp23xx_cpp_boot(void) -{ - return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES); -} -#endif - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/time.h b/arch/arm/mach-ixp23xx/include/mach/time.h deleted file mode 100644 index b61dafc884ac..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/time.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/time.h - */ diff --git a/arch/arm/mach-ixp23xx/include/mach/timex.h b/arch/arm/mach-ixp23xx/include/mach/timex.h deleted file mode 100644 index e341e9cf9c37..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/timex.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/timex.h - * - * XScale architecture timex specifications - */ - -#define CLOCK_TICK_RATE 75000000 diff --git a/arch/arm/mach-ixp23xx/include/mach/uncompress.h b/arch/arm/mach-ixp23xx/include/mach/uncompress.h deleted file mode 100644 index 8b4c358d2c04..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/uncompress.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/uncompress.h - * - * Copyright (C) 2002-2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <mach/ixp23xx.h> -#include <linux/serial_reg.h> - -#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS) - -static inline void putc(char c) -{ - int j; - - for (j = 0; j < 0x1000; j++) { - if (UART_BASE[UART_LSR] & UART_LSR_THRE) - break; - barrier(); - } - - UART_BASE[UART_TX] = c; -} - -static inline void flush(void) -{ -} - -#define arch_decomp_setup() -#define arch_decomp_wdog() - - -#endif diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c deleted file mode 100644 index b0e07db5ceaf..000000000000 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/ixdp2351.c - * - * IXDP2351 board-specific routines - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * Based on 2.4 code Copyright 2004 (c) Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/ioport.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/pci.h> -#include <linux/mtd/physmap.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> - -/* - * IXDP2351 Interrupt Handling - */ -static void ixdp2351_inta_mask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq); -} - -static void ixdp2351_inta_unmask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq); -} - -static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc) -{ - u16 ex_interrupt = - *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID; - int i; - - desc->irq_data.chip->irq_mask(&desc->irq_data); - - for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) { - if (ex_interrupt & (1 << i)) { - int cpld_irq = - IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i); - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2351_inta_chip = { - .irq_ack = ixdp2351_inta_mask, - .irq_mask = ixdp2351_inta_mask, - .irq_unmask = ixdp2351_inta_unmask -}; - -static void ixdp2351_intb_mask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq); -} - -static void ixdp2351_intb_unmask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq); -} - -static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc) -{ - u16 ex_interrupt = - *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID; - int i; - - desc->irq_data.chip->irq_ack(&desc->irq_data); - - for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) { - if (ex_interrupt & (1 << i)) { - int cpld_irq = - IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i); - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2351_intb_chip = { - .irq_ack = ixdp2351_intb_mask, - .irq_mask = ixdp2351_intb_mask, - .irq_unmask = ixdp2351_intb_unmask -}; - -void __init ixdp2351_init_irq(void) -{ - int irq; - - /* Mask all interrupts from CPLD, disable simulation */ - *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1; - *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1; - *IXDP2351_CPLD_INTA_SIM_REG = 0; - *IXDP2351_CPLD_INTB_SIM_REG = 0; - - ixp23xx_init_irq(); - - for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE); - irq < - IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM); - irq++) { - if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { - set_irq_flags(irq, IRQF_VALID); - irq_set_chip_and_handler(irq, &ixdp2351_inta_chip, - handle_level_irq); - } - } - - for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE); - irq < - IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM); - irq++) { - if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { - set_irq_flags(irq, IRQF_VALID); - irq_set_chip_and_handler(irq, &ixdp2351_intb_chip, - handle_level_irq); - } - } - - irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); - irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); -} - -/* - * IXDP2351 PCI - */ - -/* - * This board does not do normal PCI IRQ routing, or any - * sort of swizzling, so we just need to check where on the - * bus the device is and figure out what CPLD pin it is - * being routed to. - */ -#define DEVPIN(dev, pin) ((pin) | ((dev) << 3)) - -static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - u8 bus = dev->bus->number; - u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin); - struct pci_bus *tmp_bus = dev->bus; - - /* Primary bus, no interrupts here */ - if (!bus) - return -1; - - /* Lookup first leaf in bus tree */ - while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) - tmp_bus = tmp_bus->parent; - - /* Select between known bridges */ - switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) { - /* Device is located after first bridge */ - case 0x0008: - if (tmp_bus == dev->bus) { - /* Device is located directy after first bridge */ - switch (devpin) { - /* Onboard 82546 */ - case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ - return IRQ_IXDP2351_INTA_82546; - case DEVPIN(1, 2): /* Onboard 82546 ch 1 */ - return IRQ_IXDP2351_INTB_82546; - /* PMC SLOT */ - case DEVPIN(0, 1): /* PMCP INTA# */ - case DEVPIN(2, 4): /* PMCS INTD# */ - return IRQ_IXDP2351_SPCI_PMC_INTA; - case DEVPIN(0, 2): /* PMCP INTB# */ - case DEVPIN(2, 1): /* PMCS INTA# */ - return IRQ_IXDP2351_SPCI_PMC_INTB; - case DEVPIN(0, 3): /* PMCP INTC# */ - case DEVPIN(2, 2): /* PMCS INTB# */ - return IRQ_IXDP2351_SPCI_PMC_INTC; - case DEVPIN(0, 4): /* PMCP INTD# */ - case DEVPIN(2, 3): /* PMCS INTC# */ - return IRQ_IXDP2351_SPCI_PMC_INTD; - } - } else { - /* Device is located indirectly after first bridge */ - /* Not supported now */ - return -1; - } - break; - case 0x0010: - if (tmp_bus == dev->bus) { - /* Device is located directy after second bridge */ - /* Secondary bus of second bridge */ - switch (devpin) { - case DEVPIN(0, 1): /* DB#0 */ - case DEVPIN(0, 2): - case DEVPIN(0, 3): - case DEVPIN(0, 4): - return IRQ_IXDP2351_SPCI_DB_0; - case DEVPIN(1, 1): /* DB#1 */ - case DEVPIN(1, 2): - case DEVPIN(1, 3): - case DEVPIN(1, 4): - return IRQ_IXDP2351_SPCI_DB_1; - case DEVPIN(2, 1): /* FIC1 */ - case DEVPIN(2, 2): - case DEVPIN(2, 3): - case DEVPIN(2, 4): - case DEVPIN(3, 1): /* FIC2 */ - case DEVPIN(3, 2): - case DEVPIN(3, 3): - case DEVPIN(3, 4): - return IRQ_IXDP2351_SPCI_FIC; - } - } else { - /* Device is located indirectly after second bridge */ - /* Not supported now */ - return -1; - } - break; - } - - return -1; -} - -struct hw_pci ixdp2351_pci __initdata = { - .nr_controllers = 1, - .preinit = ixp23xx_pci_preinit, - .setup = ixp23xx_pci_setup, - .scan = ixp23xx_pci_scan_bus, - .map_irq = ixdp2351_map_irq, -}; - -int __init ixdp2351_pci_init(void) -{ - if (machine_is_ixdp2351()) - pci_common_init(&ixdp2351_pci); - - return 0; -} - -subsys_initcall(ixdp2351_pci_init); - -/* - * IXDP2351 Static Mapped I/O - */ -static struct map_desc ixdp2351_io_desc[] __initdata = { - { - .virtual = IXDP2351_NP_VIRT_BASE, - .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE), - .length = IXDP2351_NP_PHYS_SIZE, - .type = MT_DEVICE - }, { - .virtual = IXDP2351_BB_BASE_VIRT, - .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS), - .length = IXDP2351_BB_SIZE, - .type = MT_DEVICE - } -}; - -static void __init ixdp2351_map_io(void) -{ - ixp23xx_map_io(); - iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc)); -} - -static struct physmap_flash_data ixdp2351_flash_data = { - .width = 1, -}; - -static struct resource ixdp2351_flash_resource = { - .start = 0x90000000, - .end = 0x93ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2351_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ixdp2351_flash_data, - }, - .num_resources = 1, - .resource = &ixdp2351_flash_resource, -}; - -static void __init ixdp2351_init(void) -{ - platform_device_register(&ixdp2351_flash); - - /* - * Mark flash as writeable - */ - IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE; - - ixp23xx_sys_init(); -} - -static void ixdp2351_restart(char mode, const char *cmd) -{ - /* First try machine specific support */ - - *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC; - (void) *IXDP2351_CPLD_RESET1_REG; - *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE; - - ixp23xx_restart(mode, cmd); -} - -MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .map_io = ixdp2351_map_io, - .init_irq = ixdp2351_init_irq, - .timer = &ixp23xx_timer, - .atag_offset = 0x100, - .init_machine = ixdp2351_init, - .restart = ixdp2351_restart, -MACHINE_END diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c deleted file mode 100644 index 911f5a58e006..000000000000 --- a/arch/arm/mach-ixp23xx/pci.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/pci.c - * - * PCI routines for IXP23XX based systems - * - * Copyright (c) 2005 MontaVista Software, Inc. - * - * based on original code: - * - * Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Copyright 2002-2005 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/sizes.h> -#include <asm/mach/pci.h> -#include <mach/hardware.h> - -extern int (*external_fault) (unsigned long, struct pt_regs *); - -static volatile int pci_master_aborts = 0; - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -int clear_master_aborts(void); - -static u32 -*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where) -{ - u32 *paddress; - - /* - * Must be dword aligned - */ - where &= ~3; - - /* - * For top bus, generate type 0, else type 1 - */ - if (!bus_nr) { - if (PCI_SLOT(devfn) >= 8) - return 0; - - paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT - | (1 << (PCI_SLOT(devfn) + 16)) - | (PCI_FUNC(devfn) << 8) | where); - } else { - paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT - | (bus_nr << 16) - | (PCI_SLOT(devfn) << 11) - | (PCI_FUNC(devfn) << 8) | where); - } - - return paddress; -} - -/* - * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. - * 0 and 3 are not valid indexes... - */ -static u32 bytemask[] = { - /*0*/ 0, - /*1*/ 0xff, - /*2*/ 0xffff, - /*3*/ 0, - /*4*/ 0xffffffff, -}; - -static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *value) -{ - u32 n; - u32 *addr; - - n = where % 4; - - DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where, - bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - addr = ixp23xx_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - - pci_master_aborts = 0; - *value = (*addr >> (8*n)) & bytemask[size]; - if (pci_master_aborts) { - pci_master_aborts = 0; - *value = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return PCIBIOS_SUCCESSFUL; -} - -/* - * We don't do error checking on the address for writes. - * It's assumed that the user checked for the device existing first - * by doing a read first. - */ -static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) -{ - u32 mask; - u32 *addr; - u32 temp; - - mask = ~(bytemask[size] << ((where % 0x4) * 8)); - addr = ixp23xx_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - temp = (u32) (value) << ((where % 0x4) * 8); - *addr = (*addr & mask) | temp; - - clear_master_aborts(); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops ixp23xx_pci_ops = { - .read = ixp23xx_pci_read_config, - .write = ixp23xx_pci_write_config, -}; - -struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops, - sysdata, &sysdata->resources); -} - -int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - volatile unsigned long temp; - unsigned long flags; - - pci_master_aborts = 1; - - local_irq_save(flags); - temp = *IXP23XX_PCI_CONTROL; - - /* - * master abort and cmd tgt err - */ - if (temp & ((1 << 8) | (1 << 5))) - *IXP23XX_PCI_CONTROL = temp; - - temp = *IXP23XX_PCI_CMDSTAT; - - if (temp & (1 << 29)) - *IXP23XX_PCI_CMDSTAT = temp; - local_irq_restore(flags); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -int clear_master_aborts(void) -{ - volatile u32 temp; - - temp = *IXP23XX_PCI_CONTROL; - - /* - * master abort and cmd tgt err - */ - if (temp & ((1 << 8) | (1 << 5))) - *IXP23XX_PCI_CONTROL = temp; - - temp = *IXP23XX_PCI_CMDSTAT; - - if (temp & (1 << 29)) - *IXP23XX_PCI_CMDSTAT = temp; - - return 0; -} - -static void __init ixp23xx_pci_common_init(void) -{ -#ifdef __ARMEB__ - *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */ -#endif - /* - * ADDR_31 needs to be clear for PCI memory access to CPP memory - */ - *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31; - *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF; - - /* - * Select correct memory for PCI inbound transactions - */ - if (ixp23xx_cpp_boot()) { - *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1); - } else { - *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1); - - /* - * Enable coherency on A2 silicon. - */ - if (arch_is_coherent()) - *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF; - } -} - -void __init ixp23xx_pci_preinit(void) -{ - pcibios_min_io = 0; - pcibios_min_mem = 0xe0000000; - - pci_set_flags(0); - - ixp23xx_pci_common_init(); - - hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0, - "PCI config cycle to non-existent device"); - - *IXP23XX_PCI_ADDR_EXT = 0x0000e000; -} - -/* - * Prevent PCI layer from seeing the inbound host-bridge resources - */ -static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev) -{ - int i; - - dev->class &= 0xff; - dev->class |= PCI_CLASS_BRIDGE_HOST << 8; - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx); - -/* - * IXP2300 systems often have large resource requirements, so we just - * use our own resource space. - */ -static struct resource ixp23xx_pci_mem_space = { - .start = IXP23XX_PCI_MEM_START, - .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, - .name = "PCI Mem Space" -}; - -static struct resource ixp23xx_pci_io_space = { - .start = 0x00000100, - .end = 0x01ffffff, - .flags = IORESOURCE_IO, - .name = "PCI I/O Space" -}; - -int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys) -{ - if (nr >= 1) - return 0; - - pci_add_resource_offset(&sys->resources, - &ixp23xx_pci_io_space, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &ixp23xx_pci_mem_space, sys->mem_offset); - - return 1; -} - -void __init ixp23xx_pci_slave_init(void) -{ - ixp23xx_pci_common_init(); -} diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c deleted file mode 100644 index eaaa3fa9fd05..000000000000 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/roadrunner.c - * - * RoadRunner board-specific routines - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/ioport.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/pci.h> -#include <linux/mtd/physmap.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> - -/* - * Interrupt mapping - */ -#define INTA IRQ_ROADRUNNER_PCI_INTA -#define INTB IRQ_ROADRUNNER_PCI_INTB -#define INTC IRQ_ROADRUNNER_PCI_INTC -#define INTD IRQ_ROADRUNNER_PCI_INTD - -#define INTC_PIN IXP23XX_GPIO_PIN_11 -#define INTD_PIN IXP23XX_GPIO_PIN_12 - -static int __init roadrunner_map_irq(const struct pci_dev *dev, u8 idsel, - u8 pin) -{ - static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA}; - static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD}; - static int usb_irq[] = {INTB, INTC, INTD, -1}; - static int mini_pci_1_irq[] = {INTB, INTC, -1, -1}; - static int mini_pci_2_irq[] = {INTC, INTD, -1, -1}; - - switch(dev->bus->number) { - case 0: - switch(dev->devfn) { - case 0x0: // PCI-PCI bridge - break; - case 0x8: // PCI Card Slot - return pci_card_slot_irq[pin - 1]; - case 0x10: // PMC Slot - return pmc_card_slot_irq[pin - 1]; - case 0x18: // PMC Slot Secondary Agent - break; - case 0x20: // IXP Processor - break; - default: - return NO_IRQ; - } - break; - - case 1: - switch(dev->devfn) { - case 0x0: // IDE Controller - return (pin == 1) ? INTC : -1; - case 0x8: // USB fun 0 - case 0x9: // USB fun 1 - case 0xa: // USB fun 2 - return usb_irq[pin - 1]; - case 0x10: // Mini PCI 1 - return mini_pci_1_irq[pin-1]; - case 0x18: // Mini PCI 2 - return mini_pci_2_irq[pin-1]; - case 0x20: // MEM slot - return (pin == 1) ? INTA : -1; - default: - return NO_IRQ; - } - break; - - default: - return NO_IRQ; - } - - return NO_IRQ; -} - -static void __init roadrunner_pci_preinit(void) -{ - irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); - - ixp23xx_pci_preinit(); -} - -static struct hw_pci roadrunner_pci __initdata = { - .nr_controllers = 1, - .preinit = roadrunner_pci_preinit, - .setup = ixp23xx_pci_setup, - .scan = ixp23xx_pci_scan_bus, - .map_irq = roadrunner_map_irq, -}; - -static int __init roadrunner_pci_init(void) -{ - if (machine_is_roadrunner()) - pci_common_init(&roadrunner_pci); - - return 0; -}; - -subsys_initcall(roadrunner_pci_init); - -static struct physmap_flash_data roadrunner_flash_data = { - .width = 2, -}; - -static struct resource roadrunner_flash_resource = { - .start = 0x90000000, - .end = 0x93ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device roadrunner_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &roadrunner_flash_data, - }, - .num_resources = 1, - .resource = &roadrunner_flash_resource, -}; - -static void __init roadrunner_init(void) -{ - platform_device_register(&roadrunner_flash); - - /* - * Mark flash as writeable - */ - IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE; - - ixp23xx_sys_init(); -} - -MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform") - /* Maintainer: Deepak Saxena */ - .map_io = ixp23xx_map_io, - .init_irq = ixp23xx_init_irq, - .timer = &ixp23xx_timer, - .atag_offset = 0x100, - .init_machine = roadrunner_init, - .restart = ixp23xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 8fea0a3c5246..548c7d43ade6 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -65,10 +65,9 @@ static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci avila_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = avila_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = avila_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index d5719eb42591..1694f01ce2b6 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -480,12 +480,6 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) return 1; } -struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys, - &sys->resources); -} - int dma_set_coherent_mask(struct device *dev, u64 mask) { if (mask >= SZ_64M - 1) diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index 71f5c9c60fc3..5d14ce2aee6d 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -48,10 +48,9 @@ static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci coyote_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = coyote_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = coyote_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index 0532510b5e8c..8dca76937723 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -62,10 +62,9 @@ static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata dsmg600_pci = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = dsmg600_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = dsmg600_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index d2ac803328f7..fd4a8625b4ae 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -59,10 +59,9 @@ static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci fsg_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = fsg_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = fsg_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 76581fb467c4..d9d6cc089707 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c @@ -47,10 +47,9 @@ static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot, struct hw_pci gateway7001_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = gateway7001_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = gateway7001_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index 46bb924962ee..b800a031207c 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -473,11 +473,10 @@ static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci gmlr_hw_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = gmlr_pci_preinit, .postinit = gmlr_pci_postinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = gmlr_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index d68fc068c38d..551d114c9e14 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -67,10 +67,9 @@ static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci gtwx5715_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = gtwx5715_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = gtwx5715_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h index 292d55ed2113..cf03614d250d 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h @@ -75,4 +75,7 @@ struct ixp46x_ts_regs { #define TX_SNAPSHOT_LOCKED (1<<0) #define RX_SNAPSHOT_LOCKED (1<<1) +/* The ptp_ixp46x module will set this variable */ +extern int ixp46x_phc_index; + #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h index b66bedc64de1..5bce94aacca9 100644 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h +++ b/arch/arm/mach-ixp4xx/include/mach/platform.h @@ -130,7 +130,7 @@ extern void ixp4xx_restart(char, const char *); extern void ixp4xx_pci_preinit(void); struct pci_sys_data; extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); -extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); +extern struct pci_ops ixp4xx_ops; /* * GPIO-functions diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index fffd8c5e40bf..318424dd3c50 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -60,10 +60,9 @@ static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci ixdp425_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = ixdp425_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = ixdp425_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 34efe75015ec..1f8717ba13dc 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -42,10 +42,9 @@ static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci ixdpg425_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = ixdpg425_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = ixdpg425_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c index ca0bae7fca90..d114ccd2017c 100644 --- a/arch/arm/mach-ixp4xx/miccpt-pci.c +++ b/arch/arm/mach-ixp4xx/miccpt-pci.c @@ -61,10 +61,9 @@ static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci miccpt_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = miccpt_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = miccpt_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index 5434ccf553eb..8f0eba0a6800 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -58,10 +58,9 @@ static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata nas100d_pci = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = nas100d_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = nas100d_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index b57160535e47..032defe111aa 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -54,10 +54,9 @@ static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci __initdata nslu2_pci = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = nslu2_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = nslu2_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index 0bc3f34c282f..a4220fa5e0c3 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -56,10 +56,9 @@ static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci vulcan_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = vulcan_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = vulcan_map_irq, }; diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index f27dfcfe811b..c92e5b82af36 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c @@ -46,10 +46,9 @@ static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) struct hw_pci wg302v2_pci __initdata = { .nr_controllers = 1, + .ops = &ixp4xx_ops, .preinit = wg302v2_pci_preinit, - .swizzle = pci_std_swizzle, .setup = ixp4xx_setup, - .scan = ixp4xx_scan_bus, .map_irq = wg302v2_map_irq, }; diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 1c672d9e6656..f7fe1b9f3170 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/kexec.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/bridge-regs.h> diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index f56a0118c1bb..de373176ee67 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -44,12 +44,6 @@ struct pcie_port { static int pcie_port_map[2]; static int num_pcie_ports; -static inline struct pcie_port *bus_to_port(struct pci_bus *bus) -{ - struct pci_sys_data *sys = bus->sysdata; - return sys->private_data; -} - static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) { /* @@ -79,7 +73,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -98,7 +93,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -248,13 +244,13 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus); + struct pci_sys_data *sys = dev->sysdata; + struct pcie_port *pp = sys->private_data; return pp->irq; } static struct hw_pci kirkwood_pci __initdata = { - .swizzle = pci_std_swizzle, .setup = kirkwood_pcie_setup, .scan = kirkwood_pcie_scan_bus, .map_irq = kirkwood_pcie_map_irq, diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c index acc701435817..bb18193b4bac 100644 --- a/arch/arm/mach-ks8695/pci.c +++ b/arch/arm/mach-ks8695/pci.c @@ -141,12 +141,6 @@ static struct pci_ops ks8695_pci_ops = { .write = ks8695_pci_writeconfig, }; -static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys, - &sys->resources); -} - static struct resource pci_mem = { .name = "PCI Memory space", .start = KS8695_PCIMEM_PA, @@ -302,11 +296,10 @@ static void ks8695_show_pciregs(void) static struct hw_pci ks8695_pci __initdata = { .nr_controllers = 1, + .ops = &ks8695_pci_ops, .preinit = ks8695_pci_preinit, .setup = ks8695_pci_setup, - .scan = ks8695_pci_scan_bus, .postinit = NULL, - .swizzle = pci_std_swizzle, .map_irq = NULL, }; diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index db81ed531031..75b3cfcada6d 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -17,7 +17,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/irq.h> -#include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/io.h> diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 7e8909c978c3..fbaa4ed95a3c 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -17,7 +17,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/irq.h> -#include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/usb/msm_hsusb.h> diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S index 3ffd8668c9a5..0e05f88abcd5 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/mach-msm/include/mach/debug-macro.S @@ -30,8 +30,7 @@ @ Write the 1 character to UARTDM_TF str \rd, [\rx, #0x70] #else - teq \rx, #0 - strne \rd, [\rx, #0x0C] + str \rd, [\rx, #0x0C] #endif .endm diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c index bafabb502580..c536fd6bf827 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-msm/scm.c @@ -282,6 +282,9 @@ u32 scm_get_version(void) __asmeq("%1", "r1") __asmeq("%2", "r0") __asmeq("%3", "r1") +#ifdef REQUIRES_SEC + ".arch_extension sec\n" +#endif "smc #0 @ switch to secure world\n" : "=r" (r0), "=r" (r1) : "r" (r0), "r" (r1) diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index df3e38055a24..2e56e86b6d68 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -147,6 +147,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) return 0; pp = &pcie_port[nr]; + sys->private_data = pp; pp->root_bus_nr = sys->busnr; /* @@ -161,19 +162,6 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static struct pcie_port *bus_to_port(int bus) -{ - int i; - - for (i = num_pcie_ports - 1; i >= 0; i--) { - int rbus = pcie_port[i].root_bus_nr; - if (rbus != -1 && rbus <= bus) - break; - } - - return i >= 0 ? pcie_port + i : NULL; -} - static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) { /* @@ -189,7 +177,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -208,7 +197,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus_to_port(bus->number); + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; unsigned long flags; int ret; @@ -263,7 +253,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - struct pcie_port *pp = bus_to_port(dev->bus->number); + struct pci_sys_data *sys = dev->bus->sysdata; + struct pcie_port *pp = sys->private_data; return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min; } @@ -271,7 +262,6 @@ static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci mv78xx0_pci __initdata = { .nr_controllers = 8, .preinit = mv78xx0_pcie_preinit, - .swizzle = pci_std_swizzle, .setup = mv78xx0_pcie_setup, .scan = mv78xx0_pcie_scan_bus, .map_irq = mv78xx0_pcie_map_irq, diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 4d1329d59287..9acdd6387047 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -11,10 +11,16 @@ #include <mach/mx23.h> #include <mach/devices-common.h> #include <mach/mxsfb.h> +#include <linux/amba/bus.h> -extern const struct amba_device mx23_duart_device __initconst; -#define mx23_add_duart() \ - mxs_add_duart(&mx23_duart_device) +static inline int mx23_add_duart(void) +{ + struct amba_device *d; + + d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K, + MX23_INT_DUART, 0, 0, 0); + return IS_ERR(d) ? PTR_ERR(d) : 0; +} extern const struct mxs_auart_data mx23_auart_data[] __initconst; #define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 9dbeae130842..84b2960df117 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -11,10 +11,16 @@ #include <mach/mx28.h> #include <mach/devices-common.h> #include <mach/mxsfb.h> +#include <linux/amba/bus.h> -extern const struct amba_device mx28_duart_device __initconst; -#define mx28_add_duart() \ - mxs_add_duart(&mx28_duart_device) +static inline int mx28_add_duart(void) +{ + struct amba_device *d; + + d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K, + MX28_INT_DUART, 0, 0, 0); + return IS_ERR(d) ? PTR_ERR(d) : 0; +} extern const struct mxs_auart_data mx28_auart_data[] __initconst; #define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id]) diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c index 01faffec3064..cf50b5a66dda 100644 --- a/arch/arm/mach-mxs/devices.c +++ b/arch/arm/mach-mxs/devices.c @@ -75,22 +75,6 @@ err: return pdev; } -int __init mxs_add_amba_device(const struct amba_device *dev) -{ - struct amba_device *adev = amba_device_alloc(dev->dev.init_name, - dev->res.start, resource_size(&dev->res)); - - if (!adev) { - pr_err("%s: failed to allocate memory", __func__); - return -ENOMEM; - } - - adev->irq[0] = dev->irq[0]; - adev->irq[1] = dev->irq[1]; - - return amba_device_add(adev, &iomem_resource); -} - struct device mxs_apbh_bus = { .init_name = "mxs_apbh", .parent = &platform_bus, diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index c8f5c9541a30..5f72d9787444 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -1,4 +1,3 @@ -obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o obj-y += platform-dma.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c deleted file mode 100644 index a5479f766046..000000000000 --- a/arch/arm/mach-mxs/devices/amba-duart.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/irq.h> -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define MXS_AMBA_DUART_DEVICE(name, soc) \ -const struct amba_device name##_device __initconst = { \ - .dev = { \ - .init_name = "duart", \ - }, \ - .res = { \ - .start = soc ## _DUART_BASE_ADDR, \ - .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \ - .flags = IORESOURCE_MEM, \ - }, \ - .irq = {soc ## _INT_DUART}, \ -} - -#ifdef CONFIG_SOC_IMX23 -MXS_AMBA_DUART_DEVICE(mx23_duart, MX23); -#endif - -#ifdef CONFIG_SOC_IMX28 -MXS_AMBA_DUART_DEVICE(mx28_duart, MX28); -#endif - -int __init mxs_add_duart(const struct amba_device *dev) -{ - return mxs_add_amba_device(dev); -} diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index f2e383955d88..21e45a70d344 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -27,11 +27,6 @@ static inline struct platform_device *mxs_add_platform_device( name, id, res, num_resources, data, size_data, 0); } -int __init mxs_add_amba_device(const struct amba_device *dev); - -/* duart */ -int __init mxs_add_duart(const struct amba_device *dev); - /* auart */ struct mxs_auart_data { int id; diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 9923f92b5450..398e9e53e189 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -12,6 +12,9 @@ endif obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o +# OCPI interconnect support for 1710, 1610 and 5912 +obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o + # Power Management obj-$(CONFIG_PM) += pm.o sleep.o @@ -28,13 +31,15 @@ usb-fs-$(CONFIG_USB) := usb.o obj-y += $(usb-fs-m) $(usb-fs-y) # Specific board support -obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o +obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o \ + board-nand.o obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o -obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o -obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o +obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o board-nand.o +obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o -obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o +obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \ + board-nand.o obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index fcce7ff37630..68e8e5654c0a 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -48,7 +48,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id) struct irq_chip *irq_chip = NULL; int gpio, irq_num, fiq_count; - irq_desc = irq_to_desc(IH_GPIO_BASE); + irq_desc = irq_to_desc(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK)); if (irq_desc) irq_chip = irq_desc->irq_data.chip; @@ -102,7 +102,7 @@ void __init ams_delta_init_fiq(void) } retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, - IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0); + IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL); if (retval < 0) { pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); release_fiq(&fh); diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 80bd43c7f4ec..4a4afb371022 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -185,20 +185,6 @@ static struct platform_device nor_device = { .resource = &nor_resource, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define FSAMPLE_NAND_RB_GPIO_PIN 62 static int nand_dev_ready(struct mtd_info *mtd) @@ -216,7 +202,7 @@ static struct platform_nand_data nand_data = { .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, }; diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 553a2e535764..057ec13f0649 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -179,20 +179,6 @@ static struct mtd_partition h2_nand_partitions[] = { }, }; -static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define H2_NAND_RB_GPIO_PIN 62 static int h2_nand_dev_ready(struct mtd_info *mtd) @@ -212,9 +198,8 @@ static struct platform_nand_data h2_nand_platdata = { .part_probe_types = h2_part_probes, }, .ctrl = { - .cmd_ctrl = h2_nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = h2_nand_dev_ready, - }, }; diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 4c19f4c06851..f6ddf8759657 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -181,20 +181,6 @@ static struct mtd_partition nand_partitions[] = { }, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define H3_NAND_RB_GPIO_PIN 10 static int nand_dev_ready(struct mtd_info *mtd) @@ -214,7 +200,7 @@ static struct platform_nand_data nand_platdata = { .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, diff --git a/arch/arm/mach-omap1/board-nand.c b/arch/arm/mach-omap1/board-nand.c new file mode 100644 index 000000000000..4d0835327d20 --- /dev/null +++ b/arch/arm/mach-omap1/board-nand.c @@ -0,0 +1,37 @@ +/* + * linux/arch/arm/mach-omap1/board-nand.c + * + * Common OMAP1 board NAND code + * + * Copyright (C) 2004, 2012 Texas Instruments, Inc. + * Copyright (C) 2002 MontaVista Software, Inc. + * Copyright (C) 2001 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> + +#include "common.h" + +void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long mask; + + if (cmd == NAND_CMD_NONE) + return; + + mask = (ctrl & NAND_CLE) ? 0x02 : 0; + if (ctrl & NAND_ALE) + mask |= 0x04; + + writeb(cmd, this->IO_ADDR_W + mask); +} + diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index a2c5abcd7c84..61ed4f0247ce 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -289,10 +289,10 @@ palmz71_gpio_setup(int early) gpio_direction_input(PALMZ71_USBDETECT_GPIO); if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO), palmz71_powercable, IRQF_SAMPLE_RANDOM, - "palmz71-cable", 0)) + "palmz71-cable", NULL)) printk(KERN_ERR "IRQ request for power cable failed!\n"); - palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), 0); + palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL); } } diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 76d4ee05a814..a2c88890e767 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -143,20 +143,6 @@ static struct platform_device nor_device = { .resource = &nor_resource, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define P2_NAND_RB_GPIO_PIN 62 static int nand_dev_ready(struct mtd_info *mtd) @@ -174,7 +160,7 @@ static struct platform_nand_data nand_data = { .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, }; diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 67382ddd8c83..a9ee06b6cb42 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -194,9 +194,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) { /* Find the highest supported frequency <= rate and switch to it */ struct mpu_rate * ptr; - unsigned long dpll1_rate, ref_rate; + unsigned long ref_rate; - dpll1_rate = ck_dpll1_p->rate; ref_rate = ck_ref_p->rate; for (ptr = omap1_rate_table; ptr->rate; ptr++) { diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index af658ad338ec..bb7779b57795 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -27,6 +27,7 @@ #define __ARCH_ARM_MACH_OMAP1_COMMON_H #include <plat/common.h> +#include <linux/mtd/mtd.h> #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) void omap7xx_map_io(void); @@ -56,8 +57,20 @@ void omap1_init_early(void); void omap1_init_irq(void); void omap1_restart(char, const char *); +extern void __init omap_check_revision(void); + +extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, + unsigned int ctrl); + extern struct sys_timer omap1_timer; extern bool omap_32k_timer_init(void); -extern void __init omap_init_consistent_dma_size(void); + +extern u32 omap_irq_flags; + +#ifdef CONFIG_ARCH_OMAP16XX +extern int ocpi_enable(void); +#else +static inline int ocpi_enable(void) { return 0; } +#endif #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */ diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 76c67b3f9f61..29ec50fc688d 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -87,7 +87,7 @@ static void fpga_mask_ack_irq(struct irq_data *d) fpga_ack_irq(d); } -void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) +static void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) { u32 stat; int fpga_irq; diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index 2b28e1da14b0..a1b846aacdaf 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -21,6 +21,8 @@ #include <mach/hardware.h> +#include "common.h" + #define OMAP_DIE_ID_0 0xfffe1800 #define OMAP_DIE_ID_1 0xfffe1804 #define OMAP_PRODUCTION_ID_0 0xfffe2000 diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index d969a7203d14..71ce017bf5d8 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -18,13 +18,12 @@ #include <plat/mux.h> #include <plat/tc.h> +#include <plat/dma.h> #include "iomap.h" #include "common.h" #include "clock.h" -extern void omap_check_revision(void); - /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 4448114fab72..6995fb6a3345 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -49,6 +49,8 @@ #include <mach/hardware.h> +#include "common.h" + #define IRQ_BANK(irq) ((irq) >> 5) #define IRQ_BIT(irq) ((irq) & 0x1f) diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c index 86ace9aaa663..5769c71815b2 100644 --- a/arch/arm/mach-omap1/lcd_dma.c +++ b/arch/arm/mach-omap1/lcd_dma.c @@ -57,7 +57,7 @@ static struct lcd_dma_info { void *cb_data; int active; - unsigned long addr, size; + unsigned long addr; int rotate, data_type, xres, yres; int vxres; int mirror; @@ -77,11 +77,6 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, } EXPORT_SYMBOL(omap_set_lcd_dma_b1); -void omap_set_lcd_dma_src_port(int port) -{ - lcd_dma.src_port = port; -} - void omap_set_lcd_dma_ext_controller(int external) { lcd_dma.ext_ctrl = external; diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/mach-omap1/ocpi.c index ebe0c73c8901..238170cab5b7 100644 --- a/arch/arm/plat-omap/ocpi.c +++ b/arch/arm/mach-omap1/ocpi.c @@ -4,6 +4,7 @@ * Minimal OCP bus support for omap16xx * * Copyright (C) 2003 - 2005 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Written by Tony Lindgren <tony@atomide.com> * * Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>. @@ -35,6 +36,8 @@ #include <mach/hardware.h> +#include "common.h" + #define OCPI_BASE 0xfffec320 #define OCPI_FAULT (OCPI_BASE + 0x00) #define OCPI_CMD_FAULT (OCPI_BASE + 0x04) @@ -64,7 +67,7 @@ int ocpi_enable(void) /* Enable access for OHCI in OCPI */ val = omap_readl(OCPI_PROT); val &= ~0xff; - //val &= (1 << 0); /* Allow access only to EMIFS */ + /* val &= (1 << 0); Allow access only to EMIFS */ omap_writel(val, OCPI_PROT); val = omap_readl(OCPI_SEC); @@ -86,7 +89,7 @@ static int __init omap_ocpi_init(void) clk_enable(ocpi_ck); ocpi_enable(); - printk("OMAP OCPI interconnect driver loaded\n"); + pr_info("OMAP OCPI interconnect driver loaded\n"); return 0; } diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index f66c32912b22..b2560d32b3a0 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -569,11 +569,10 @@ static int omap_pm_read_proc( static void omap_pm_init_proc(void) { - struct proc_dir_entry *entry; - - entry = create_proc_read_entry("driver/omap_pm", - S_IWUSR | S_IRUGO, NULL, - omap_pm_read_proc, NULL); + /* XXX Appears to leak memory */ + create_proc_read_entry("driver/omap_pm", + S_IWUSR | S_IRUGO, NULL, + omap_pm_read_proc, NULL); } #endif /* DEBUG && CONFIG_PROC_FS */ diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c index f255b153b863..b17709103866 100644 --- a/arch/arm/mach-omap1/reset.c +++ b/arch/arm/mach-omap1/reset.c @@ -8,6 +8,8 @@ #include <mach/hardware.h> +#include "common.h" + void omap1_restart(char mode, const char *cmd) { /* diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index fb202af01d0d..64c65bcb2d67 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -54,8 +54,7 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev, return 0; } - -int __init omap1_dm_timer_init(void) +static int __init omap1_dm_timer_init(void) { int i; int ret; diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index 19de03b074e3..e61afd922766 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -29,6 +29,8 @@ #include <plat/mux.h> #include <plat/usb.h> +#include "common.h" + /* These routines should handle the standard chip-specific modes * for usb0/1/2 ports, covering basic mux and transceiver setup. * @@ -138,6 +140,7 @@ static inline void ohci_device_init(struct omap_usb_config *pdata) if (cpu_is_omap7xx()) ohci_resources[1].start = INT_7XX_USB_HHC_1; pdata->ohci_device = &ohci_device; + pdata->ocpi_enable = &ocpi_enable; } #else diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index 1f97e7475206..447682c4e11c 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c @@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = { static void am35xx_enable_emac_int(void) { - u32 regval; - - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | - AM35XX_CPGMAC_C0_TX_PULSE_CLR | - AM35XX_CPGMAC_C0_MISC_PULSE_CLR | - AM35XX_CPGMAC_C0_RX_THRESH_CLR); - omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR | + AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ } static void am35xx_disable_emac_int(void) { - u32 regval; + u32 v; - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | - AM35XX_CPGMAC_C0_TX_PULSE_CLR); - omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ } static struct emac_platform_data am35xx_emac_pdata = { @@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = { void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) { - unsigned int regval; + u32 v; int err; am35xx_emac_pdata.rmii_en = rmii_en; @@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) return; } - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); - regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); - omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + v &= ~AM35XX_CPGMACSS_SW_RST; + omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); + omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ } diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index da75f239873e..37abb0d49b51 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -37,7 +37,7 @@ #include <plat/dma.h> #include <plat/gpmc.h> #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/gpmc-smc91x.h> @@ -113,9 +113,6 @@ static struct gpio sdp3430_dss_gpios[] __initdata = { {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"}, }; -static int lcd_enabled; -static int dvi_enabled; - static void __init sdp3430_display_init(void) { int r; @@ -129,44 +126,18 @@ static void __init sdp3430_display_init(void) static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) { - if (dvi_enabled) { - printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); - return -EINVAL; - } - gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1); gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1); - lcd_enabled = 1; - return 0; } static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) { - lcd_enabled = 0; - gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0); gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0); } -static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - - dvi_enabled = 1; - - return 0; -} - -static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - dvi_enabled = 0; -} - static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) { return 0; @@ -186,15 +157,14 @@ static struct omap_dss_device sdp3430_lcd_device = { .platform_disable = sdp3430_panel_disable_lcd, }; -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = sdp3430_panel_enable_dvi, - .platform_disable = sdp3430_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = -1, }; static struct omap_dss_device sdp3430_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 6dc184841892..4a9bc00a7d98 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -622,6 +622,10 @@ static struct nokia_dsi_panel_data dsi1_panel = { .use_ext_te = false, .ext_te_gpio = 101, .esd_interval = 0, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, + }, }; static struct omap_dss_device sdp4430_lcd_device = { @@ -630,13 +634,6 @@ static struct omap_dss_device sdp4430_lcd_device = { .type = OMAP_DISPLAY_TYPE_DSI, .data = &dsi1_panel, .phy.dsi = { - .clk_lane = 1, - .clk_pol = 0, - .data1_lane = 2, - .data1_pol = 0, - .data2_lane = 3, - .data2_pol = 0, - .module = 0, }, @@ -671,6 +668,10 @@ static struct nokia_dsi_panel_data dsi2_panel = { .use_ext_te = false, .ext_te_gpio = 103, .esd_interval = 0, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, + }, }; static struct omap_dss_device sdp4430_lcd2_device = { @@ -679,12 +680,6 @@ static struct omap_dss_device sdp4430_lcd2_device = { .type = OMAP_DISPLAY_TYPE_DSI, .data = &dsi2_panel, .phy.dsi = { - .clk_lane = 1, - .clk_pol = 0, - .data1_lane = 2, - .data1_pol = 0, - .data2_lane = 3, - .data2_pol = 0, .module = 1, }, @@ -714,21 +709,6 @@ static struct omap_dss_device sdp4430_lcd2_device = { .channel = OMAP_DSS_CHANNEL_LCD2, }; -static void sdp4430_lcd_init(void) -{ - int r; - - r = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT, - "lcd1_reset_gpio"); - if (r) - pr_err("%s: Could not get lcd1_reset_gpio\n", __func__); - - r = gpio_request_one(dsi2_panel.reset_gpio, GPIOF_DIR_OUT, - "lcd2_reset_gpio"); - if (r) - pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); -} - static struct omap_dss_hdmi_data sdp4430_hdmi_data = { .hpd_gpio = HDMI_GPIO_HPD, }; @@ -814,7 +794,6 @@ static void __init omap_4430sdp_display_init(void) if (r) pr_err("%s: Could not get display_sel GPIO\n", __func__); - sdp4430_lcd_init(); sdp4430_picodlp_init(); omap_display_init(&sdp4430_dss_data); /* diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 3645285a3e2b..99790eb646e8 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -37,7 +37,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include "am35xx-emac.h" #include "mux.h" @@ -207,31 +207,14 @@ static struct omap_dss_device am3517_evm_tv_device = { .platform_disable = am3517_evm_panel_disable_tv, }; -static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - dvi_enabled = 1; - - return 0; -} - -static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = am3517_evm_panel_enable_dvi, - .platform_disable = am3517_evm_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = -1, }; static struct omap_dss_device am3517_evm_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 909a8b91b564..45746cb56c68 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -44,7 +44,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/mcspi.h> #include <mach/hardware.h> @@ -218,25 +218,6 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) gpio_set_value(CM_T35_LCD_EN_GPIO, 0); } -static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - - gpio_set_value(CM_T35_DVI_EN_GPIO, 0); - dvi_enabled = 1; - - return 0; -} - -static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(CM_T35_DVI_EN_GPIO, 1); - dvi_enabled = 0; -} - static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) { return 0; @@ -260,15 +241,14 @@ static struct omap_dss_device cm_t35_lcd_device = { .phy.dpi.data_lines = 18, }; -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = cm_t35_panel_enable_dvi, - .platform_disable = cm_t35_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = CM_T35_DVI_EN_GPIO, }; static struct omap_dss_device cm_t35_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -316,7 +296,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { static struct gpio cm_t35_dss_gpios[] __initdata = { { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" }, { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" }, - { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable" }, }; static void __init cm_t35_init_display(void) @@ -335,7 +314,6 @@ static void __init cm_t35_init_display(void) gpio_export(CM_T35_LCD_EN_GPIO, 0); gpio_export(CM_T35_LCD_BL_GPIO, 0); - gpio_export(CM_T35_DVI_EN_GPIO, 0); msleep(50); gpio_set_value(CM_T35_LCD_EN_GPIO, 1); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index a2010f07de31..b063f0d2faa6 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -47,7 +47,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/mcspi.h> #include <linux/input/matrix_keypad.h> @@ -118,19 +118,6 @@ static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) gpio_set_value_cansleep(dssdev->reset_gpio, 0); } -static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value_cansleep(dssdev->reset_gpio, 1); - return 0; -} - -static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value_cansleep(dssdev->reset_gpio, 0); -} - static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = { REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), }; @@ -154,15 +141,14 @@ static struct omap_dss_device devkit8000_lcd_device = { .phy.dpi.data_lines = 24, }; -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = devkit8000_panel_enable_dvi, - .platform_disable = devkit8000_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = -1, }; static struct omap_dss_device devkit8000_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -244,13 +230,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev, } /* gpio + 7 is "DVI_PD" (out, active low) */ - devkit8000_dvi_device.reset_gpio = gpio + 7; - ret = gpio_request_one(devkit8000_dvi_device.reset_gpio, - GPIOF_OUT_INIT_LOW, "DVI PowerDown"); - if (ret < 0) { - devkit8000_dvi_device.reset_gpio = -EINVAL; - printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n"); - } + dvi_panel.power_down_gpio = gpio + 7; return 0; } diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 8f67861405bc..4c1acecce93f 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -32,7 +32,7 @@ #include <plat/gpmc.h> #include <plat/usb.h> #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/onenand.h> #include "mux.h" @@ -444,28 +444,15 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { .setup = igep_twl_gpio_setup, }; -static int igep2_enable_dvi(struct omap_dss_device *dssdev) -{ - gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1); - - return 0; -} - -static void igep2_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0); -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = igep2_enable_dvi, - .platform_disable = igep2_disable_dvi, - .i2c_bus_num = 3, +static struct tfp410_platform_data dvi_panel = { + .i2c_bus_num = 3, + .power_down_gpio = IGEP2_GPIO_DVI_PUP, }; static struct omap_dss_device igep2_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -480,14 +467,6 @@ static struct omap_dss_board_info igep2_dss_data = { .default_device = &igep2_dvi_device, }; -static void __init igep2_display_init(void) -{ - int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH, - "GPIO_DVI_PUP"); - if (err) - pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n"); -} - static struct platform_device *igep_devices[] __initdata = { &igep_vwlan_device, }; @@ -641,7 +620,7 @@ static struct regulator_consumer_supply dummy_supplies[] = { static void __init igep_init(void) { - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies)); omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); /* Get IGEP2 hardware revision */ @@ -668,7 +647,6 @@ static void __init igep_init(void) if (machine_is_igep0020()) { omap_display_init(&igep2_dss_data); - igep2_display_init(); igep2_init_smsc911x(); usbhs_init(&igep2_usbhs_bdata); } else { diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 7be8d659d91d..8ede8d20d7b2 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -42,7 +42,7 @@ #include <plat/board.h> #include "common.h" #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> @@ -189,33 +189,17 @@ static struct mtd_partition omap3beagle_nand_partitions[] = { /* DSS */ -static int beagle_enable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 1); - - return 0; -} - -static void beagle_disable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 0); -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = beagle_enable_dvi, - .platform_disable = beagle_disable_dvi, +static struct tfp410_platform_data dvi_panel = { .i2c_bus_num = 3, + .power_down_gpio = -1, }; static struct omap_dss_device beagle_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, - .reset_gpio = -EINVAL, }; static struct omap_dss_device beagle_tv_device = { @@ -236,16 +220,6 @@ static struct omap_dss_board_info beagle_dss_data = { .default_device = &beagle_dvi_device, }; -static void __init beagle_display_init(void) -{ - int r; - - r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW, - "DVI reset"); - if (r < 0) - printk(KERN_ERR "Unable to get DVI reset GPIO\n"); -} - #include "sdram-micron-mt46h32m32lf-6.h" static struct omap2_hsmmc_info mmc[] = { @@ -309,7 +283,7 @@ static int beagle_twl_gpio_setup(struct device *dev, if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC")) pr_err("%s: unable to configure EHCI_nOC\n", __func__); } - beagle_dvi_device.reset_gpio = beagle_config.reset_gpio; + dvi_panel.power_down_gpio = beagle_config.reset_gpio; gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level, "nEN_USB_PWR"); @@ -552,7 +526,6 @@ static void __init omap3_beagle_init(void) omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); - beagle_display_init(); beagle_opp_init(); } diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 49df12735b41..ace3c675e9c2 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -46,7 +46,7 @@ #include "common.h" #include <plat/mcspi.h> #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" @@ -219,35 +219,14 @@ static struct omap_dss_device omap3_evm_tv_device = { .platform_disable = omap3_evm_disable_tv, }; -static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - - gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); - - dvi_enabled = 1; - return 0; -} - -static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); - - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = omap3_evm_enable_dvi, - .platform_disable = omap3_evm_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, }; static struct omap_dss_device omap3_evm_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -630,13 +609,13 @@ static struct regulator_consumer_supply dummy_supplies[] = { static void __init omap3_evm_init(void) { + struct omap_board_mux *obm; + omap3_evm_get_revision(); regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - if (cpu_is_omap3630()) - omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB); - else - omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB); + obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux; + omap3_mux_init(obm, OMAP_PACKAGE_CBB); omap_board_config = omap3_evm_config; omap_board_config_size = ARRAY_SIZE(omap3_evm_config); diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 4dffc95bddd2..4396bae91677 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -42,7 +42,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/mcspi.h> #include <linux/input/matrix_keypad.h> @@ -92,9 +92,6 @@ static inline void __init omap3stalker_init_eth(void) #define LCD_PANEL_BKLIGHT_GPIO 210 #define ENABLE_VPLL2_DEV_GRP 0xE0 -static int lcd_enabled; -static int dvi_enabled; - static void __init omap3_stalker_display_init(void) { return; @@ -122,32 +119,14 @@ static struct omap_dss_device omap3_stalker_tv_device = { .platform_disable = omap3_stalker_disable_tv, }; -static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - gpio_set_value(DSS_ENABLE_GPIO, 1); - dvi_enabled = 1; - return 0; -} - -static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(DSS_ENABLE_GPIO, 0); - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = omap3_stalker_enable_dvi, - .platform_disable = omap3_stalker_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = DSS_ENABLE_GPIO, }; static struct omap_dss_device omap3_stalker_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index d53b07345f0b..bb75eb091a88 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -42,7 +42,7 @@ #include "common.h" #include <plat/usb.h> #include <plat/mmc.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include "hsmmc.h" #include "control.h" @@ -371,47 +371,22 @@ static struct omap_board_mux board_mux[] __initdata = { /* Display DVI */ #define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 -static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(dssdev->reset_gpio, 1); - return 0; -} - -static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(dssdev->reset_gpio, 0); -} - /* Using generic display panel */ -static struct panel_dvi_platform_data omap4_dvi_panel = { - .platform_enable = omap4_panda_enable_dvi, - .platform_disable = omap4_panda_disable_dvi, - .i2c_bus_num = 3, +static struct tfp410_platform_data omap4_dvi_panel = { + .i2c_bus_num = 3, + .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, }; static struct omap_dss_device omap4_panda_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &omap4_dvi_panel, .phy.dpi.data_lines = 24, .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, .channel = OMAP_DSS_CHANNEL_LCD2, }; -static int __init omap4_panda_dvi_init(void) -{ - int r; - - /* Requesting TFP410 DVI GPIO and disabling it, at bootup */ - r = gpio_request_one(omap4_panda_dvi_device.reset_gpio, - GPIOF_OUT_INIT_LOW, "DVI PD"); - if (r) - pr_err("Failed to get DVI powerdown GPIO\n"); - - return r; -} - static struct gpio panda_hdmi_gpios[] = { { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, @@ -462,11 +437,6 @@ static struct omap_dss_board_info omap4_panda_dss_data = { static void __init omap4_panda_display_init(void) { - int r; - - r = omap4_panda_dvi_init(); - if (r) - pr_err("error initializing panda DVI\n"); omap_display_init(&omap4_panda_dss_data); diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 33aa3910b09e..5527c1979a16 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -46,7 +46,7 @@ #include "common.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> #include <mach/hardware.h> #include <plat/nand.h> @@ -167,32 +167,15 @@ static void __init overo_display_init(void) gpio_export(OVERO_GPIO_LCD_BL, 0); } -static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - dvi_enabled = 1; - - return 0; -} - -static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = overo_panel_enable_dvi, - .platform_disable = overo_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { .i2c_bus_num = 3, + .power_down_gpio = -1, }; static struct omap_dss_device overo_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index d87ee0612098..ae957c92081b 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -872,11 +872,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = { .resource_config = twl4030_rconfig, }; -struct twl4030_vibra_data rx51_vibra_data __initdata = { +static struct twl4030_vibra_data rx51_vibra_data __initdata = { .coexist = 0, }; -struct twl4030_audio_data rx51_audio_data __initdata = { +static struct twl4030_audio_data rx51_audio_data __initdata = { .audio_mclk = 26000000, .vibra = &rx51_vibra_data, }; diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 27f01f051dff..2da92a6ba40a 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -59,25 +59,24 @@ static struct platform_device leds_gpio = { }; /* - * cpuidle C-states definition override from the default values. - * The 'exit_latency' field is the sum of sleep and wake-up latencies. - */ -static struct cpuidle_params rx51_cpuidle_params[] = { - /* C1 */ - {110 + 162, 5 , 1}, - /* C2 */ - {106 + 180, 309, 1}, - /* C3 */ - {107 + 410, 46057, 0}, - /* C4 */ - {121 + 3374, 46057, 0}, - /* C5 */ - {855 + 1146, 46057, 1}, - /* C6 */ - {7580 + 4134, 484329, 0}, - /* C7 */ - {7505 + 15274, 484329, 1}, -}; + * cpuidle C-states definition for rx51. + * + * The 'exit_latency' field is the sum of sleep + * and wake-up latencies. + + --------------------------------------------- + | state | exit_latency | target_residency | + --------------------------------------------- + | C1 | 110 + 162 | 5 | + | C2 | 106 + 180 | 309 | + | C3 | 107 + 410 | 46057 | + | C4 | 121 + 3374 | 46057 | + | C5 | 855 + 1146 | 46057 | + | C6 | 7580 + 4134 | 484329 | + | C7 | 7505 + 15274 | 484329 | + --------------------------------------------- + +*/ extern void __init rx51_peripherals_init(void); @@ -98,7 +97,6 @@ static void __init rx51_init(void) struct omap_sdrc_params *sdrc_params; omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3_pm_init_cpuidle(rx51_cpuidle_params); omap_serial_init(); sdrc_params = nokia_get_sdram_timings(); diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index a43a765dd092..28187f134fff 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -16,6 +16,7 @@ #include <linux/spi/spi.h> #include <plat/mcspi.h> #include <video/omapdss.h> +#include <mach/board-zoom.h> #define LCD_PANEL_RESET_GPIO_PROD 96 #define LCD_PANEL_RESET_GPIO_PILOT 55 diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index c09ca63b8ac8..f14b3aec58cc 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -135,8 +135,6 @@ void omap4_map_io(void); void ti81xx_map_io(void); void omap_barriers_init(void); -extern void __init omap_init_consistent_dma_size(void); - /** * omap_test_timeout - busy-loop, testing a condition * @cond: condition to test until it evaluates to true diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 535866489ce3..207bc1c7759f 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -38,40 +38,44 @@ #ifdef CONFIG_CPU_IDLE -/* - * The latencies/thresholds for various C states have - * to be configured from the respective board files. - * These are some default values (which might not provide - * the best power savings) used on boards which do not - * pass these details from the board file. - */ -static struct cpuidle_params cpuidle_params_table[] = { - /* C1 */ - {2 + 2, 5, 1}, - /* C2 */ - {10 + 10, 30, 1}, - /* C3 */ - {50 + 50, 300, 1}, - /* C4 */ - {1500 + 1800, 4000, 1}, - /* C5 */ - {2500 + 7500, 12000, 1}, - /* C6 */ - {3000 + 8500, 15000, 1}, - /* C7 */ - {10000 + 30000, 300000, 1}, -}; -#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table) - /* Mach specific information to be recorded in the C-state driver_data */ struct omap3_idle_statedata { u32 mpu_state; u32 core_state; - u8 valid; }; -struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES]; -struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; +static struct omap3_idle_statedata omap3_idle_data[] = { + { + .mpu_state = PWRDM_POWER_ON, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_ON, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_RET, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_OFF, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_RET, + .core_state = PWRDM_POWER_RET, + }, + { + .mpu_state = PWRDM_POWER_OFF, + .core_state = PWRDM_POWER_RET, + }, + { + .mpu_state = PWRDM_POWER_OFF, + .core_state = PWRDM_POWER_OFF, + }, +}; + +static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; static int _cpuidle_allow_idle(struct powerdomain *pwrdm, struct clockdomain *clkdm) @@ -91,8 +95,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct omap3_idle_statedata *cx = - cpuidle_get_statedata(&dev->states_usage[index]); + struct omap3_idle_statedata *cx = &omap3_idle_data[index]; u32 mpu_state = cx->mpu_state, core_state = cx->core_state; local_fiq_disable(); @@ -169,14 +172,12 @@ static inline int omap3_enter_idle(struct cpuidle_device *dev, * if it satisfies the enable_off_mode condition. */ static int next_valid_state(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) + struct cpuidle_driver *drv, int index) { - struct cpuidle_state_usage *curr_usage = &dev->states_usage[index]; - struct cpuidle_state *curr = &drv->states[index]; - struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage); + struct omap3_idle_statedata *cx = &omap3_idle_data[index]; u32 mpu_deepest_state = PWRDM_POWER_RET; u32 core_deepest_state = PWRDM_POWER_RET; + int idx; int next_index = -1; if (enable_off_mode) { @@ -191,45 +192,29 @@ static int next_valid_state(struct cpuidle_device *dev, } /* Check if current state is valid */ - if ((cx->valid) && - (cx->mpu_state >= mpu_deepest_state) && - (cx->core_state >= core_deepest_state)) { + if ((cx->mpu_state >= mpu_deepest_state) && + (cx->core_state >= core_deepest_state)) return index; - } else { - int idx = OMAP3_NUM_STATES - 1; - - /* Reach the current state starting at highest C-state */ - for (; idx >= 0; idx--) { - if (&drv->states[idx] == curr) { - next_index = idx; - break; - } - } - - /* Should never hit this condition */ - WARN_ON(next_index == -1); - /* - * Drop to next valid state. - * Start search from the next (lower) state. - */ - idx--; - for (; idx >= 0; idx--) { - cx = cpuidle_get_statedata(&dev->states_usage[idx]); - if ((cx->valid) && - (cx->mpu_state >= mpu_deepest_state) && - (cx->core_state >= core_deepest_state)) { - next_index = idx; - break; - } + /* + * Drop to next valid state. + * Start search from the next (lower) state. + */ + for (idx = index - 1; idx >= 0; idx--) { + cx = &omap3_idle_data[idx]; + if ((cx->mpu_state >= mpu_deepest_state) && + (cx->core_state >= core_deepest_state)) { + next_index = idx; + break; } - /* - * C1 is always valid. - * So, no need to check for 'next_index == -1' outside - * this loop. - */ } + /* + * C1 is always valid. + * So, no need to check for 'next_index == -1' outside + * this loop. + */ + return next_index; } @@ -273,7 +258,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, * Prevent PER off if CORE is not in retention or off as this * would disable PER wakeups completely. */ - cx = cpuidle_get_statedata(&dev->states_usage[index]); + cx = &omap3_idle_data[index]; core_next_state = cx->core_state; per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); if ((per_next_state == PWRDM_POWER_OFF) && @@ -298,57 +283,71 @@ select_state: DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); -void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) -{ - int i; - - if (!cpuidle_board_params) - return; - - for (i = 0; i < OMAP3_NUM_STATES; i++) { - cpuidle_params_table[i].valid = cpuidle_board_params[i].valid; - cpuidle_params_table[i].exit_latency = - cpuidle_board_params[i].exit_latency; - cpuidle_params_table[i].target_residency = - cpuidle_board_params[i].target_residency; - } - return; -} - struct cpuidle_driver omap3_idle_driver = { .name = "omap3_idle", .owner = THIS_MODULE, + .states = { + { + .enter = omap3_enter_idle, + .exit_latency = 2 + 2, + .target_residency = 5, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C1", + .desc = "MPU ON + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 10 + 10, + .target_residency = 30, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C2", + .desc = "MPU ON + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 50 + 50, + .target_residency = 300, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C3", + .desc = "MPU RET + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 1500 + 1800, + .target_residency = 4000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C4", + .desc = "MPU OFF + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 2500 + 7500, + .target_residency = 12000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C5", + .desc = "MPU RET + CORE RET", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 3000 + 8500, + .target_residency = 15000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C6", + .desc = "MPU OFF + CORE RET", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 10000 + 30000, + .target_residency = 30000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C7", + .desc = "MPU OFF + CORE OFF", + }, + }, + .state_count = ARRAY_SIZE(omap3_idle_data), + .safe_state_index = 0, }; -/* Helper to fill the C-state common data*/ -static inline void _fill_cstate(struct cpuidle_driver *drv, - int idx, const char *descr) -{ - struct cpuidle_state *state = &drv->states[idx]; - - state->exit_latency = cpuidle_params_table[idx].exit_latency; - state->target_residency = cpuidle_params_table[idx].target_residency; - state->flags = CPUIDLE_FLAG_TIME_VALID; - state->enter = omap3_enter_idle_bm; - sprintf(state->name, "C%d", idx + 1); - strncpy(state->desc, descr, CPUIDLE_DESC_LEN); - -} - -/* Helper to register the driver_data */ -static inline struct omap3_idle_statedata *_fill_cstate_usage( - struct cpuidle_device *dev, - int idx) -{ - struct omap3_idle_statedata *cx = &omap3_idle_data[idx]; - struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; - - cx->valid = cpuidle_params_table[idx].valid; - cpuidle_set_statedata(state_usage, cx); - - return cx; -} - /** * omap3_idle_init - Init routine for OMAP3 idle * @@ -358,77 +357,20 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage( int __init omap3_idle_init(void) { struct cpuidle_device *dev; - struct cpuidle_driver *drv = &omap3_idle_driver; - struct omap3_idle_statedata *cx; mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); per_pd = pwrdm_lookup("per_pwrdm"); cam_pd = pwrdm_lookup("cam_pwrdm"); + if (!mpu_pd || !core_pd || !per_pd || !cam_pd) + return -ENODEV; - drv->safe_state_index = -1; - dev = &per_cpu(omap3_idle_dev, smp_processor_id()); - - /* C1 . MPU WFI + Core active */ - _fill_cstate(drv, 0, "MPU ON + CORE ON"); - (&drv->states[0])->enter = omap3_enter_idle; - drv->safe_state_index = 0; - cx = _fill_cstate_usage(dev, 0); - cx->valid = 1; /* C1 is always valid */ - cx->mpu_state = PWRDM_POWER_ON; - cx->core_state = PWRDM_POWER_ON; - - /* C2 . MPU WFI + Core inactive */ - _fill_cstate(drv, 1, "MPU ON + CORE ON"); - cx = _fill_cstate_usage(dev, 1); - cx->mpu_state = PWRDM_POWER_ON; - cx->core_state = PWRDM_POWER_ON; - - /* C3 . MPU CSWR + Core inactive */ - _fill_cstate(drv, 2, "MPU RET + CORE ON"); - cx = _fill_cstate_usage(dev, 2); - cx->mpu_state = PWRDM_POWER_RET; - cx->core_state = PWRDM_POWER_ON; - - /* C4 . MPU OFF + Core inactive */ - _fill_cstate(drv, 3, "MPU OFF + CORE ON"); - cx = _fill_cstate_usage(dev, 3); - cx->mpu_state = PWRDM_POWER_OFF; - cx->core_state = PWRDM_POWER_ON; - - /* C5 . MPU RET + Core RET */ - _fill_cstate(drv, 4, "MPU RET + CORE RET"); - cx = _fill_cstate_usage(dev, 4); - cx->mpu_state = PWRDM_POWER_RET; - cx->core_state = PWRDM_POWER_RET; - - /* C6 . MPU OFF + Core RET */ - _fill_cstate(drv, 5, "MPU OFF + CORE RET"); - cx = _fill_cstate_usage(dev, 5); - cx->mpu_state = PWRDM_POWER_OFF; - cx->core_state = PWRDM_POWER_RET; - - /* C7 . MPU OFF + Core OFF */ - _fill_cstate(drv, 6, "MPU OFF + CORE OFF"); - cx = _fill_cstate_usage(dev, 6); - /* - * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot - * enable OFF mode in a stable form for previous revisions. - * We disable C7 state as a result. - */ - if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { - cx->valid = 0; - pr_warn("%s: core off state C7 disabled due to i583\n", - __func__); - } - cx->mpu_state = PWRDM_POWER_OFF; - cx->core_state = PWRDM_POWER_OFF; - - drv->state_count = OMAP3_NUM_STATES; cpuidle_register_driver(&omap3_idle_driver); - dev->state_count = OMAP3_NUM_STATES; + dev = &per_cpu(omap3_idle_dev, smp_processor_id()); + dev->cpu = 0; + if (cpuidle_register_device(dev)) { printk(KERN_ERR "%s: CPUidle register device failed\n", __func__); diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index f386cbe9c889..be1617ca84bd 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -24,26 +24,31 @@ #ifdef CONFIG_CPU_IDLE -/* Machine specific information to be recorded in the C-state driver_data */ +/* Machine specific information */ struct omap4_idle_statedata { u32 cpu_state; u32 mpu_logic_state; u32 mpu_state; - u8 valid; }; -static struct cpuidle_params cpuidle_params_table[] = { - /* C1 - CPU0 ON + CPU1 ON + MPU ON */ - {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1}, - /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */ - {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1}, - /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ - {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1}, +static struct omap4_idle_statedata omap4_idle_data[] = { + { + .cpu_state = PWRDM_POWER_ON, + .mpu_state = PWRDM_POWER_ON, + .mpu_logic_state = PWRDM_POWER_RET, + }, + { + .cpu_state = PWRDM_POWER_OFF, + .mpu_state = PWRDM_POWER_RET, + .mpu_logic_state = PWRDM_POWER_RET, + }, + { + .cpu_state = PWRDM_POWER_OFF, + .mpu_state = PWRDM_POWER_RET, + .mpu_logic_state = PWRDM_POWER_OFF, + }, }; -#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table) - -struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES]; static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; /** @@ -60,8 +65,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct omap4_idle_statedata *cx = - cpuidle_get_statedata(&dev->states_usage[index]); + struct omap4_idle_statedata *cx = &omap4_idle_data[index]; u32 cpu1_state; int cpu_id = smp_processor_id(); @@ -78,7 +82,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev, cpu1_state = pwrdm_read_pwrst(cpu1_pd); if (cpu1_state != PWRDM_POWER_OFF) { index = drv->safe_state_index; - cx = cpuidle_get_statedata(&dev->states_usage[index]); + cx = &omap4_idle_data[index]; } if (index > 0) @@ -133,36 +137,39 @@ struct cpuidle_driver omap4_idle_driver = { .name = "omap4_idle", .owner = THIS_MODULE, .en_core_tk_irqen = 1, + .states = { + { + /* C1 - CPU0 ON + CPU1 ON + MPU ON */ + .exit_latency = 2 + 2, + .target_residency = 5, + .flags = CPUIDLE_FLAG_TIME_VALID, + .enter = omap4_enter_idle, + .name = "C1", + .desc = "MPUSS ON" + }, + { + /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ + .exit_latency = 328 + 440, + .target_residency = 960, + .flags = CPUIDLE_FLAG_TIME_VALID, + .enter = omap4_enter_idle, + .name = "C2", + .desc = "MPUSS CSWR", + }, + { + /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ + .exit_latency = 460 + 518, + .target_residency = 1100, + .flags = CPUIDLE_FLAG_TIME_VALID, + .enter = omap4_enter_idle, + .name = "C3", + .desc = "MPUSS OSWR", + }, + }, + .state_count = ARRAY_SIZE(omap4_idle_data), + .safe_state_index = 0, }; -static inline void _fill_cstate(struct cpuidle_driver *drv, - int idx, const char *descr) -{ - struct cpuidle_state *state = &drv->states[idx]; - - state->exit_latency = cpuidle_params_table[idx].exit_latency; - state->target_residency = cpuidle_params_table[idx].target_residency; - state->flags = CPUIDLE_FLAG_TIME_VALID; - state->enter = omap4_enter_idle; - sprintf(state->name, "C%d", idx + 1); - strncpy(state->desc, descr, CPUIDLE_DESC_LEN); -} - -static inline struct omap4_idle_statedata *_fill_cstate_usage( - struct cpuidle_device *dev, - int idx) -{ - struct omap4_idle_statedata *cx = &omap4_idle_data[idx]; - struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; - - cx->valid = cpuidle_params_table[idx].valid; - cpuidle_set_statedata(state_usage, cx); - - return cx; -} - - - /** * omap4_idle_init - Init routine for OMAP4 idle * @@ -171,9 +178,7 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage( */ int __init omap4_idle_init(void) { - struct omap4_idle_statedata *cx; struct cpuidle_device *dev; - struct cpuidle_driver *drv = &omap4_idle_driver; unsigned int cpu_id = 0; mpu_pd = pwrdm_lookup("mpu_pwrdm"); @@ -182,42 +187,15 @@ int __init omap4_idle_init(void) if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) return -ENODEV; - - drv->safe_state_index = -1; dev = &per_cpu(omap4_idle_dev, cpu_id); dev->cpu = cpu_id; - /* C1 - CPU0 ON + CPU1 ON + MPU ON */ - _fill_cstate(drv, 0, "MPUSS ON"); - drv->safe_state_index = 0; - cx = _fill_cstate_usage(dev, 0); - cx->valid = 1; /* C1 is always valid */ - cx->cpu_state = PWRDM_POWER_ON; - cx->mpu_state = PWRDM_POWER_ON; - cx->mpu_logic_state = PWRDM_POWER_RET; - - /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ - _fill_cstate(drv, 1, "MPUSS CSWR"); - cx = _fill_cstate_usage(dev, 1); - cx->cpu_state = PWRDM_POWER_OFF; - cx->mpu_state = PWRDM_POWER_RET; - cx->mpu_logic_state = PWRDM_POWER_RET; - - /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ - _fill_cstate(drv, 2, "MPUSS OSWR"); - cx = _fill_cstate_usage(dev, 2); - cx->cpu_state = PWRDM_POWER_OFF; - cx->mpu_state = PWRDM_POWER_RET; - cx->mpu_logic_state = PWRDM_POWER_OFF; - - drv->state_count = OMAP4_NUM_STATES; cpuidle_register_driver(&omap4_idle_driver); - dev->state_count = OMAP4_NUM_STATES; if (cpuidle_register_device(dev)) { pr_err("%s: CPUidle register device failed\n", __func__); - return -EIO; - } + return -EIO; + } return 0; } diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index e4336035c0ea..f3953a499286 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -42,7 +42,6 @@ static int __init omap3_l3_init(void) { - int l; struct omap_hwmod *oh; struct platform_device *pdev; char oh_name[L3_MODULES_MAX_LEN]; @@ -54,7 +53,7 @@ static int __init omap3_l3_init(void) if (!(cpu_is_omap34xx())) return -ENODEV; - l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); + snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); oh = omap_hwmod_lookup(oh_name); @@ -72,7 +71,7 @@ postcore_initcall(omap3_l3_init); static int __init omap4_l3_init(void) { - int l, i; + int i; struct omap_hwmod *oh[3]; struct platform_device *pdev; char oh_name[L3_MODULES_MAX_LEN]; @@ -89,7 +88,7 @@ static int __init omap4_l3_init(void) return -ENODEV; for (i = 0; i < L3_MODULES; i++) { - l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); + snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); oh[i] = omap_hwmod_lookup(oh_name); if (!(oh[i])) diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 2f994e5194e8..064cab03d2bd 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -58,7 +58,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); - if (!pdata) { + if (!pdata->regs) { pr_err("gpio%d: Memory allocation failed\n", id); return -ENOMEM; } diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 385b3e02c4a6..a0fa9bb2bda5 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -176,7 +176,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, const int t_wpl = 40; const int t_wph = 30; int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; - int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; + int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; int err, ticks_cez; int cs = cfg->cs, freq = *freq_ptr; @@ -240,7 +240,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, break; } - tick_ns = gpmc_ticks_to_ns(1); div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); gpmc_clk_ns = gpmc_ticks_to_ns(div); if (gpmc_clk_ns < 15) /* >66Mhz */ diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 00d510858e28..580e684e8825 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -755,8 +755,7 @@ static int __init gpmc_init(void) irq++; } - ret = request_irq(gpmc_irq, - gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); + ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL); if (ret) pr_err("gpmc: irq-%d could not claim: err %d\n", gpmc_irq, ret); diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c index 454dfce125ca..8763c8520dc2 100644 --- a/arch/arm/mach-omap2/hwspinlock.c +++ b/arch/arm/mach-omap2/hwspinlock.c @@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = { .base_id = 0, }; -int __init hwspinlocks_init(void) +static int __init hwspinlocks_init(void) { int retval = 0; struct omap_hwmod *oh; diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h index 1e2d3322f33e..c88420de1151 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h @@ -941,10 +941,10 @@ #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) #define OMAP4_DSI1_LANEENABLE_SHIFT 24 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_DSI2_PIPD_SHIFT 19 -#define OMAP4_DSI2_PIPD_MASK (0x1f << 19) -#define OMAP4_DSI1_PIPD_SHIFT 14 -#define OMAP4_DSI1_PIPD_MASK (0x1f << 14) +#define OMAP4_DSI1_PIPD_SHIFT 19 +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) +#define OMAP4_DSI2_PIPD_SHIFT 14 +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) /* CONTROL_MCBSPLP */ #define OMAP4_ALBCTRLRX_FSX_SHIFT 31 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 065bd768987c..2d5a57669a79 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -31,6 +31,7 @@ #include <plat/omap-pm.h> #include <plat/omap_hwmod.h> #include <plat/multi.h> +#include <plat/dma.h> #include "iomap.h" #include "voltage.h" diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 7f47e3f65150..1ecf54565fe2 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -25,6 +25,7 @@ #include <mach/hardware.h> #include "iomap.h" +#include "common.h" /* selected INTC register offsets */ @@ -333,7 +334,7 @@ void omap_intc_restore_context(void) void omap3_intc_suspend(void) { /* A pending interrupt would prevent OMAP from entering suspend */ - omap_ack_irq(0); + omap_ack_irq(NULL); } void omap3_intc_prepare_idle(void) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 65c33911341f..3268ee24eada 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -247,7 +247,7 @@ int __init omap_mux_init_signal(const char *muxname, int val) int mux_mode; mux_mode = omap_mux_get_by_name(muxname, &partition, &mux); - if (mux_mode < 0) + if (mux_mode < 0 || !mux) return mux_mode; old_mode = omap_mux_read(partition, mux->reg_offset); diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index d8f8ef40290f..d9ae4a53d818 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -18,6 +18,7 @@ #include <asm/cacheflush.h> #include <asm/memblock.h> +#include <plat/omap-secure.h> #include <mach/omap-secure.h> static phys_addr_t omap_secure_memblock_base; diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 42cd7fb52414..d811c7790350 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -259,7 +259,7 @@ static void irq_save_context(void) /* * Clear WakeupGen SAR backup status. */ -void irq_sar_clear(void) +static void irq_sar_clear(void) { u32 val; val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 7144ae651d3d..bf86f7e8f91f 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2,7 +2,7 @@ * omap_hwmod implementation for OMAP2/3/4 * * Copyright (C) 2009-2011 Nokia Corporation - * Copyright (C) 2011 Texas Instruments, Inc. + * Copyright (C) 2011-2012 Texas Instruments, Inc. * * Paul Walmsley, BenoĂ®t Cousson, Kevin Hilman * @@ -137,6 +137,7 @@ #include <linux/mutex.h> #include <linux/spinlock.h> #include <linux/slab.h> +#include <linux/bootmem.h> #include "common.h" #include <plat/cpu.h> @@ -159,16 +160,58 @@ /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" +/* + * Number of struct omap_hwmod_link records per struct + * omap_hwmod_ocp_if record (master->slave and slave->master) + */ +#define LINKS_PER_OCP_IF 2 + /* omap_hwmod_list contains all registered struct omap_hwmods */ static LIST_HEAD(omap_hwmod_list); /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; +/* + * linkspace: ptr to a buffer that struct omap_hwmod_link records are + * allocated from - used to reduce the number of small memory + * allocations, which has a significant impact on performance + */ +static struct omap_hwmod_link *linkspace; + +/* + * free_ls, max_ls: array indexes into linkspace; representing the + * next free struct omap_hwmod_link index, and the maximum number of + * struct omap_hwmod_link records allocated (respectively) + */ +static unsigned short free_ls, max_ls, ls_supp; /* Private functions */ /** + * _fetch_next_ocp_if - return the next OCP interface in a list + * @p: ptr to a ptr to the list_head inside the ocp_if to return + * @i: pointer to the index of the element pointed to by @p in the list + * + * Return a pointer to the struct omap_hwmod_ocp_if record + * containing the struct list_head pointed to by @p, and increment + * @p such that a future call to this routine will return the next + * record. + */ +static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, + int *i) +{ + struct omap_hwmod_ocp_if *oi; + + oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; + *p = (*p)->next; + + *i = *i + 1; + + return oi; +} + +/** * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy * @oh: struct omap_hwmod * * @@ -582,16 +625,16 @@ static int _init_main_clk(struct omap_hwmod *oh) */ static int _init_interface_clks(struct omap_hwmod *oh) { + struct omap_hwmod_ocp_if *os; + struct list_head *p; struct clk *c; - int i; + int i = 0; int ret = 0; - if (oh->slaves_cnt == 0) - return 0; - - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; + p = oh->slave_ports.next; + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); if (!os->clk) continue; @@ -643,21 +686,22 @@ static int _init_opt_clks(struct omap_hwmod *oh) */ static int _enable_clocks(struct omap_hwmod *oh) { - int i; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i = 0; pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); if (oh->_clk) clk_enable(oh->_clk); - if (oh->slaves_cnt > 0) { - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; - struct clk *c = os->_clk; + p = oh->slave_ports.next; - if (c && (os->flags & OCPIF_SWSUP_IDLE)) - clk_enable(c); - } + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + + if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) + clk_enable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -673,21 +717,22 @@ static int _enable_clocks(struct omap_hwmod *oh) */ static int _disable_clocks(struct omap_hwmod *oh) { - int i; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i = 0; pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); if (oh->_clk) clk_disable(oh->_clk); - if (oh->slaves_cnt > 0) { - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; - struct clk *c = os->_clk; + p = oh->slave_ports.next; - if (c && (os->flags & OCPIF_SWSUP_IDLE)) - clk_disable(c); - } + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + + if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) + clk_disable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -781,39 +826,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) } /** - * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 - * @oh: struct omap_hwmod * - * - * Disable the PRCM module mode related to the hwmod @oh. - * Return EINVAL if the modulemode is not supported and 0 in case of success. - */ -static int _omap4_disable_module(struct omap_hwmod *oh) -{ - int v; - - /* The module mode does not exist prior OMAP4 */ - if (!cpu_is_omap44xx()) - return -EINVAL; - - if (!oh->clkdm || !oh->prcm.omap4.modulemode) - return -EINVAL; - - pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); - - omap4_cminst_module_disable(oh->clkdm->prcm_partition, - oh->clkdm->cm_inst, - oh->clkdm->clkdm_offs, - oh->prcm.omap4.clkctrl_offs); - - v = _omap4_wait_target_disable(oh); - if (v) - pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", - oh->name); - - return 0; -} - -/** * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh * @oh: struct omap_hwmod *oh * @@ -883,59 +895,220 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) } /** - * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use - * @oh: struct omap_hwmod * + * _get_mpu_irq_by_name - fetch MPU interrupt line number by name + * @oh: struct omap_hwmod * to operate on + * @name: pointer to the name of the MPU interrupt number to fetch (optional) + * @irq: pointer to an unsigned int to store the MPU IRQ number to * - * Returns the array index of the OCP slave port that the MPU - * addresses the device on, or -EINVAL upon error or not found. + * Retrieve a MPU hardware IRQ line number named by @name associated + * with the IP block pointed to by @oh. The IRQ number will be filled + * into the address pointed to by @dma. When @name is non-null, the + * IRQ line number associated with the named entry will be returned. + * If @name is null, the first matching entry will be returned. Data + * order is not meaningful in hwmod data, so callers are strongly + * encouraged to use a non-null @name whenever possible to avoid + * unpredictable effects if hwmod data is later added that causes data + * ordering to change. Returns 0 upon success or a negative error + * code upon error. */ -static int __init _find_mpu_port_index(struct omap_hwmod *oh) +static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, + unsigned int *irq) { int i; - int found = 0; + bool found = false; - if (!oh || oh->slaves_cnt == 0) - return -EINVAL; + if (!oh->mpu_irqs) + return -ENOENT; - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; + i = 0; + while (oh->mpu_irqs[i].irq != -1) { + if (name == oh->mpu_irqs[i].name || + !strcmp(name, oh->mpu_irqs[i].name)) { + found = true; + break; + } + i++; + } - if (os->user & OCP_USER_MPU) { - found = 1; + if (!found) + return -ENOENT; + + *irq = oh->mpu_irqs[i].irq; + + return 0; +} + +/** + * _get_sdma_req_by_name - fetch SDMA request line ID by name + * @oh: struct omap_hwmod * to operate on + * @name: pointer to the name of the SDMA request line to fetch (optional) + * @dma: pointer to an unsigned int to store the request line ID to + * + * Retrieve an SDMA request line ID named by @name on the IP block + * pointed to by @oh. The ID will be filled into the address pointed + * to by @dma. When @name is non-null, the request line ID associated + * with the named entry will be returned. If @name is null, the first + * matching entry will be returned. Data order is not meaningful in + * hwmod data, so callers are strongly encouraged to use a non-null + * @name whenever possible to avoid unpredictable effects if hwmod + * data is later added that causes data ordering to change. Returns 0 + * upon success or a negative error code upon error. + */ +static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, + unsigned int *dma) +{ + int i; + bool found = false; + + if (!oh->sdma_reqs) + return -ENOENT; + + i = 0; + while (oh->sdma_reqs[i].dma_req != -1) { + if (name == oh->sdma_reqs[i].name || + !strcmp(name, oh->sdma_reqs[i].name)) { + found = true; break; } + i++; } - if (found) - pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", - oh->name, i); - else - pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", - oh->name); + if (!found) + return -ENOENT; + + *dma = oh->sdma_reqs[i].dma_req; - return (found) ? i : -EINVAL; + return 0; } /** - * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU - * @oh: struct omap_hwmod * + * _get_addr_space_by_name - fetch address space start & end by name + * @oh: struct omap_hwmod * to operate on + * @name: pointer to the name of the address space to fetch (optional) + * @pa_start: pointer to a u32 to store the starting address to + * @pa_end: pointer to a u32 to store the ending address to * - * Return the virtual address of the base of the register target of - * device @oh, or NULL on error. + * Retrieve address space start and end addresses for the IP block + * pointed to by @oh. The data will be filled into the addresses + * pointed to by @pa_start and @pa_end. When @name is non-null, the + * address space data associated with the named entry will be + * returned. If @name is null, the first matching entry will be + * returned. Data order is not meaningful in hwmod data, so callers + * are strongly encouraged to use a non-null @name whenever possible + * to avoid unpredictable effects if hwmod data is later added that + * causes data ordering to change. Returns 0 upon success or a + * negative error code upon error. */ -static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) +static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, + u32 *pa_start, u32 *pa_end) { + int i, j; struct omap_hwmod_ocp_if *os; - struct omap_hwmod_addr_space *mem; - int i = 0, found = 0; - void __iomem *va_start; + struct list_head *p = NULL; + bool found = false; + + p = oh->slave_ports.next; + + i = 0; + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + + if (!os->addr) + return -ENOENT; + + j = 0; + while (os->addr[j].pa_start != os->addr[j].pa_end) { + if (name == os->addr[j].name || + !strcmp(name, os->addr[j].name)) { + found = true; + break; + } + j++; + } + + if (found) + break; + } + + if (!found) + return -ENOENT; + + *pa_start = os->addr[j].pa_start; + *pa_end = os->addr[j].pa_end; + + return 0; +} + +/** + * _save_mpu_port_index - find and save the index to @oh's MPU port + * @oh: struct omap_hwmod * + * + * Determines the array index of the OCP slave port that the MPU uses + * to address the device, and saves it into the struct omap_hwmod. + * Intended to be called during hwmod registration only. No return + * value. + */ +static void __init _save_mpu_port_index(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os = NULL; + struct list_head *p; + int i = 0; + + if (!oh) + return; - if (!oh || oh->slaves_cnt == 0) + oh->_int_flags |= _HWMOD_NO_MPU_PORT; + + p = oh->slave_ports.next; + + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + if (os->user & OCP_USER_MPU) { + oh->_mpu_port = os; + oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; + break; + } + } + + return; +} + +/** + * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU + * @oh: struct omap_hwmod * + * + * Given a pointer to a struct omap_hwmod record @oh, return a pointer + * to the struct omap_hwmod_ocp_if record that is used by the MPU to + * communicate with the IP block. This interface need not be directly + * connected to the MPU (and almost certainly is not), but is directly + * connected to the IP block represented by @oh. Returns a pointer + * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon + * error or if there does not appear to be a path from the MPU to this + * IP block. + */ +static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) +{ + if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) return NULL; - os = oh->slaves[index]; + return oh->_mpu_port; +}; + +/** + * _find_mpu_rt_addr_space - return MPU register target address space for @oh + * @oh: struct omap_hwmod * + * + * Returns a pointer to the struct omap_hwmod_addr_space record representing + * the register target MPU address space; or returns NULL upon error. + */ +static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + struct omap_hwmod_addr_space *mem; + int found = 0, i = 0; - if (!os->addr) + os = _find_mpu_rt_port(oh); + if (!os || !os->addr) return NULL; do { @@ -944,20 +1117,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) found = 1; } while (!found && mem->pa_start != mem->pa_end); - if (found) { - va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); - if (!va_start) { - pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); - return NULL; - } - pr_debug("omap_hwmod: %s: MPU register target at va %p\n", - oh->name, va_start); - } else { - pr_debug("omap_hwmod: %s: no MPU register target found\n", - oh->name); - } - - return (found) ? va_start : NULL; + return (found) ? mem : NULL; } /** @@ -1205,12 +1365,11 @@ static int _wait_target_ready(struct omap_hwmod *oh) if (!oh) return -EINVAL; - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + if (oh->flags & HWMOD_NO_IDLEST) return 0; - os = oh->slaves[oh->_mpu_port_index]; - - if (oh->flags & HWMOD_NO_IDLEST) + os = _find_mpu_rt_port(oh); + if (!os) return 0; /* XXX check module SIDLEMODE */ @@ -1378,13 +1537,73 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) } /** + * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset + * @oh: struct omap_hwmod * + * + * If any hardreset line associated with @oh is asserted, then return true. + * Otherwise, if @oh has no hardreset lines associated with it, or if + * no hardreset lines associated with @oh are asserted, then return false. + * This function is used to avoid executing some parts of the IP block + * enable/disable sequence if a hardreset line is set. + */ +static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) +{ + int i; + + if (oh->rst_lines_cnt == 0) + return false; + + for (i = 0; i < oh->rst_lines_cnt; i++) + if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) + return true; + + return false; +} + +/** + * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 + * @oh: struct omap_hwmod * + * + * Disable the PRCM module mode related to the hwmod @oh. + * Return EINVAL if the modulemode is not supported and 0 in case of success. + */ +static int _omap4_disable_module(struct omap_hwmod *oh) +{ + int v; + + /* The module mode does not exist prior OMAP4 */ + if (!cpu_is_omap44xx()) + return -EINVAL; + + if (!oh->clkdm || !oh->prcm.omap4.modulemode) + return -EINVAL; + + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); + + omap4_cminst_module_disable(oh->clkdm->prcm_partition, + oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); + + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + + v = _omap4_wait_target_disable(oh); + if (v) + pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", + oh->name); + + return 0; +} + +/** * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be - * enabled for this to work. Returns -EINVAL if the hwmod cannot be - * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if - * the module did not reset in time, or 0 upon success. + * enabled for this to work. Returns -ENOENT if the hwmod cannot be + * reset this way, -EINVAL if the hwmod is in the wrong state, + * -ETIMEDOUT if the module did not reset in time, or 0 upon success. * * In OMAP3 a specific SYSSTATUS register is used to get the reset status. * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead @@ -1401,7 +1620,7 @@ static int _ocp_softreset(struct omap_hwmod *oh) if (!oh->class->sysc || !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) - return -EINVAL; + return -ENOENT; /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { @@ -1462,32 +1681,60 @@ dis_opt_clks: * _reset - reset an omap_hwmod * @oh: struct omap_hwmod * * - * Resets an omap_hwmod @oh. The default software reset mechanism for - * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET - * bit. However, some hwmods cannot be reset via this method: some - * are not targets and therefore have no OCP header registers to - * access; others (like the IVA) have idiosyncratic reset sequences. - * So for these relatively rare cases, custom reset code can be - * supplied in the struct omap_hwmod_class .reset function pointer. - * Passes along the return value from either _reset() or the custom - * reset function - these must return -EINVAL if the hwmod cannot be - * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if - * the module did not reset in time, or 0 upon success. + * Resets an omap_hwmod @oh. If the module has a custom reset + * function pointer defined, then call it to reset the IP block, and + * pass along its return value to the caller. Otherwise, if the IP + * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield + * associated with it, call a function to reset the IP block via that + * method, and pass along the return value to the caller. Finally, if + * the IP block has some hardreset lines associated with it, assert + * all of those, but do _not_ deassert them. (This is because driver + * authors have expressed an apparent requirement to control the + * deassertion of the hardreset lines themselves.) + * + * The default software reset mechanism for most OMAP IP blocks is + * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some + * hwmods cannot be reset via this method. Some are not targets and + * therefore have no OCP header registers to access. Others (like the + * IVA) have idiosyncratic reset sequences. So for these relatively + * rare cases, custom reset code can be supplied in the struct + * omap_hwmod_class .reset function pointer. Passes along the return + * value from either _ocp_softreset() or the custom reset function - + * these must return -EINVAL if the hwmod cannot be reset this way or + * if the hwmod is in the wrong state, -ETIMEDOUT if the module did + * not reset in time, or 0 upon success. */ static int _reset(struct omap_hwmod *oh) { - int ret; + int i, r; pr_debug("omap_hwmod: %s: resetting\n", oh->name); - ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); + if (oh->class->reset) { + r = oh->class->reset(oh); + } else { + if (oh->rst_lines_cnt > 0) { + for (i = 0; i < oh->rst_lines_cnt; i++) + _assert_hardreset(oh, oh->rst_lines[i].name); + return 0; + } else { + r = _ocp_softreset(oh); + if (r == -ENOENT) + r = 0; + } + } + /* + * OCP_SYSCONFIG bits need to be reprogrammed after a + * softreset. The _enable() function should be split to avoid + * the rewrite of the OCP_SYSCONFIG register. + */ if (oh->class->sysc) { _update_sysc_cache(oh); _enable_sysc(oh); } - return ret; + return r; } /** @@ -1506,10 +1753,9 @@ static int _enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); /* - * hwmods with HWMOD_INIT_NO_IDLE flag set are left - * in enabled state at init. - * Now that someone is really trying to enable them, - * just ensure that the hwmod mux is set. + * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled + * state at init. Now that someone is really trying to enable + * them, just ensure that the hwmod mux is set. */ if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { /* @@ -1532,15 +1778,17 @@ static int _enable(struct omap_hwmod *oh) return -EINVAL; } - /* - * If an IP contains only one HW reset line, then de-assert it in order - * to allow the module state transition. Otherwise the PRCM will return - * Intransition status, and the init will failed. + * If an IP block contains HW reset lines and any of them are + * asserted, we let integration code associated with that + * block handle the enable. We've received very little + * information on what those driver authors need, and until + * detailed information is provided and the driver code is + * posted to the public lists, this is probably the best we + * can do. */ - if ((oh->_state == _HWMOD_STATE_INITIALIZED || - oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) - _deassert_hardreset(oh, oh->rst_lines[0].name); + if (_are_any_hardreset_lines_asserted(oh)) + return 0; /* Mux pins for device runtime if populated */ if (oh->mux && (!oh->mux->enabled || @@ -1615,6 +1863,9 @@ static int _idle(struct omap_hwmod *oh) return -EINVAL; } + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); @@ -1687,7 +1938,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) */ static int _shutdown(struct omap_hwmod *oh) { - int ret; + int ret, i; u8 prev_state; if (oh->_state != _HWMOD_STATE_IDLE && @@ -1697,6 +1948,9 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->pre_shutdown) { @@ -1728,12 +1982,8 @@ static int _shutdown(struct omap_hwmod *oh) } /* XXX Should this code also force-disable the optional clocks? */ - /* - * If an IP contains only one HW reset line, then assert it - * after disabling the clocks and before shutting down the IP. - */ - if (oh->rst_lines_cnt == 1) - _assert_hardreset(oh, oh->rst_lines[0].name); + for (i = 0; i < oh->rst_lines_cnt; i++) + _assert_hardreset(oh, oh->rst_lines[i].name); /* Mux pins to safe mode or use populated off mode values */ if (oh->mux) @@ -1745,59 +1995,186 @@ static int _shutdown(struct omap_hwmod *oh) } /** - * _setup - do initial configuration of omap_hwmod - * @oh: struct omap_hwmod * + * _init_mpu_rt_base - populate the virtual address for a hwmod + * @oh: struct omap_hwmod * to locate the virtual address * - * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. Returns 0. + * Cache the virtual address used by the MPU to access this IP block's + * registers. This address is needed early so the OCP registers that + * are part of the device's address space can be ioremapped properly. + * No return value. */ -static int _setup(struct omap_hwmod *oh, void *data) +static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) { - int i, r; - u8 postsetup_state; + struct omap_hwmod_addr_space *mem; + void __iomem *va_start; + + if (!oh) + return; + + _save_mpu_port_index(oh); - if (oh->_state != _HWMOD_STATE_CLKS_INITED) + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return; + + mem = _find_mpu_rt_addr_space(oh); + if (!mem) { + pr_debug("omap_hwmod: %s: no MPU register target found\n", + oh->name); + return; + } + + va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); + if (!va_start) { + pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); + return; + } + + pr_debug("omap_hwmod: %s: MPU register target at va %p\n", + oh->name, va_start); + + oh->_mpu_rt_va = va_start; +} + +/** + * _init - initialize internal data for the hwmod @oh + * @oh: struct omap_hwmod * + * @n: (unused) + * + * Look up the clocks and the address space used by the MPU to access + * registers belonging to the hwmod @oh. @oh must already be + * registered at this point. This is the first of two phases for + * hwmod initialization. Code called here does not touch any hardware + * registers, it simply prepares internal data structures. Returns 0 + * upon success or if the hwmod isn't registered, or -EINVAL upon + * failure. + */ +static int __init _init(struct omap_hwmod *oh, void *data) +{ + int r; + + if (oh->_state != _HWMOD_STATE_REGISTERED) return 0; - /* Set iclk autoidle mode */ - if (oh->slaves_cnt > 0) { - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; - struct clk *c = os->_clk; + _init_mpu_rt_base(oh, NULL); - if (!c) - continue; + r = _init_clocks(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); + return -EINVAL; + } - if (os->flags & OCPIF_SWSUP_IDLE) { - /* XXX omap_iclk_deny_idle(c); */ - } else { - /* XXX omap_iclk_allow_idle(c); */ - clk_enable(c); - } + oh->_state = _HWMOD_STATE_INITIALIZED; + + return 0; +} + +/** + * _setup_iclk_autoidle - configure an IP block's interface clocks + * @oh: struct omap_hwmod * + * + * Set up the module's interface clocks. XXX This function is still mostly + * a stub; implementing this properly requires iclk autoidle usecounting in + * the clock code. No return value. + */ +static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i = 0; + if (oh->_state != _HWMOD_STATE_INITIALIZED) + return; + + p = oh->slave_ports.next; + + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + if (!os->_clk) + continue; + + if (os->flags & OCPIF_SWSUP_IDLE) { + /* XXX omap_iclk_deny_idle(c); */ + } else { + /* XXX omap_iclk_allow_idle(c); */ + clk_enable(os->_clk); } } - oh->_state = _HWMOD_STATE_INITIALIZED; + return; +} - /* - * In the case of hwmod with hardreset that should not be - * de-assert at boot time, we have to keep the module - * initialized, because we cannot enable it properly with the - * reset asserted. Exit without warning because that behavior is - * expected. - */ - if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) - return 0; +/** + * _setup_reset - reset an IP block during the setup process + * @oh: struct omap_hwmod * + * + * Reset the IP block corresponding to the hwmod @oh during the setup + * process. The IP block is first enabled so it can be successfully + * reset. Returns 0 upon success or a negative error code upon + * failure. + */ +static int __init _setup_reset(struct omap_hwmod *oh) +{ + int r; - r = _enable(oh); - if (r) { - pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", - oh->name, oh->_state); - return 0; + if (oh->_state != _HWMOD_STATE_INITIALIZED) + return -EINVAL; + + if (oh->rst_lines_cnt == 0) { + r = _enable(oh); + if (r) { + pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", + oh->name, oh->_state); + return -EINVAL; + } } if (!(oh->flags & HWMOD_INIT_NO_RESET)) - _reset(oh); + r = _reset(oh); + + return r; +} + +/** + * _setup_postsetup - transition to the appropriate state after _setup + * @oh: struct omap_hwmod * + * + * Place an IP block represented by @oh into a "post-setup" state -- + * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that + * this function is called at the end of _setup().) The postsetup + * state for an IP block can be changed by calling + * omap_hwmod_enter_postsetup_state() early in the boot process, + * before one of the omap_hwmod_setup*() functions are called for the + * IP block. + * + * The IP block stays in this state until a PM runtime-based driver is + * loaded for that IP block. A post-setup state of IDLE is + * appropriate for almost all IP blocks with runtime PM-enabled + * drivers, since those drivers are able to enable the IP block. A + * post-setup state of ENABLED is appropriate for kernels with PM + * runtime disabled. The DISABLED state is appropriate for unusual IP + * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers + * included, since the WDTIMER starts running on reset and will reset + * the MPU if left active. + * + * This post-setup mechanism is deprecated. Once all of the OMAP + * drivers have been converted to use PM runtime, and all of the IP + * block data and interconnect data is available to the hwmod code, it + * should be possible to replace this mechanism with a "lazy reset" + * arrangement. In a "lazy reset" setup, each IP block is enabled + * when the driver first probes, then all remaining IP blocks without + * drivers are either shut down or enabled after the drivers have + * loaded. However, this cannot take place until the above + * preconditions have been met, since otherwise the late reset code + * has no way of knowing which IP blocks are in use by drivers, and + * which ones are unused. + * + * No return value. + */ +static void __init _setup_postsetup(struct omap_hwmod *oh) +{ + u8 postsetup_state; + + if (oh->rst_lines_cnt > 0) + return; postsetup_state = oh->_postsetup_state; if (postsetup_state == _HWMOD_STATE_UNKNOWN) @@ -1821,6 +2198,35 @@ static int _setup(struct omap_hwmod *oh, void *data) WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", oh->name, postsetup_state); + return; +} + +/** + * _setup - prepare IP block hardware for use + * @oh: struct omap_hwmod * + * @n: (unused, pass NULL) + * + * Configure the IP block represented by @oh. This may include + * enabling the IP block, resetting it, and placing it into a + * post-setup state, depending on the type of IP block and applicable + * flags. IP blocks are reset to prevent any previous configuration + * by the bootloader or previous operating system from interfering + * with power management or other parts of the system. The reset can + * be avoided; see omap_hwmod_no_setup_reset(). This is the second of + * two phases for hwmod initialization. Code called here generally + * affects the IP block hardware, or system integration hardware + * associated with the IP block. Returns 0. + */ +static int __init _setup(struct omap_hwmod *oh, void *data) +{ + if (oh->_state != _HWMOD_STATE_INITIALIZED) + return 0; + + _setup_iclk_autoidle(oh); + + if (!_setup_reset(oh)) + _setup_postsetup(oh); + return 0; } @@ -1843,8 +2249,6 @@ static int _setup(struct omap_hwmod *oh, void *data) */ static int __init _register(struct omap_hwmod *oh) { - int ms_id; - if (!oh || !oh->name || !oh->class || !oh->class->name || (oh->_state != _HWMOD_STATE_UNKNOWN)) return -EINVAL; @@ -1854,14 +2258,10 @@ static int __init _register(struct omap_hwmod *oh) if (_lookup(oh->name)) return -EEXIST; - ms_id = _find_mpu_port_index(oh); - if (!IS_ERR_VALUE(ms_id)) - oh->_mpu_port_index = ms_id; - else - oh->_int_flags |= _HWMOD_NO_MPU_PORT; - list_add_tail(&oh->node, &omap_hwmod_list); + INIT_LIST_HEAD(&oh->master_ports); + INIT_LIST_HEAD(&oh->slave_ports); spin_lock_init(&oh->_lock); oh->_state = _HWMOD_STATE_REGISTERED; @@ -1876,6 +2276,160 @@ static int __init _register(struct omap_hwmod *oh) return 0; } +/** + * _alloc_links - return allocated memory for hwmod links + * @ml: pointer to a struct omap_hwmod_link * for the master link + * @sl: pointer to a struct omap_hwmod_link * for the slave link + * + * Return pointers to two struct omap_hwmod_link records, via the + * addresses pointed to by @ml and @sl. Will first attempt to return + * memory allocated as part of a large initial block, but if that has + * been exhausted, will allocate memory itself. Since ideally this + * second allocation path will never occur, the number of these + * 'supplemental' allocations will be logged when debugging is + * enabled. Returns 0. + */ +static int __init _alloc_links(struct omap_hwmod_link **ml, + struct omap_hwmod_link **sl) +{ + unsigned int sz; + + if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { + *ml = &linkspace[free_ls++]; + *sl = &linkspace[free_ls++]; + return 0; + } + + sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; + + *sl = NULL; + *ml = alloc_bootmem(sz); + + memset(*ml, 0, sz); + + *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); + + ls_supp++; + pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", + ls_supp * LINKS_PER_OCP_IF); + + return 0; +}; + +/** + * _add_link - add an interconnect between two IP blocks + * @oi: pointer to a struct omap_hwmod_ocp_if record + * + * Add struct omap_hwmod_link records connecting the master IP block + * specified in @oi->master to @oi, and connecting the slave IP block + * specified in @oi->slave to @oi. This code is assumed to run before + * preemption or SMP has been enabled, thus avoiding the need for + * locking in this code. Changes to this assumption will require + * additional locking. Returns 0. + */ +static int __init _add_link(struct omap_hwmod_ocp_if *oi) +{ + struct omap_hwmod_link *ml, *sl; + + pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, + oi->slave->name); + + _alloc_links(&ml, &sl); + + ml->ocp_if = oi; + INIT_LIST_HEAD(&ml->node); + list_add(&ml->node, &oi->master->master_ports); + oi->master->masters_cnt++; + + sl->ocp_if = oi; + INIT_LIST_HEAD(&sl->node); + list_add(&sl->node, &oi->slave->slave_ports); + oi->slave->slaves_cnt++; + + return 0; +} + +/** + * _register_link - register a struct omap_hwmod_ocp_if + * @oi: struct omap_hwmod_ocp_if * + * + * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it + * has already been registered; -EINVAL if @oi is NULL or if the + * record pointed to by @oi is missing required fields; or 0 upon + * success. + * + * XXX The data should be copied into bootmem, so the original data + * should be marked __initdata and freed after init. This would allow + * unneeded omap_hwmods to be freed on multi-OMAP configurations. + */ +static int __init _register_link(struct omap_hwmod_ocp_if *oi) +{ + if (!oi || !oi->master || !oi->slave || !oi->user) + return -EINVAL; + + if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) + return -EEXIST; + + pr_debug("omap_hwmod: registering link from %s to %s\n", + oi->master->name, oi->slave->name); + + /* + * Register the connected hwmods, if they haven't been + * registered already + */ + if (oi->master->_state != _HWMOD_STATE_REGISTERED) + _register(oi->master); + + if (oi->slave->_state != _HWMOD_STATE_REGISTERED) + _register(oi->slave); + + _add_link(oi); + + oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; + + return 0; +} + +/** + * _alloc_linkspace - allocate large block of hwmod links + * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count + * + * Allocate a large block of struct omap_hwmod_link records. This + * improves boot time significantly by avoiding the need to allocate + * individual records one by one. If the number of records to + * allocate in the block hasn't been manually specified, this function + * will count the number of struct omap_hwmod_ocp_if records in @ois + * and use that to determine the allocation size. For SoC families + * that require multiple list registrations, such as OMAP3xxx, this + * estimation process isn't optimal, so manual estimation is advised + * in those cases. Returns -EEXIST if the allocation has already occurred + * or 0 upon success. + */ +static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) +{ + unsigned int i = 0; + unsigned int sz; + + if (linkspace) { + WARN(1, "linkspace already allocated\n"); + return -EEXIST; + } + + if (max_ls == 0) + while (ois[i++]) + max_ls += LINKS_PER_OCP_IF; + + sz = sizeof(struct omap_hwmod_link) * max_ls; + + pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", + __func__, sz, max_ls); + + linkspace = alloc_bootmem(sz); + + memset(linkspace, 0, sz); + + return 0; +} /* Public functions */ @@ -2004,120 +2558,101 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), } /** - * omap_hwmod_register - register an array of hwmods - * @ohs: pointer to an array of omap_hwmods to register + * omap_hwmod_register_links - register an array of hwmod links + * @ois: pointer to an array of omap_hwmod_ocp_if to register * * Intended to be called early in boot before the clock framework is - * initialized. If @ohs is not null, will register all omap_hwmods - * listed in @ohs that are valid for this chip. Returns 0. + * initialized. If @ois is not null, will register all omap_hwmods + * listed in @ois that are valid for this chip. Returns 0. */ -int __init omap_hwmod_register(struct omap_hwmod **ohs) +int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) { int r, i; - if (!ohs) + if (!ois) return 0; + if (!linkspace) { + if (_alloc_linkspace(ois)) { + pr_err("omap_hwmod: could not allocate link space\n"); + return -ENOMEM; + } + } + i = 0; do { - r = _register(ohs[i]); - WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, - r); - } while (ohs[++i]); + r = _register_link(ois[i]); + WARN(r && r != -EEXIST, + "omap_hwmod: _register_link(%s -> %s) returned %d\n", + ois[i]->master->name, ois[i]->slave->name, r); + } while (ois[++i]); return 0; } -/* - * _populate_mpu_rt_base - populate the virtual address for a hwmod +/** + * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up + * @oh: pointer to the hwmod currently being set up (usually not the MPU) * - * Must be called only from omap_hwmod_setup_*() so ioremap works properly. - * Assumes the caller takes care of locking if needed. + * If the hwmod data corresponding to the MPU subsystem IP block + * hasn't been initialized and set up yet, do so now. This must be + * done first since sleep dependencies may be added from other hwmods + * to the MPU. Intended to be called only by omap_hwmod_setup*(). No + * return value. */ -static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) +static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) { - if (oh->_state != _HWMOD_STATE_REGISTERED) - return 0; - - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) - return 0; - - oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); - - return 0; + if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) + pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", + __func__, MPU_INITIATOR_NAME); + else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) + omap_hwmod_setup_one(MPU_INITIATOR_NAME); } /** * omap_hwmod_setup_one - set up a single hwmod * @oh_name: const char * name of the already-registered hwmod to set up * - * Must be called after omap2_clk_init(). Resolves the struct clk - * names to struct clk pointers for each registered omap_hwmod. Also - * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon - * success. + * Initialize and set up a single hwmod. Intended to be used for a + * small number of early devices, such as the timer IP blocks used for + * the scheduler clock. Must be called after omap2_clk_init(). + * Resolves the struct clk names to struct clk pointers for each + * registered omap_hwmod. Also calls _setup() on each hwmod. Returns + * -EINVAL upon error or 0 upon success. */ int __init omap_hwmod_setup_one(const char *oh_name) { struct omap_hwmod *oh; - int r; pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); - if (!mpu_oh) { - pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", - oh_name, MPU_INITIATOR_NAME); - return -EINVAL; - } - oh = _lookup(oh_name); if (!oh) { WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); return -EINVAL; } - if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) - omap_hwmod_setup_one(MPU_INITIATOR_NAME); - - r = _populate_mpu_rt_base(oh, NULL); - if (IS_ERR_VALUE(r)) { - WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); - return -EINVAL; - } - - r = _init_clocks(oh, NULL); - if (IS_ERR_VALUE(r)) { - WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); - return -EINVAL; - } + _ensure_mpu_hwmod_is_setup(oh); + _init(oh, NULL); _setup(oh, NULL); return 0; } /** - * omap_hwmod_setup - do some post-clock framework initialization + * omap_hwmod_setup_all - set up all registered IP blocks * - * Must be called after omap2_clk_init(). Resolves the struct clk names - * to struct clk pointers for each registered omap_hwmod. Also calls - * _setup() on each hwmod. Returns 0 upon success. + * Initialize and set up all IP blocks registered with the hwmod code. + * Must be called after omap2_clk_init(). Resolves the struct clk + * names to struct clk pointers for each registered omap_hwmod. Also + * calls _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) { - int r; - - if (!mpu_oh) { - pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", - __func__, MPU_INITIATOR_NAME); - return -EINVAL; - } - - r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); - - r = omap_hwmod_for_each(_init_clocks, NULL); - WARN(IS_ERR_VALUE(r), - "omap_hwmod: %s: _init_clocks failed\n", __func__); + _ensure_mpu_hwmod_is_setup(NULL); + omap_hwmod_for_each(_init, NULL); omap_hwmod_for_each(_setup, NULL); return 0; @@ -2274,6 +2809,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh) return r; } +/* + * IP block data retrieval functions + */ + /** * omap_hwmod_count_resources - count number of struct resources needed by hwmod * @oh: struct omap_hwmod * @@ -2292,12 +2831,19 @@ int omap_hwmod_reset(struct omap_hwmod *oh) */ int omap_hwmod_count_resources(struct omap_hwmod *oh) { - int ret, i; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int ret; + int i = 0; ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); - for (i = 0; i < oh->slaves_cnt; i++) - ret += _count_ocp_if_addr_spaces(oh->slaves[i]); + p = oh->slave_ports.next; + + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + ret += _count_ocp_if_addr_spaces(os); + } return ret; } @@ -2314,7 +2860,9 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) */ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) { - int i, j, mpu_irqs_cnt, sdma_reqs_cnt; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; int r = 0; /* For each IRQ, DMA, memory area, fill in array.*/ @@ -2337,11 +2885,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) r++; } - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os; - int addr_cnt; + p = oh->slave_ports.next; - os = oh->slaves[i]; + i = 0; + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); addr_cnt = _count_ocp_if_addr_spaces(os); for (j = 0; j < addr_cnt; j++) { @@ -2357,6 +2905,69 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) } /** + * omap_hwmod_get_resource_byname - fetch IP block integration data by name + * @oh: struct omap_hwmod * to operate on + * @type: one of the IORESOURCE_* constants from include/linux/ioport.h + * @name: pointer to the name of the data to fetch (optional) + * @rsrc: pointer to a struct resource, allocated by the caller + * + * Retrieve MPU IRQ, SDMA request line, or address space start/end + * data for the IP block pointed to by @oh. The data will be filled + * into a struct resource record pointed to by @rsrc. The struct + * resource must be allocated by the caller. When @name is non-null, + * the data associated with the matching entry in the IRQ/SDMA/address + * space hwmod data arrays will be returned. If @name is null, the + * first array entry will be returned. Data order is not meaningful + * in hwmod data, so callers are strongly encouraged to use a non-null + * @name whenever possible to avoid unpredictable effects if hwmod + * data is later added that causes data ordering to change. This + * function is only intended for use by OMAP core code. Device + * drivers should not call this function - the appropriate bus-related + * data accessor functions should be used instead. Returns 0 upon + * success or a negative error code upon error. + */ +int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, + const char *name, struct resource *rsrc) +{ + int r; + unsigned int irq, dma; + u32 pa_start, pa_end; + + if (!oh || !rsrc) + return -EINVAL; + + if (type == IORESOURCE_IRQ) { + r = _get_mpu_irq_by_name(oh, name, &irq); + if (r) + return r; + + rsrc->start = irq; + rsrc->end = irq; + } else if (type == IORESOURCE_DMA) { + r = _get_sdma_req_by_name(oh, name, &dma); + if (r) + return r; + + rsrc->start = dma; + rsrc->end = dma; + } else if (type == IORESOURCE_MEM) { + r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); + if (r) + return r; + + rsrc->start = pa_start; + rsrc->end = pa_end; + } else { + return -EINVAL; + } + + rsrc->flags = type; + rsrc->name = name; + + return 0; +} + +/** * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain * @oh: struct omap_hwmod * * @@ -2370,6 +2981,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { struct clk *c; + struct omap_hwmod_ocp_if *oi; if (!oh) return NULL; @@ -2377,9 +2989,10 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) if (oh->_clk) { c = oh->_clk; } else { - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + oi = _find_mpu_rt_port(oh); + if (!oi) return NULL; - c = oh->slaves[oh->_mpu_port_index]->_clk; + c = oi->_clk; } if (!c->clkdm) @@ -2653,10 +3266,10 @@ int omap_hwmod_for_each_by_class(const char *classname, * @state: state that _setup() should leave the hwmod in * * Sets the hwmod state that @oh will enter at the end of _setup() - * (called by omap_hwmod_setup_*()). Only valid to call between - * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns - * 0 upon success or -EINVAL if there is a problem with the arguments - * or if the hwmod is in the wrong state. + * (called by omap_hwmod_setup_*()). See also the documentation + * for _setup_postsetup(), above. Returns 0 upon success or + * -EINVAL if there is a problem with the arguments or if the hwmod is + * in the wrong state. */ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) { diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a6bde34e443a..2c087ffc6a92 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -2,6 +2,7 @@ * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips * * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -32,707 +33,268 @@ /* * OMAP2420 hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap2420_mpu_hwmod; -static struct omap_hwmod omap2420_iva_hwmod; -static struct omap_hwmod omap2420_l3_main_hwmod; -static struct omap_hwmod omap2420_l4_core_hwmod; -static struct omap_hwmod omap2420_dss_core_hwmod; -static struct omap_hwmod omap2420_dss_dispc_hwmod; -static struct omap_hwmod omap2420_dss_rfbi_hwmod; -static struct omap_hwmod omap2420_dss_venc_hwmod; -static struct omap_hwmod omap2420_wd_timer2_hwmod; -static struct omap_hwmod omap2420_gpio1_hwmod; -static struct omap_hwmod omap2420_gpio2_hwmod; -static struct omap_hwmod omap2420_gpio3_hwmod; -static struct omap_hwmod omap2420_gpio4_hwmod; -static struct omap_hwmod omap2420_dma_system_hwmod; -static struct omap_hwmod omap2420_mcspi1_hwmod; -static struct omap_hwmod omap2420_mcspi2_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { - .master = &omap2420_l3_main_hwmod, - .slave = &omap2420_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { - .master = &omap2420_mpu_hwmod, - .slave = &omap2420_l3_main_hwmod, - .user = OCP_USER_MPU, -}; - -/* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { - &omap2420_mpu__l3_main, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap2420_dss__l3 = { - .master = &omap2420_dss_core_hwmod, - .slave = &omap2420_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { - &omap2420_l3_main__l4_core, -}; - -/* L3 */ -static struct omap_hwmod omap2420_l3_main_hwmod = { - .name = "l3_main", - .class = &l3_hwmod_class, - .masters = omap2420_l3_main_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), - .slaves = omap2420_l3_main_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod omap2420_l4_wkup_hwmod; -static struct omap_hwmod omap2420_uart1_hwmod; -static struct omap_hwmod omap2420_uart2_hwmod; -static struct omap_hwmod omap2420_uart3_hwmod; -static struct omap_hwmod omap2420_i2c1_hwmod; -static struct omap_hwmod omap2420_i2c2_hwmod; -static struct omap_hwmod omap2420_mcbsp1_hwmod; -static struct omap_hwmod omap2420_mcbsp2_hwmod; - -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcspi1_hwmod, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcspi2_hwmod, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Slave interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { - &omap2420_l3_main__l4_core, -}; - -/* Master interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { - &omap2420_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, - &omap2420_l4_core__i2c1, - &omap2420_l4_core__i2c2 -}; - -/* L4 CORE */ -static struct omap_hwmod omap2420_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .masters = omap2420_l4_core_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), - .slaves = omap2420_l4_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Slave interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { - &omap2420_l4_core__l4_wkup, -}; - -/* Master interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { -}; - -/* L4 WKUP */ -static struct omap_hwmod omap2420_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .masters = omap2420_l4_wkup_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), - .slaves = omap2420_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Master interfaces on the MPU device */ -static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { - &omap2420_mpu__l3_main, -}; - -/* MPU */ -static struct omap_hwmod omap2420_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "mpu_ck", - .masters = omap2420_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), -}; - /* - * IVA1 interface data + * IP blocks */ -/* IVA <- L3 interface */ -static struct omap_hwmod_ocp_if omap2420_l3__iva = { - .master = &omap2420_l3_main_hwmod, - .slave = &omap2420_iva_hwmod, - .clk = "iva1_ifck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* IVA1 (IVA1) */ +static struct omap_hwmod_class iva1_hwmod_class = { + .name = "iva1", }; -static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { - &omap2420_l3__iva, +static struct omap_hwmod_rst_info omap2420_iva_resets[] = { + { .name = "iva", .rst_shift = 8 }, }; -/* - * IVA2 (IVA2) - */ - static struct omap_hwmod omap2420_iva_hwmod = { .name = "iva", - .class = &iva_hwmod_class, - .masters = omap2420_iva_masters, - .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), + .class = &iva1_hwmod_class, + .clkdm_name = "iva1_clkdm", + .rst_lines = omap2420_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), + .main_clk = "iva1_ifck", }; -/* always-on timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, -}; - -/* pwm timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, -}; - -/* timer1 */ -static struct omap_hwmod omap2420_timer1_hwmod; - -static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { - { - .pa_start = 0x48028000, - .pa_end = 0x48028000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +/* DSP */ +static struct omap_hwmod_class dsp_hwmod_class = { + .name = "dsp", }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2420_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "mmu", .rst_shift = 1 }, }; -/* timer1 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { - &omap2420_l4_wkup__timer1, +static struct omap_hwmod omap2420_dsp_hwmod = { + .name = "dsp", + .class = &dsp_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap2420_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), + .main_clk = "dsp_fck", }; -/* timer1 hwmod */ -static struct omap_hwmod omap2420_timer1_hwmod = { - .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), - .class = &omap2xxx_timer_hwmod_class, +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* timer2 */ -static struct omap_hwmod omap2420_timer2_hwmod; - -/* l4_core -> timer2 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_1, + .reset = &omap_i2c_reset, }; -/* timer2 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { - &omap2420_l4_core__timer2, +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_NO_FIFO | + OMAP_I2C_FLAG_SIMPLE_CLOCK | + OMAP_I2C_FLAG_16BIT_DATA_REG | + OMAP_I2C_FLAG_BUS_SHIFT_2, }; -/* timer2 hwmod */ -static struct omap_hwmod omap2420_timer2_hwmod = { - .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, - .main_clk = "gpt2_fck", +/* I2C1 */ +static struct omap_hwmod omap2420_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = omap2_i2c1_mpu_irqs, + .sdma_reqs = omap2_i2c1_sdma_reqs, + .main_clk = "i2c1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT2_SHIFT, .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer3 */ -static struct omap_hwmod omap2420_timer3_hwmod; - -/* l4_core -> timer3 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { - &omap2420_l4_core__timer3, -}; - -/* timer3 hwmod */ -static struct omap_hwmod omap2420_timer3_hwmod = { - .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, - .main_clk = "gpt3_fck", - .prcm = { - .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT3_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP2420_EN_I2C1_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer4 */ -static struct omap_hwmod omap2420_timer4_hwmod; - -/* l4_core -> timer4 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { - &omap2420_l4_core__timer4, + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .flags = HWMOD_16BIT_REG, }; -/* timer4 hwmod */ -static struct omap_hwmod omap2420_timer4_hwmod = { - .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, - .main_clk = "gpt4_fck", +/* I2C2 */ +static struct omap_hwmod omap2420_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = omap2_i2c2_mpu_irqs, + .sdma_reqs = omap2_i2c2_sdma_reqs, + .main_clk = "i2c2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT4_SHIFT, .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer5 */ -static struct omap_hwmod omap2420_timer5_hwmod; - -/* l4_core -> timer5 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { - &omap2420_l4_core__timer5, -}; - -/* timer5 hwmod */ -static struct omap_hwmod omap2420_timer5_hwmod = { - .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, - .main_clk = "gpt5_fck", - .prcm = { - .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT5_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP2420_EN_I2C2_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - - -/* timer6 */ -static struct omap_hwmod omap2420_timer6_hwmod; - -/* l4_core -> timer6 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { - &omap2420_l4_core__timer6, + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .flags = HWMOD_16BIT_REG, }; -/* timer6 hwmod */ -static struct omap_hwmod omap2420_timer6_hwmod = { - .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, - .main_clk = "gpt6_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT6_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), - .class = &omap2xxx_timer_hwmod_class, +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .lch_count = 32, }; -/* timer7 */ -static struct omap_hwmod omap2420_timer7_hwmod; - -/* l4_core -> timer7 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap2420_dma_system_hwmod = { + .name = "dma", + .class = &omap2xxx_dma_hwmod_class, + .mpu_irqs = omap2_dma_system_irqs, + .main_clk = "core_l3_ck", + .dev_attr = &dma_dev_attr, + .flags = HWMOD_NO_IDLEST, }; -/* timer7 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { - &omap2420_l4_core__timer7, +/* mailbox */ +static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { + { .name = "dsp", .irq = 26 }, + { .name = "iva", .irq = 34 }, + { .irq = -1 } }; -/* timer7 hwmod */ -static struct omap_hwmod omap2420_timer7_hwmod = { - .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, - .main_clk = "gpt7_fck", +static struct omap_hwmod omap2420_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2xxx_mailbox_hwmod_class, + .mpu_irqs = omap2420_mailbox_irqs, + .main_clk = "mailboxes_ick", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), - .class = &omap2xxx_timer_hwmod_class, }; -/* timer8 */ -static struct omap_hwmod omap2420_timer8_hwmod; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ -/* l4_core -> timer8 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { + .name = "mcbsp", }; -/* timer8 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { - &omap2420_l4_core__timer8, +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .irq = -1 } }; -/* timer8 hwmod */ -static struct omap_hwmod omap2420_timer8_hwmod = { - .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, - .main_clk = "gpt8_fck", +static struct omap_hwmod omap2420_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp1_irqs, + .sdma_reqs = omap2_mcbsp1_sdma_reqs, + .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer9 */ -static struct omap_hwmod omap2420_timer9_hwmod; - -/* l4_core -> timer9 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer9 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { - &omap2420_l4_core__timer9, +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .irq = -1 } }; -/* timer9 hwmod */ -static struct omap_hwmod omap2420_timer9_hwmod = { - .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, - .main_clk = "gpt9_fck", +static struct omap_hwmod omap2420_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp2_irqs, + .sdma_reqs = omap2_mcbsp2_sdma_reqs, + .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), - .class = &omap2xxx_timer_hwmod_class, }; -/* timer10 */ -static struct omap_hwmod omap2420_timer10_hwmod; +/* + * interfaces + */ -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2420_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer10 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { - &omap2420_l4_core__timer10, -}; - -/* timer10 hwmod */ -static struct omap_hwmod omap2420_timer10_hwmod = { - .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, - .main_clk = "gpt10_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT10_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), - .class = &omap2xxx_timer_hwmod_class, +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2420_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer11 */ -static struct omap_hwmod omap2420_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, +/* IVA <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__iva = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2420_iva_hwmod, + .clk = "core_l3_ck", .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer11 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { - &omap2420_l4_core__timer11, +/* DSP <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__dsp = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2420_dsp_hwmod, + .clk = "dsp_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer11 hwmod */ -static struct omap_hwmod omap2420_timer11_hwmod = { - .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, - .main_clk = "gpt11_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT11_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, - }, +static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { + { + .pa_start = 0x48028000, + .pa_end = 0x48028000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), - .class = &omap2xxx_timer_hwmod_class, + { } }; -/* timer12 */ -static struct omap_hwmod omap2420_timer12_hwmod; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2420_timer1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer12 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { - &omap2420_l4_core__timer12, -}; - -/* timer12 hwmod */ -static struct omap_hwmod omap2420_timer12_hwmod = { - .name = "timer12", - .mpu_irqs = omap2xxx_timer12_mpu_irqs, - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT12_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer12_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { { @@ -744,363 +306,13 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_wd_timer2_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_wd_timer2_hwmod, .clk = "mpu_wdt_ick", .addr = omap2420_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { - &omap2420_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap2420_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2xxx_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, - }, - }, - .slaves = omap2420_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), -}; - -/* UART1 */ - -static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { - &omap2_l4_core__uart1, -}; - -static struct omap_hwmod omap2420_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, - }, - }, - .slaves = omap2420_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), - .class = &omap2_uart_class, -}; - -/* UART2 */ - -static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { - &omap2_l4_core__uart2, -}; - -static struct omap_hwmod omap2420_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .slaves = omap2420_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), - .class = &omap2_uart_class, -}; - -/* UART3 */ - -static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { - &omap2_l4_core__uart3, -}; - -static struct omap_hwmod omap2420_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .slaves = omap2420_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), - .class = &omap2_uart_class, -}; - -/* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { - &omap2420_dss__l3, -}; - -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { - &omap2420_l4_core__dss, -}; - -static struct omap_hwmod_opt_clk dss_opt_clks[] = { - /* - * The DSS HW needs all DSS clocks enabled during reset. The dss_core - * driver does not use these clocks. - */ - { .role = "tv_clk", .clk = "dss_54m_fck" }, - { .role = "sys_clk", .clk = "dss2_fck" }, -}; - -static struct omap_hwmod omap2420_dss_core_hwmod = { - .name = "dss_core", - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_fck", /* instead of dss_fck */ - .sdma_reqs = omap2xxx_dss_sdma_chs, - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap2420_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), - .masters = omap2420_dss_masters, - .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, -}; - -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { - &omap2420_l4_core__dss_dispc, -}; - -static struct omap_hwmod omap2420_dss_dispc_hwmod = { - .name = "dss_dispc", - .class = &omap2_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .slaves = omap2420_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), - .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr -}; - -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { - &omap2420_l4_core__dss_rfbi, -}; - -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { - { .role = "ick", .clk = "dss_ick" }, -}; - -static struct omap_hwmod omap2420_dss_rfbi_hwmod = { - .name = "dss_rfbi", - .class = &omap2_rfbi_hwmod_class, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .opt_clks = dss_rfbi_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap2420_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { - &omap2420_l4_core__dss_venc, -}; - -static struct omap_hwmod omap2420_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap2_venc_hwmod_class, - .main_clk = "dss_54m_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .slaves = omap2420_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* I2C common */ -static struct omap_hwmod_class_sysconfig i2c_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x20, - .syss_offs = 0x10, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class i2c_class = { - .name = "i2c", - .sysc = &i2c_sysc, - .rev = OMAP_I2C_IP_VERSION_1, - .reset = &omap_i2c_reset, -}; - -static struct omap_i2c_dev_attr i2c_dev_attr = { - .flags = OMAP_I2C_FLAG_NO_FIFO | - OMAP_I2C_FLAG_SIMPLE_CLOCK | - OMAP_I2C_FLAG_16BIT_DATA_REG | - OMAP_I2C_FLAG_BUS_SHIFT_2, -}; - -/* I2C1 */ - -static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { - &omap2420_l4_core__i2c1, -}; - -static struct omap_hwmod omap2420_i2c1_hwmod = { - .name = "i2c1", - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, - .main_clk = "i2c1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, - }, - }, - .slaves = omap2420_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, - .flags = HWMOD_16BIT_REG, -}; - -/* I2C2 */ - -static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { - &omap2420_l4_core__i2c2, -}; - -static struct omap_hwmod omap2420_i2c2_hwmod = { - .name = "i2c2", - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, - .main_clk = "i2c2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, - }, - }, - .slaves = omap2420_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, - .flags = HWMOD_16BIT_REG, -}; - /* l4_wkup -> gpio1 */ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { { @@ -1112,8 +324,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio1_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio1_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -1130,8 +342,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio2_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio2_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -1148,8 +360,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio3_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio3_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -1166,408 +378,100 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio4_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio4_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = false, -}; - -/* gpio1 */ -static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { - &omap2420_l4_wkup__gpio1, -}; - -static struct omap_hwmod omap2420_gpio1_hwmod = { - .name = "gpio1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio2 */ -static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { - &omap2420_l4_wkup__gpio2, -}; - -static struct omap_hwmod omap2420_gpio2_hwmod = { - .name = "gpio2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio3 */ -static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { - &omap2420_l4_wkup__gpio3, -}; - -static struct omap_hwmod omap2420_gpio3_hwmod = { - .name = "gpio3", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio4 */ -static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { - &omap2420_l4_wkup__gpio4, -}; - -static struct omap_hwmod omap2420_gpio4_hwmod = { - .name = "gpio4", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32, - .lch_count = 32, -}; - /* dma_system -> L3 */ static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { .master = &omap2420_dma_system_hwmod, - .slave = &omap2420_l3_main_hwmod, + .slave = &omap2xxx_l3_main_hwmod, .clk = "core_l3_ck", .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { - &omap2420_dma_system__l3, -}; - /* l4_core -> dma_system */ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_dma_system_hwmod, .clk = "sdma_ick", .addr = omap2_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { - &omap2420_l4_core__dma_system, -}; - -static struct omap_hwmod omap2420_dma_system_hwmod = { - .name = "dma", - .class = &omap2xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, - .main_clk = "core_l3_ck", - .slaves = omap2420_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), - .masters = omap2420_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, -}; - -/* mailbox */ -static struct omap_hwmod omap2420_mailbox_hwmod; -static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { - { .name = "dsp", .irq = 26 }, - { .name = "iva", .irq = 34 }, - { .irq = -1 } -}; - /* l4_core -> mailbox */ static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mailbox_hwmod, .addr = omap2_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { - &omap2420_l4_core__mailbox, -}; - -static struct omap_hwmod omap2420_mailbox_hwmod = { - .name = "mailbox", - .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2420_mailbox_irqs, - .main_clk = "mailboxes_ick", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, - }, - }, - .slaves = omap2420_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), -}; - -/* mcspi1 */ -static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { - &omap2420_l4_core__mcspi1, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - -static struct omap_hwmod omap2420_mcspi1_hwmod = { - .name = "mcspi1_hwmod", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, - }, - }, - .slaves = omap2420_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, -}; - -/* mcspi2 */ -static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { - &omap2420_l4_core__mcspi2, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - -static struct omap_hwmod omap2420_mcspi2_hwmod = { - .name = "mcspi2_hwmod", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, - }, - }, - .slaves = omap2420_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, -}; - -/* - * 'mcbsp' class - * multi channel buffered serial port controller - */ - -static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { - .name = "mcbsp", -}; - -/* mcbsp1 */ -static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } -}; - /* l4_core -> mcbsp1 */ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp1_hwmod, .clk = "mcbsp1_ick", .addr = omap2_mcbsp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { - &omap2420_l4_core__mcbsp1, -}; - -static struct omap_hwmod omap2420_mcbsp1_hwmod = { - .name = "mcbsp1", - .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, - .main_clk = "mcbsp1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, - }, - }, - .slaves = omap2420_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), -}; - -/* mcbsp2 */ -static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } -}; - /* l4_core -> mcbsp2 */ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp2_hwmod, .clk = "mcbsp2_ick", .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { +static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { + &omap2xxx_l3_main__l4_core, + &omap2xxx_mpu__l3_main, + &omap2xxx_dss__l3, + &omap2xxx_l4_core__mcspi1, + &omap2xxx_l4_core__mcspi2, + &omap2xxx_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, + &omap2420_l4_core__i2c1, + &omap2420_l4_core__i2c2, + &omap2420_l3__iva, + &omap2420_l3__dsp, + &omap2420_l4_wkup__timer1, + &omap2xxx_l4_core__timer2, + &omap2xxx_l4_core__timer3, + &omap2xxx_l4_core__timer4, + &omap2xxx_l4_core__timer5, + &omap2xxx_l4_core__timer6, + &omap2xxx_l4_core__timer7, + &omap2xxx_l4_core__timer8, + &omap2xxx_l4_core__timer9, + &omap2xxx_l4_core__timer10, + &omap2xxx_l4_core__timer11, + &omap2xxx_l4_core__timer12, + &omap2420_l4_wkup__wd_timer2, + &omap2xxx_l4_core__dss, + &omap2xxx_l4_core__dss_dispc, + &omap2xxx_l4_core__dss_rfbi, + &omap2xxx_l4_core__dss_venc, + &omap2420_l4_wkup__gpio1, + &omap2420_l4_wkup__gpio2, + &omap2420_l4_wkup__gpio3, + &omap2420_l4_wkup__gpio4, + &omap2420_dma_system__l3, + &omap2420_l4_core__dma_system, + &omap2420_l4_core__mailbox, + &omap2420_l4_core__mcbsp1, &omap2420_l4_core__mcbsp2, -}; - -static struct omap_hwmod omap2420_mcbsp2_hwmod = { - .name = "mcbsp2", - .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, - .main_clk = "mcbsp2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, - }, - }, - .slaves = omap2420_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), -}; - -static __initdata struct omap_hwmod *omap2420_hwmods[] = { - &omap2420_l3_main_hwmod, - &omap2420_l4_core_hwmod, - &omap2420_l4_wkup_hwmod, - &omap2420_mpu_hwmod, - &omap2420_iva_hwmod, - - &omap2420_timer1_hwmod, - &omap2420_timer2_hwmod, - &omap2420_timer3_hwmod, - &omap2420_timer4_hwmod, - &omap2420_timer5_hwmod, - &omap2420_timer6_hwmod, - &omap2420_timer7_hwmod, - &omap2420_timer8_hwmod, - &omap2420_timer9_hwmod, - &omap2420_timer10_hwmod, - &omap2420_timer11_hwmod, - &omap2420_timer12_hwmod, - - &omap2420_wd_timer2_hwmod, - &omap2420_uart1_hwmod, - &omap2420_uart2_hwmod, - &omap2420_uart3_hwmod, - /* dss class */ - &omap2420_dss_core_hwmod, - &omap2420_dss_dispc_hwmod, - &omap2420_dss_rfbi_hwmod, - &omap2420_dss_venc_hwmod, - /* i2c class */ - &omap2420_i2c1_hwmod, - &omap2420_i2c2_hwmod, - - /* gpio class */ - &omap2420_gpio1_hwmod, - &omap2420_gpio2_hwmod, - &omap2420_gpio3_hwmod, - &omap2420_gpio4_hwmod, - - /* dma_system class*/ - &omap2420_dma_system_hwmod, - - /* mailbox class */ - &omap2420_mailbox_hwmod, - - /* mcbsp class */ - &omap2420_mcbsp1_hwmod, - &omap2420_mcbsp2_hwmod, - - /* mcspi class */ - &omap2420_mcspi1_hwmod, - &omap2420_mcspi2_hwmod, NULL, }; int __init omap2420_hwmod_init(void) { - return omap_hwmod_register(omap2420_hwmods); + return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 04a3885f4475..71d9f8824f9d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -2,6 +2,7 @@ * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips * * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -33,1044 +34,29 @@ /* * OMAP2430 hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap2430_mpu_hwmod; -static struct omap_hwmod omap2430_iva_hwmod; -static struct omap_hwmod omap2430_l3_main_hwmod; -static struct omap_hwmod omap2430_l4_core_hwmod; -static struct omap_hwmod omap2430_dss_core_hwmod; -static struct omap_hwmod omap2430_dss_dispc_hwmod; -static struct omap_hwmod omap2430_dss_rfbi_hwmod; -static struct omap_hwmod omap2430_dss_venc_hwmod; -static struct omap_hwmod omap2430_wd_timer2_hwmod; -static struct omap_hwmod omap2430_gpio1_hwmod; -static struct omap_hwmod omap2430_gpio2_hwmod; -static struct omap_hwmod omap2430_gpio3_hwmod; -static struct omap_hwmod omap2430_gpio4_hwmod; -static struct omap_hwmod omap2430_gpio5_hwmod; -static struct omap_hwmod omap2430_dma_system_hwmod; -static struct omap_hwmod omap2430_mcbsp1_hwmod; -static struct omap_hwmod omap2430_mcbsp2_hwmod; -static struct omap_hwmod omap2430_mcbsp3_hwmod; -static struct omap_hwmod omap2430_mcbsp4_hwmod; -static struct omap_hwmod omap2430_mcbsp5_hwmod; -static struct omap_hwmod omap2430_mcspi1_hwmod; -static struct omap_hwmod omap2430_mcspi2_hwmod; -static struct omap_hwmod omap2430_mcspi3_hwmod; -static struct omap_hwmod omap2430_mmc1_hwmod; -static struct omap_hwmod omap2430_mmc2_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { - .master = &omap2430_mpu_hwmod, - .slave = &omap2430_l3_main_hwmod, - .user = OCP_USER_MPU, -}; - -/* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { - &omap2430_mpu__l3_main, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap2430_dss__l3 = { - .master = &omap2430_dss_core_hwmod, - .slave = &omap2430_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { - &omap2430_l3_main__l4_core, -}; - -/* L3 */ -static struct omap_hwmod omap2430_l3_main_hwmod = { - .name = "l3_main", - .class = &l3_hwmod_class, - .masters = omap2430_l3_main_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), - .slaves = omap2430_l3_main_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod omap2430_l4_wkup_hwmod; -static struct omap_hwmod omap2430_uart1_hwmod; -static struct omap_hwmod omap2430_uart2_hwmod; -static struct omap_hwmod omap2430_uart3_hwmod; -static struct omap_hwmod omap2430_i2c1_hwmod; -static struct omap_hwmod omap2430_i2c2_hwmod; - -static struct omap_hwmod omap2430_usbhsotg_hwmod; - -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { - .master = &omap2430_usbhsotg_hwmod, - .slave = &omap2430_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* -* usbhsotg interface data -*/ -static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { - { - .pa_start = OMAP243X_HS_BASE, - .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core ->usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_usbhsotg_hwmod, - .clk = "usb_l4_ick", - .addr = omap2430_usbhsotg_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { - &omap2430_usbhsotg__l3, -}; - -static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { - &omap2430_l4_core__usbhsotg, -}; - -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Slave interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { - &omap2430_l3_main__l4_core, -}; - -/* Master interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { - &omap2430_l4_core__l4_wkup, - &omap2430_l4_core__mmc1, - &omap2430_l4_core__mmc2, -}; - -/* L4 CORE */ -static struct omap_hwmod omap2430_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .masters = omap2430_l4_core_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), - .slaves = omap2430_l4_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Slave interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { - &omap2430_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, -}; - -/* Master interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { -}; - -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi1_hwmod, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi2_hwmod, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi3_hwmod, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 WKUP */ -static struct omap_hwmod omap2430_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .masters = omap2430_l4_wkup_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), - .slaves = omap2430_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Master interfaces on the MPU device */ -static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { - &omap2430_mpu__l3_main, -}; - -/* MPU */ -static struct omap_hwmod omap2430_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "mpu_ck", - .masters = omap2430_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), -}; - -/* - * IVA2_1 interface data + * IP blocks */ -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap2430_l3__iva = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_iva_hwmod, - .clk = "dsp_fck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { - &omap2430_l3__iva, +/* IVA2 (IVA2) */ +static struct omap_hwmod_rst_info omap2430_iva_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "mmu", .rst_shift = 1 }, }; -/* - * IVA2 (IVA2) - */ - static struct omap_hwmod omap2430_iva_hwmod = { .name = "iva", .class = &iva_hwmod_class, - .masters = omap2430_iva_masters, - .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), -}; - -/* always-on timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, -}; - -/* pwm timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, -}; - -/* timer1 */ -static struct omap_hwmod omap2430_timer1_hwmod; - -static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { - { - .pa_start = 0x49018000, - .pa_end = 0x49018000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2430_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { - &omap2430_l4_wkup__timer1, -}; - -/* timer1 hwmod */ -static struct omap_hwmod omap2430_timer1_hwmod = { - .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer2 */ -static struct omap_hwmod omap2430_timer2_hwmod; - -/* l4_core -> timer2 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { - &omap2430_l4_core__timer2, -}; - -/* timer2 hwmod */ -static struct omap_hwmod omap2430_timer2_hwmod = { - .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, - .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT2_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer3 */ -static struct omap_hwmod omap2430_timer3_hwmod; - -/* l4_core -> timer3 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { - &omap2430_l4_core__timer3, -}; - -/* timer3 hwmod */ -static struct omap_hwmod omap2430_timer3_hwmod = { - .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, - .main_clk = "gpt3_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT3_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer4 */ -static struct omap_hwmod omap2430_timer4_hwmod; - -/* l4_core -> timer4 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { - &omap2430_l4_core__timer4, -}; - -/* timer4 hwmod */ -static struct omap_hwmod omap2430_timer4_hwmod = { - .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, - .main_clk = "gpt4_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT4_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer5 */ -static struct omap_hwmod omap2430_timer5_hwmod; - -/* l4_core -> timer5 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { - &omap2430_l4_core__timer5, -}; - -/* timer5 hwmod */ -static struct omap_hwmod omap2430_timer5_hwmod = { - .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, - .main_clk = "gpt5_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT5_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer6 */ -static struct omap_hwmod omap2430_timer6_hwmod; - -/* l4_core -> timer6 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { - &omap2430_l4_core__timer6, -}; - -/* timer6 hwmod */ -static struct omap_hwmod omap2430_timer6_hwmod = { - .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, - .main_clk = "gpt6_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT6_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer7 */ -static struct omap_hwmod omap2430_timer7_hwmod; - -/* l4_core -> timer7 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer7 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { - &omap2430_l4_core__timer7, -}; - -/* timer7 hwmod */ -static struct omap_hwmod omap2430_timer7_hwmod = { - .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, - .main_clk = "gpt7_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT7_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer8 */ -static struct omap_hwmod omap2430_timer8_hwmod; - -/* l4_core -> timer8 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer8 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { - &omap2430_l4_core__timer8, -}; - -/* timer8 hwmod */ -static struct omap_hwmod omap2430_timer8_hwmod = { - .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, - .main_clk = "gpt8_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT8_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer9 */ -static struct omap_hwmod omap2430_timer9_hwmod; - -/* l4_core -> timer9 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { - &omap2430_l4_core__timer9, -}; - -/* timer9 hwmod */ -static struct omap_hwmod omap2430_timer9_hwmod = { - .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, - .main_clk = "gpt9_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT9_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer10 */ -static struct omap_hwmod omap2430_timer10_hwmod; - -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { - &omap2430_l4_core__timer10, -}; - -/* timer10 hwmod */ -static struct omap_hwmod omap2430_timer10_hwmod = { - .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, - .main_clk = "gpt10_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT10_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer11 */ -static struct omap_hwmod omap2430_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { - &omap2430_l4_core__timer11, -}; - -/* timer11 hwmod */ -static struct omap_hwmod omap2430_timer11_hwmod = { - .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, - .main_clk = "gpt11_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT11_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer12 */ -static struct omap_hwmod omap2430_timer12_hwmod; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer12 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { - &omap2430_l4_core__timer12, -}; - -/* timer12 hwmod */ -static struct omap_hwmod omap2430_timer12_hwmod = { - .name = "timer12", - .mpu_irqs = omap2xxx_timer12_mpu_irqs, - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT12_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer12_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { - { - .pa_start = 0x49016000, - .pa_end = 0x4901607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2430_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { - &omap2430_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap2430_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2xxx_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, - }, - }, - .slaves = omap2430_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), -}; - -/* UART1 */ - -static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { - &omap2_l4_core__uart1, -}; - -static struct omap_hwmod omap2430_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, - }, - }, - .slaves = omap2430_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), - .class = &omap2_uart_class, -}; - -/* UART2 */ - -static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { - &omap2_l4_core__uart2, -}; - -static struct omap_hwmod omap2430_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .slaves = omap2430_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), - .class = &omap2_uart_class, -}; - -/* UART3 */ - -static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { - &omap2_l4_core__uart3, -}; - -static struct omap_hwmod omap2430_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .slaves = omap2430_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), - .class = &omap2_uart_class, -}; - -/* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { - &omap2430_dss__l3, -}; - -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { - &omap2430_l4_core__dss, -}; - -static struct omap_hwmod_opt_clk dss_opt_clks[] = { - /* - * The DSS HW needs all DSS clocks enabled during reset. The dss_core - * driver does not use these clocks. - */ - { .role = "tv_clk", .clk = "dss_54m_fck" }, - { .role = "sys_clk", .clk = "dss2_fck" }, -}; - -static struct omap_hwmod omap2430_dss_core_hwmod = { - .name = "dss_core", - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_fck", /* instead of dss_fck */ - .sdma_reqs = omap2xxx_dss_sdma_chs, - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap2430_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), - .masters = omap2430_dss_masters, - .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, -}; - -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { - &omap2430_l4_core__dss_dispc, -}; - -static struct omap_hwmod omap2430_dss_dispc_hwmod = { - .name = "dss_dispc", - .class = &omap2_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .slaves = omap2430_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), - .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr -}; - -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { - &omap2430_l4_core__dss_rfbi, -}; - -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { - { .role = "ick", .clk = "dss_ick" }, -}; - -static struct omap_hwmod omap2430_dss_rfbi_hwmod = { - .name = "dss_rfbi", - .class = &omap2_rfbi_hwmod_class, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .opt_clks = dss_rfbi_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap2430_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { - &omap2430_l4_core__dss_venc, -}; - -static struct omap_hwmod omap2430_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap2_venc_hwmod_class, - .main_clk = "dss_54m_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .slaves = omap2430_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), - .flags = HWMOD_NO_IDLEST, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap2430_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), + .main_clk = "dsp_fck", }; /* I2C common */ @@ -1098,11 +84,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* I2C1 */ - -static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { - &omap2430_l4_core__i2c1, -}; - static struct omap_hwmod omap2430_i2c1_hwmod = { .name = "i2c1", .flags = HWMOD_16BIT_REG, @@ -1126,18 +107,11 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, }, }, - .slaves = omap2430_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, }; /* I2C2 */ - -static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { - &omap2430_l4_core__i2c2, -}; - static struct omap_hwmod omap2430_i2c2_hwmod = { .name = "i2c2", .flags = HWMOD_16BIT_REG, @@ -1153,218 +127,16 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, }, }, - .slaves = omap2430_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { - { - .pa_start = 0x4900C000, - .pa_end = 0x4900C1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio1_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { - { - .pa_start = 0x4900E000, - .pa_end = 0x4900E1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio2_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { - { - .pa_start = 0x49010000, - .pa_end = 0x490101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio3_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { - { - .pa_start = 0x49012000, - .pa_end = 0x490121ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio4_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> gpio5 */ -static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { - { - .pa_start = 0x480B6000, - .pa_end = 0x480B61ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_gpio5_hwmod, - .clk = "gpio5_ick", - .addr = omap2430_gpio5_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = false, -}; - -/* gpio1 */ -static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { - &omap2430_l4_wkup__gpio1, -}; - -static struct omap_hwmod omap2430_gpio1_hwmod = { - .name = "gpio1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio2 */ -static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { - &omap2430_l4_wkup__gpio2, -}; - -static struct omap_hwmod omap2430_gpio2_hwmod = { - .name = "gpio2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio3 */ -static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { - &omap2430_l4_wkup__gpio3, -}; - -static struct omap_hwmod omap2430_gpio3_hwmod = { - .name = "gpio3", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio4 */ -static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { - &omap2430_l4_wkup__gpio4, -}; - -static struct omap_hwmod omap2430_gpio4_hwmod = { - .name = "gpio4", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - /* gpio5 */ static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ { .irq = -1 } }; -static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { - &omap2430_l4_core__gpio5, -}; - static struct omap_hwmod omap2430_gpio5_hwmod = { .name = "gpio5", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -1379,10 +151,8 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, }, }, - .slaves = omap2430_gpio5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .dev_attr = &omap2xxx_gpio_dev_attr, }; /* dma attributes */ @@ -1392,66 +162,21 @@ static struct omap_dma_dev_attr dma_dev_attr = { .lch_count = 32, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { - .master = &omap2430_dma_system_hwmod, - .slave = &omap2430_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { - &omap2430_dma_system__l3, -}; - -/* l4_core -> dma_system */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dma_system_hwmod, - .clk = "sdma_ick", - .addr = omap2_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { - &omap2430_l4_core__dma_system, -}; - static struct omap_hwmod omap2430_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, .mpu_irqs = omap2_dma_system_irqs, .main_clk = "core_l3_ck", - .slaves = omap2430_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), - .masters = omap2430_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, }; /* mailbox */ -static struct omap_hwmod omap2430_mailbox_hwmod; static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { { .irq = 26 }, { .irq = -1 } }; -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mailbox_hwmod, - .addr = omap2_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { - &omap2430_l4_core__mailbox, -}; - static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -1466,66 +191,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .slaves = omap2430_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), -}; - -/* mcspi1 */ -static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { - &omap2430_l4_core__mcspi1, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - -static struct omap_hwmod omap2430_mcspi1_hwmod = { - .name = "mcspi1_hwmod", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, - }, - }, - .slaves = omap2430_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, -}; - -/* mcspi2 */ -static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { - &omap2430_l4_core__mcspi2, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - -static struct omap_hwmod omap2430_mcspi2_hwmod = { - .name = "mcspi2_hwmod", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, - }, - }, - .slaves = omap2430_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, }; /* mcspi3 */ @@ -1542,16 +207,12 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { - &omap2430_l4_core__mcspi3, -}; - static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { .num_chipselect = 2, }; static struct omap_hwmod omap2430_mcspi3_hwmod = { - .name = "mcspi3_hwmod", + .name = "mcspi3", .mpu_irqs = omap2430_mcspi3_mpu_irqs, .sdma_reqs = omap2430_mcspi3_sdma_reqs, .main_clk = "mcspi3_fck", @@ -1564,15 +225,11 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, }, }, - .slaves = omap2430_mcspi3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi3_dev_attr, }; -/* - * usbhsotg - */ +/* usbhsotg */ static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { .rev_offs = 0x0400, .sysc_offs = 0x0404, @@ -1611,10 +268,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, }, }, - .masters = omap2430_usbhsotg_masters, - .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), - .slaves = omap2430_usbhsotg_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), .class = &usbotg_class, /* * Erratum ID: i479 idle_req / idle_ack mechanism potentially @@ -1652,20 +305,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { - &omap2430_l4_core__mcbsp1, -}; - static struct omap_hwmod omap2430_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2430_mcbsp_hwmod_class, @@ -1681,8 +320,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, }, }, - .slaves = omap2430_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), }; /* mcbsp2 */ @@ -1693,20 +330,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { - &omap2430_l4_core__mcbsp2, -}; - static struct omap_hwmod omap2430_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2430_mcbsp_hwmod_class, @@ -1722,8 +345,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, }, }, - .slaves = omap2430_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), }; /* mcbsp3 */ @@ -1734,30 +355,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808C000, - .pa_end = 0x4808C0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp3_hwmod, - .clk = "mcbsp3_ick", - .addr = omap2430_mcbsp3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp3 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { - &omap2430_l4_core__mcbsp3, -}; - static struct omap_hwmod omap2430_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap2430_mcbsp_hwmod_class, @@ -1773,8 +370,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, }, }, - .slaves = omap2430_mcbsp3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), }; /* mcbsp4 */ @@ -1791,30 +386,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808E000, - .pa_end = 0x4808E0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp4_hwmod, - .clk = "mcbsp4_ick", - .addr = omap2430_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp4 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { - &omap2430_l4_core__mcbsp4, -}; - static struct omap_hwmod omap2430_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap2430_mcbsp_hwmod_class, @@ -1830,8 +401,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, }, }, - .slaves = omap2430_mcbsp4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), }; /* mcbsp5 */ @@ -1848,30 +417,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp5 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp5_hwmod, - .clk = "mcbsp5_ick", - .addr = omap2430_mcbsp5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp5 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { - &omap2430_l4_core__mcbsp5, -}; - static struct omap_hwmod omap2430_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap2430_mcbsp_hwmod_class, @@ -1887,12 +432,9 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, }, }, - .slaves = omap2430_mcbsp5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), }; /* MMC/SD/SDIO common */ - static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { .rev_offs = 0x1fc, .sysc_offs = 0x10, @@ -1910,7 +452,6 @@ static struct omap_hwmod_class omap2430_mmc_class = { }; /* MMC/SD/SDIO1 */ - static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { { .irq = 83 }, { .irq = -1 } @@ -1926,10 +467,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb1_fck" }, }; -static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { - &omap2430_l4_core__mmc1, -}; - static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -1952,13 +489,10 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { }, }, .dev_attr = &mmc1_dev_attr, - .slaves = omap2430_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), .class = &omap2430_mmc_class, }; /* MMC/SD/SDIO2 */ - static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { { .irq = 86 }, { .irq = -1 } @@ -1974,10 +508,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb2_fck" }, }; -static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { - &omap2430_l4_core__mmc2, -}; - static struct omap_hwmod omap2430_mmc2_hwmod = { .name = "mmc2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -1995,78 +525,371 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, }, }, - .slaves = omap2430_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), .class = &omap2430_mmc_class, }; -static __initdata struct omap_hwmod *omap2430_hwmods[] = { - &omap2430_l3_main_hwmod, - &omap2430_l4_core_hwmod, - &omap2430_l4_wkup_hwmod, - &omap2430_mpu_hwmod, - &omap2430_iva_hwmod, - - &omap2430_timer1_hwmod, - &omap2430_timer2_hwmod, - &omap2430_timer3_hwmod, - &omap2430_timer4_hwmod, - &omap2430_timer5_hwmod, - &omap2430_timer6_hwmod, - &omap2430_timer7_hwmod, - &omap2430_timer8_hwmod, - &omap2430_timer9_hwmod, - &omap2430_timer10_hwmod, - &omap2430_timer11_hwmod, - &omap2430_timer12_hwmod, - - &omap2430_wd_timer2_hwmod, - &omap2430_uart1_hwmod, - &omap2430_uart2_hwmod, - &omap2430_uart3_hwmod, - /* dss class */ - &omap2430_dss_core_hwmod, - &omap2430_dss_dispc_hwmod, - &omap2430_dss_rfbi_hwmod, - &omap2430_dss_venc_hwmod, - /* i2c class */ - &omap2430_i2c1_hwmod, - &omap2430_i2c2_hwmod, - &omap2430_mmc1_hwmod, - &omap2430_mmc2_hwmod, - - /* gpio class */ - &omap2430_gpio1_hwmod, - &omap2430_gpio2_hwmod, - &omap2430_gpio3_hwmod, - &omap2430_gpio4_hwmod, - &omap2430_gpio5_hwmod, - - /* dma_system class*/ - &omap2430_dma_system_hwmod, - - /* mcbsp class */ - &omap2430_mcbsp1_hwmod, - &omap2430_mcbsp2_hwmod, - &omap2430_mcbsp3_hwmod, - &omap2430_mcbsp4_hwmod, - &omap2430_mcbsp5_hwmod, - - /* mailbox class */ - &omap2430_mailbox_hwmod, - - /* mcspi class */ - &omap2430_mcspi1_hwmod, - &omap2430_mcspi2_hwmod, - &omap2430_mcspi3_hwmod, - - /* usbotg class*/ - &omap2430_usbhsotg_hwmod, +/* + * interfaces + */ + +/* L3 -> L4_CORE interface */ +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { + .master = &omap2430_usbhsotg_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { + { + .pa_start = OMAP243X_HS_BASE, + .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core ->usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_usbhsotg_hwmod, + .clk = "usb_l4_ick", + .addr = omap2430_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcspi3_hwmod, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap2430_l3__iva = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2430_iva_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { + { + .pa_start = 0x49018000, + .pa_end = 0x49018000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2430_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { + { + .pa_start = 0x49016000, + .pa_end = 0x4901607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2430_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { + { + .pa_start = 0x4900C000, + .pa_end = 0x4900C1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { + { + .pa_start = 0x4900E000, + .pa_end = 0x4900E1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { + { + .pa_start = 0x49010000, + .pa_end = 0x490101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { + { + .pa_start = 0x49012000, + .pa_end = 0x490121ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> gpio5 */ +static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { + { + .pa_start = 0x480B6000, + .pa_end = 0x480B61ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap2430_gpio5_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mailbox_hwmod, + .addr = omap2_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap2xxx_mcbsp2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808C000, + .pa_end = 0x4808C0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap2430_mcbsp3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808E000, + .pa_end = 0x4808E0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap2430_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap2430_mcbsp5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { + &omap2xxx_l3_main__l4_core, + &omap2xxx_mpu__l3_main, + &omap2xxx_dss__l3, + &omap2430_usbhsotg__l3, + &omap2430_l4_core__i2c1, + &omap2430_l4_core__i2c2, + &omap2xxx_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, + &omap2430_l4_core__usbhsotg, + &omap2430_l4_core__mmc1, + &omap2430_l4_core__mmc2, + &omap2xxx_l4_core__mcspi1, + &omap2xxx_l4_core__mcspi2, + &omap2430_l4_core__mcspi3, + &omap2430_l3__iva, + &omap2430_l4_wkup__timer1, + &omap2xxx_l4_core__timer2, + &omap2xxx_l4_core__timer3, + &omap2xxx_l4_core__timer4, + &omap2xxx_l4_core__timer5, + &omap2xxx_l4_core__timer6, + &omap2xxx_l4_core__timer7, + &omap2xxx_l4_core__timer8, + &omap2xxx_l4_core__timer9, + &omap2xxx_l4_core__timer10, + &omap2xxx_l4_core__timer11, + &omap2xxx_l4_core__timer12, + &omap2430_l4_wkup__wd_timer2, + &omap2xxx_l4_core__dss, + &omap2xxx_l4_core__dss_dispc, + &omap2xxx_l4_core__dss_rfbi, + &omap2xxx_l4_core__dss_venc, + &omap2430_l4_wkup__gpio1, + &omap2430_l4_wkup__gpio2, + &omap2430_l4_wkup__gpio3, + &omap2430_l4_wkup__gpio4, + &omap2430_l4_core__gpio5, + &omap2430_dma_system__l3, + &omap2430_l4_core__dma_system, + &omap2430_l4_core__mailbox, + &omap2430_l4_core__mcbsp1, + &omap2430_l4_core__mcbsp2, + &omap2430_l4_core__mcbsp3, + &omap2430_l4_core__mcbsp4, + &omap2430_l4_core__mcbsp5, NULL, }; int __init omap2430_hwmod_init(void) { - return omap_hwmod_register(omap2430_hwmods); + return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 4f3547c2a49e..5178e40e84f9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -15,10 +15,12 @@ #include <plat/omap_hwmod.h> #include <plat/serial.h> +#include <plat/l3_2xxx.h> +#include <plat/l4_2xxx.h> #include "omap_hwmod_common_data.h" -struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { +static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { { .pa_start = OMAP2_UART1_BASE, .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, @@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { +static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { { .pa_start = OMAP2_UART2_BASE, .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, @@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { +static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { { .pa_start = OMAP2_UART3_BASE, .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, @@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { { .pa_start = 0x4802a000, .pa_end = 0x4802a000 + SZ_1K - 1, @@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { { .pa_start = 0x48078000, .pa_end = 0x48078000 + SZ_1K - 1, @@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { { .pa_start = 0x4807a000, .pa_end = 0x4807a000 + SZ_1K - 1, @@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { { .pa_start = 0x4807c000, .pa_end = 0x4807c000 + SZ_1K - 1, @@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { { .pa_start = 0x4807e000, .pa_end = 0x4807e000 + SZ_1K - 1, @@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { { .pa_start = 0x48080000, .pa_end = 0x48080000 + SZ_1K - 1, @@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { { .pa_start = 0x48082000, .pa_end = 0x48082000 + SZ_1K - 1, @@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { { .pa_start = 0x48084000, .pa_end = 0x48084000 + SZ_1K - 1, @@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { { } }; +/* + * Common interconnect data + */ + +/* L3 -> L4_CORE interface */ +struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2xxx_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = { + .master = &omap2xxx_mpu_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .user = OCP_USER_MPU, +}; + +/* DSS -> l3 */ +struct omap_hwmod_ocp_if omap2xxx_dss__l3 = { + .master = &omap2xxx_dss_core_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4_CORE -> L4_WKUP interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART1 interface */ +struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi1 interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer2 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer3 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer4 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer5 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer6 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer7 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer8 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer9 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer10 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer11 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer12 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2xxx_timer12_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_dispc */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_rfbi */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_venc */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 2a6729741b06..45aaa07e3025 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -10,6 +10,7 @@ */ #include <plat/omap_hwmod.h> #include <plat/serial.h> +#include <plat/gpio.h> #include <plat/dma.h> #include <plat/dmtimer.h> #include <plat/mcspi.h> @@ -17,6 +18,8 @@ #include <mach/irqs.h> #include "omap_hwmod_common_data.h" +#include "cm-regbits-24xx.h" +#include "prm-regbits-24xx.h" #include "wd_timer.h" struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { @@ -170,3 +173,562 @@ struct omap_hwmod_class omap2xxx_mcspi_class = { .sysc = &omap2xxx_mcspi_sysc, .rev = OMAP2_MCSPI_REV, }; + +/* + * IP blocks + */ + +/* L3 */ +struct omap_hwmod omap2xxx_l3_main_hwmod = { + .name = "l3_main", + .class = &l3_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* L4 CORE */ +struct omap_hwmod omap2xxx_l4_core_hwmod = { + .name = "l4_core", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* L4 WKUP */ +struct omap_hwmod omap2xxx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* MPU */ +struct omap_hwmod omap2xxx_mpu_hwmod = { + .name = "mpu", + .class = &mpu_hwmod_class, + .main_clk = "mpu_ck", +}; + +/* IVA2 */ +struct omap_hwmod omap2xxx_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, +}; + +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, +}; + +/* timer1 */ + +struct omap_hwmod omap2xxx_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2_timer1_mpu_irqs, + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer2 */ + +struct omap_hwmod omap2xxx_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2_timer2_mpu_irqs, + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer3 */ + +struct omap_hwmod omap2xxx_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2_timer3_mpu_irqs, + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer4 */ + +struct omap_hwmod omap2xxx_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2_timer4_mpu_irqs, + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer5 */ + +struct omap_hwmod omap2xxx_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2_timer5_mpu_irqs, + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer6 */ + +struct omap_hwmod omap2xxx_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2_timer6_mpu_irqs, + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer7 */ + +struct omap_hwmod omap2xxx_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2_timer7_mpu_irqs, + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer8 */ + +struct omap_hwmod omap2xxx_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2_timer8_mpu_irqs, + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer9 */ + +struct omap_hwmod omap2xxx_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2_timer9_mpu_irqs, + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer10 */ + +struct omap_hwmod omap2xxx_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2_timer10_mpu_irqs, + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer11 */ + +struct omap_hwmod omap2xxx_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2_timer11_mpu_irqs, + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer12 */ + +struct omap_hwmod omap2xxx_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2xxx_timer12_mpu_irqs, + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* wd_timer2 */ +struct omap_hwmod omap2xxx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2xxx_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, +}; + +/* UART1 */ + +struct omap_hwmod omap2xxx_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = omap2_uart1_mpu_irqs, + .sdma_reqs = omap2_uart1_sdma_reqs, + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .class = &omap2_uart_class, +}; + +/* UART2 */ + +struct omap_hwmod omap2xxx_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = omap2_uart2_mpu_irqs, + .sdma_reqs = omap2_uart2_sdma_reqs, + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .class = &omap2_uart_class, +}; + +/* UART3 */ + +struct omap_hwmod omap2xxx_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = omap2_uart3_mpu_irqs, + .sdma_reqs = omap2_uart3_sdma_reqs, + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .class = &omap2_uart_class, +}; + +/* dss */ + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, +}; + +struct omap_hwmod omap2xxx_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .sdma_reqs = omap2xxx_dss_sdma_chs, + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, +}; + +struct omap_hwmod omap2xxx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2_dispc_hwmod_class, + .mpu_irqs = omap2_dispc_irqs, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .flags = HWMOD_NO_IDLEST, + .dev_attr = &omap2_3_dss_dispc_dev_attr +}; + +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "dss_ick" }, +}; + +struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), + .flags = HWMOD_NO_IDLEST, +}; + +struct omap_hwmod omap2xxx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2_venc_hwmod_class, + .main_clk = "dss_54m_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .flags = HWMOD_NO_IDLEST, +}; + +/* gpio dev_attr */ +struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, +}; + +/* gpio1 */ +struct omap_hwmod omap2xxx_gpio1_hwmod = { + .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio1_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* gpio2 */ +struct omap_hwmod omap2xxx_gpio2_hwmod = { + .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio2_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* gpio3 */ +struct omap_hwmod omap2xxx_gpio3_hwmod = { + .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio3_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* gpio4 */ +struct omap_hwmod omap2xxx_gpio4_hwmod = { + .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio4_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* mcspi1 */ +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +struct omap_hwmod omap2xxx_mcspi1_hwmod = { + .name = "mcspi1", + .mpu_irqs = omap2_mcspi1_mpu_irqs, + .sdma_reqs = omap2_mcspi1_sdma_reqs, + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, +}; + +/* mcspi2 */ +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +struct omap_hwmod omap2xxx_mcspi2_hwmod = { + .name = "mcspi2", + .mpu_irqs = omap2_mcspi2_mpu_irqs, + .sdma_reqs = omap2_mcspi2_sdma_reqs, + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index db86ce90c69f..0c65079c2b69 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2,6 +2,7 @@ * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips * * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -38,491 +39,56 @@ /* * OMAP3xxx hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap3xxx_mpu_hwmod; -static struct omap_hwmod omap3xxx_iva_hwmod; -static struct omap_hwmod omap3xxx_l3_main_hwmod; -static struct omap_hwmod omap3xxx_l4_core_hwmod; -static struct omap_hwmod omap3xxx_l4_per_hwmod; -static struct omap_hwmod omap3xxx_wd_timer2_hwmod; -static struct omap_hwmod omap3430es1_dss_core_hwmod; -static struct omap_hwmod omap3xxx_dss_core_hwmod; -static struct omap_hwmod omap3xxx_dss_dispc_hwmod; -static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; -static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; -static struct omap_hwmod omap3xxx_dss_venc_hwmod; -static struct omap_hwmod omap3xxx_i2c1_hwmod; -static struct omap_hwmod omap3xxx_i2c2_hwmod; -static struct omap_hwmod omap3xxx_i2c3_hwmod; -static struct omap_hwmod omap3xxx_gpio1_hwmod; -static struct omap_hwmod omap3xxx_gpio2_hwmod; -static struct omap_hwmod omap3xxx_gpio3_hwmod; -static struct omap_hwmod omap3xxx_gpio4_hwmod; -static struct omap_hwmod omap3xxx_gpio5_hwmod; -static struct omap_hwmod omap3xxx_gpio6_hwmod; -static struct omap_hwmod omap34xx_sr1_hwmod; -static struct omap_hwmod omap34xx_sr2_hwmod; -static struct omap_hwmod omap34xx_mcspi1; -static struct omap_hwmod omap34xx_mcspi2; -static struct omap_hwmod omap34xx_mcspi3; -static struct omap_hwmod omap34xx_mcspi4; -static struct omap_hwmod omap3xxx_mmc1_hwmod; -static struct omap_hwmod omap3xxx_mmc2_hwmod; -static struct omap_hwmod omap3xxx_mmc3_hwmod; -static struct omap_hwmod am35xx_usbhsotg_hwmod; - -static struct omap_hwmod omap3xxx_dma_system_hwmod; - -static struct omap_hwmod omap3xxx_mcbsp1_hwmod; -static struct omap_hwmod omap3xxx_mcbsp2_hwmod; -static struct omap_hwmod omap3xxx_mcbsp3_hwmod; -static struct omap_hwmod omap3xxx_mcbsp4_hwmod; -static struct omap_hwmod omap3xxx_mcbsp5_hwmod; -static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; -static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; -static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; -static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L3 -> L4_PER interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_per_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* + * IP blocks + */ -/* L3 taret configuration and error log registers */ +/* L3 */ static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { { .irq = INT_34XX_L3_DBG_IRQ }, { .irq = INT_34XX_L3_APP_IRQ }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { - { - .pa_start = 0x68000000, - .pa_end = 0x6800ffff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { - .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .addr = omap3xxx_l3_main_addrs, - .user = OCP_USER_MPU, -}; - -/* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { - &omap3xxx_mpu__l3_main, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { - .master = &omap3xxx_dss_core_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { - &omap3xxx_l3_main__l4_core, - &omap3xxx_l3_main__l4_per, -}; - -/* L3 */ static struct omap_hwmod omap3xxx_l3_main_hwmod = { .name = "l3_main", .class = &l3_hwmod_class, .mpu_irqs = omap3xxx_l3_main_irqs, - .masters = omap3xxx_l3_main_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), - .slaves = omap3xxx_l3_main_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod omap3xxx_l4_wkup_hwmod; -static struct omap_hwmod omap3xxx_uart1_hwmod; -static struct omap_hwmod omap3xxx_uart2_hwmod; -static struct omap_hwmod omap3xxx_uart3_hwmod; -static struct omap_hwmod omap3xxx_uart4_hwmod; -static struct omap_hwmod am35xx_uart4_hwmod; -static struct omap_hwmod omap3xxx_usbhsotg_hwmod; - -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { - .master = &omap3xxx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; - -/* l3_core -> am35xx_usbhsotg interface */ -static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { - .master = &am35xx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 -}; - -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 -}; - -/* L4 CORE -> MMC3 interface */ -static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad1ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc3_hwmod, - .clk = "mmchs3_ick", - .addr = omap3xxx_mmc3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { - { - .pa_start = OMAP3_UART1_BASE, - .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap3xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { - { - .pa_start = OMAP3_UART2_BASE, - .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap3xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { - { - .pa_start = OMAP3_UART3_BASE, - .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap3xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART4 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_BASE, - .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart4_hwmod, - .clk = "uart4_ick", - .addr = omap3xxx_uart4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* AM35xx: L4 CORE -> UART4 interface */ -static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_AM35XX_BASE, - .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_uart4_hwmod, - .clk = "uart4_ick", - .addr = am35xx_uart4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C3 interface */ -static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x48060000 + SZ_128 - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c3_hwmod, - .clk = "i2c3_ick", - .addr = omap3xxx_i2c3_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { - { .irq = 18}, - { .irq = -1 } -}; - -static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { - { .irq = 19}, - { .irq = -1 } -}; - -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { - { - .pa_start = OMAP34XX_SR1_BASE, - .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr1_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr1_addr_space, - .user = OCP_USER_MPU, -}; - -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { - { - .pa_start = OMAP34XX_SR2_BASE, - .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr2_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr2_addr_space, - .user = OCP_USER_MPU, -}; - -/* -* usbhsotg interface data -*/ - -static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { - { - .pa_start = OMAP34XX_HSUSB_OTG_BASE, - .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = omap3xxx_usbhsotg_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { - &omap3xxx_usbhsotg__l3, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { - &omap3xxx_l4_core__usbhsotg, -}; - -static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { - { - .pa_start = AM35XX_IPSS_USBOTGSS_BASE, - .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = am35xx_usbhsotg_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { - &am35xx_usbhsotg__l3, -}; - -static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { - &am35xx_l4_core__usbhsotg, -}; -/* Slave interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { - &omap3xxx_l3_main__l4_core, -}; - /* L4 CORE */ static struct omap_hwmod omap3xxx_l4_core_hwmod = { .name = "l4_core", .class = &l4_hwmod_class, - .slaves = omap3xxx_l4_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), .flags = HWMOD_NO_IDLEST, }; -/* Slave interfaces on the L4_PER interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { - &omap3xxx_l3_main__l4_per, -}; - /* L4 PER */ static struct omap_hwmod omap3xxx_l4_per_hwmod = { .name = "l4_per", .class = &l4_hwmod_class, - .slaves = omap3xxx_l4_per_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), .flags = HWMOD_NO_IDLEST, }; -/* Slave interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { - &omap3xxx_l4_core__l4_wkup, -}; - /* L4 WKUP */ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { .name = "l4_wkup", .class = &l4_hwmod_class, - .slaves = omap3xxx_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), .flags = HWMOD_NO_IDLEST, }; -/* Master interfaces on the MPU device */ -static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { - &omap3xxx_mpu__l3_main, +/* L4 SEC */ +static struct omap_hwmod omap3xxx_l4_sec_hwmod = { + .name = "l4_sec", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, }; /* MPU */ @@ -530,35 +96,22 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { .name = "mpu", .class = &mpu_hwmod_class, .main_clk = "arm_fck", - .masters = omap3xxx_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), }; -/* - * IVA2_2 interface data - */ - -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_iva_hwmod, - .clk = "iva2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* IVA2 (IVA2) */ +static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "seq0", .rst_shift = 1 }, + { .name = "seq1", .rst_shift = 2 }, }; -static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { - &omap3xxx_l3__iva, -}; - -/* - * IVA2 (IVA2) - */ - static struct omap_hwmod omap3xxx_iva_hwmod = { .name = "iva", .class = &iva_hwmod_class, - .masters = omap3xxx_iva_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), + .clkdm_name = "iva2_clkdm", + .rst_lines = omap3xxx_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), + .main_clk = "iva2_ck", }; /* timer class */ @@ -597,46 +150,20 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { /* secure timers dev attribute */ static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { - .timer_capability = OMAP_TIMER_SECURE, + .timer_capability = OMAP_TIMER_SECURE, }; /* always-on timers dev attribute */ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, + .timer_capability = OMAP_TIMER_ALWON, }; /* pwm timers dev attribute */ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, + .timer_capability = OMAP_TIMER_HAS_PWM, }; /* timer1 */ -static struct omap_hwmod omap3xxx_timer1_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { - { - .pa_start = 0x48318000, - .pa_end = 0x48318000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap3xxx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { - &omap3xxx_l4_wkup__timer1, -}; - -/* timer1 hwmod */ static struct omap_hwmod omap3xxx_timer1_hwmod = { .name = "timer1", .mpu_irqs = omap2_timer1_mpu_irqs, @@ -651,38 +178,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, }; /* timer2 */ -static struct omap_hwmod omap3xxx_timer2_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x49032000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap3xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { - &omap3xxx_l4_per__timer2, -}; - -/* timer2 hwmod */ static struct omap_hwmod omap3xxx_timer2_hwmod = { .name = "timer2", .mpu_irqs = omap2_timer2_mpu_irqs, @@ -697,38 +196,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, }; /* timer3 */ -static struct omap_hwmod omap3xxx_timer3_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { - { - .pa_start = 0x49034000, - .pa_end = 0x49034000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap3xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { - &omap3xxx_l4_per__timer3, -}; - -/* timer3 hwmod */ static struct omap_hwmod omap3xxx_timer3_hwmod = { .name = "timer3", .mpu_irqs = omap2_timer3_mpu_irqs, @@ -743,38 +214,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer4 */ -static struct omap_hwmod omap3xxx_timer4_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { - { - .pa_start = 0x49036000, - .pa_end = 0x49036000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap3xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { - &omap3xxx_l4_per__timer4, -}; - -/* timer4 hwmod */ static struct omap_hwmod omap3xxx_timer4_hwmod = { .name = "timer4", .mpu_irqs = omap2_timer4_mpu_irqs, @@ -789,38 +232,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer5 */ -static struct omap_hwmod omap3xxx_timer5_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x49038000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap3xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { - &omap3xxx_l4_per__timer5, -}; - -/* timer5 hwmod */ static struct omap_hwmod omap3xxx_timer5_hwmod = { .name = "timer5", .mpu_irqs = omap2_timer5_mpu_irqs, @@ -835,38 +250,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer6 */ -static struct omap_hwmod omap3xxx_timer6_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { - { - .pa_start = 0x4903A000, - .pa_end = 0x4903A000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer6 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap3xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { - &omap3xxx_l4_per__timer6, -}; - -/* timer6 hwmod */ static struct omap_hwmod omap3xxx_timer6_hwmod = { .name = "timer6", .mpu_irqs = omap2_timer6_mpu_irqs, @@ -881,38 +268,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer7 */ -static struct omap_hwmod omap3xxx_timer7_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { - { - .pa_start = 0x4903C000, - .pa_end = 0x4903C000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer7 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap3xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer7 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { - &omap3xxx_l4_per__timer7, -}; - -/* timer7 hwmod */ static struct omap_hwmod omap3xxx_timer7_hwmod = { .name = "timer7", .mpu_irqs = omap2_timer7_mpu_irqs, @@ -927,38 +286,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer8 */ -static struct omap_hwmod omap3xxx_timer8_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { - { - .pa_start = 0x4903E000, - .pa_end = 0x4903E000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer8 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap3xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer8 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { - &omap3xxx_l4_per__timer8, -}; - -/* timer8 hwmod */ static struct omap_hwmod omap3xxx_timer8_hwmod = { .name = "timer8", .mpu_irqs = omap2_timer8_mpu_irqs, @@ -973,38 +304,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer9 */ -static struct omap_hwmod omap3xxx_timer9_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { - { - .pa_start = 0x49040000, - .pa_end = 0x49040000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap3xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { - &omap3xxx_l4_per__timer9, -}; - -/* timer9 hwmod */ static struct omap_hwmod omap3xxx_timer9_hwmod = { .name = "timer9", .mpu_irqs = omap2_timer9_mpu_irqs, @@ -1019,29 +322,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer10 */ -static struct omap_hwmod omap3xxx_timer10_hwmod; - -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { - &omap3xxx_l4_core__timer10, -}; - -/* timer10 hwmod */ static struct omap_hwmod omap3xxx_timer10_hwmod = { .name = "timer10", .mpu_irqs = omap2_timer10_mpu_irqs, @@ -1056,29 +340,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, }; /* timer11 */ -static struct omap_hwmod omap3xxx_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { - &omap3xxx_l4_core__timer11, -}; - -/* timer11 hwmod */ static struct omap_hwmod omap3xxx_timer11_hwmod = { .name = "timer11", .mpu_irqs = omap2_timer11_mpu_irqs, @@ -1093,42 +358,15 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), .class = &omap3xxx_timer_hwmod_class, }; -/* timer12*/ -static struct omap_hwmod omap3xxx_timer12_hwmod; +/* timer12 */ static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { { .irq = 95, }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { - { - .pa_start = 0x48304000, - .pa_end = 0x48304000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap3xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer12 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { - &omap3xxx_l4_core__timer12, -}; - -/* timer12 hwmod */ static struct omap_hwmod omap3xxx_timer12_hwmod = { .name = "timer12", .mpu_irqs = omap3xxx_timer12_mpu_irqs, @@ -1143,29 +381,9 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = { }, }, .dev_attr = &capability_secure_dev_attr, - .slaves = omap3xxx_timer12_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), .class = &omap3xxx_timer_hwmod_class, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { - { - .pa_start = 0x48314000, - .pa_end = 0x4831407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_wd_timer2_hwmod, - .clk = "wdt2_ick", - .addr = omap3xxx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* * 'wd_timer' class * 32-bit watchdog upward counter that generates a pulse on the reset pin on @@ -1203,11 +421,6 @@ static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { .pre_shutdown = &omap2_wd_timer_disable }; -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { - &omap3xxx_l4_wkup__wd_timer2, -}; - static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap3xxx_wd_timer_hwmod_class, @@ -1221,8 +434,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, }, }, - .slaves = omap3xxx_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), /* * XXX: Use software supervised mode, HW supervised smartidle seems to * block CORE power domain idle transitions. Maybe a HW bug in wdt2? @@ -1231,11 +442,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { }; /* UART1 */ - -static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { - &omap3_l4_core__uart1, -}; - static struct omap_hwmod omap3xxx_uart1_hwmod = { .name = "uart1", .mpu_irqs = omap2_uart1_mpu_irqs, @@ -1250,17 +456,10 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, }, }, - .slaves = omap3xxx_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), .class = &omap2_uart_class, }; /* UART2 */ - -static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { - &omap3_l4_core__uart2, -}; - static struct omap_hwmod omap3xxx_uart2_hwmod = { .name = "uart2", .mpu_irqs = omap2_uart2_mpu_irqs, @@ -1275,17 +474,10 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, }, }, - .slaves = omap3xxx_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), .class = &omap2_uart_class, }; /* UART3 */ - -static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { - &omap3_l4_per__uart3, -}; - static struct omap_hwmod omap3xxx_uart3_hwmod = { .name = "uart3", .mpu_irqs = omap2_uart3_mpu_irqs, @@ -1300,13 +492,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, }, }, - .slaves = omap3xxx_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), .class = &omap2_uart_class, }; /* UART4 */ - static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { { .irq = INT_36XX_UART4_IRQ, }, { .irq = -1 } @@ -1318,11 +507,7 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { - &omap3_l4_per__uart4, -}; - -static struct omap_hwmod omap3xxx_uart4_hwmod = { +static struct omap_hwmod omap36xx_uart4_hwmod = { .name = "uart4", .mpu_irqs = uart4_mpu_irqs, .sdma_reqs = uart4_sdma_reqs, @@ -1336,8 +521,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, }, }, - .slaves = omap3xxx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), .class = &omap2_uart_class, }; @@ -1350,16 +533,12 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, }; -static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = { - &am35xx_l4_core__uart4, -}; - static struct omap_hwmod am35xx_uart4_hwmod = { - .name = "uart4", - .mpu_irqs = am35xx_uart4_mpu_irqs, - .sdma_reqs = am35xx_uart4_sdma_reqs, - .main_clk = "uart4_fck", - .prcm = { + .name = "uart4", + .mpu_irqs = am35xx_uart4_mpu_irqs, + .sdma_reqs = am35xx_uart4_sdma_reqs, + .main_clk = "uart4_fck", + .prcm = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, @@ -1368,12 +547,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, }, }, - .slaves = am35xx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves), - .class = &omap2_uart_class, + .class = &omap2_uart_class, }; - static struct omap_hwmod_class i2c_class = { .name = "i2c", .sysc = &i2c_sysc, @@ -1388,51 +564,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { }; /* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { - &omap3xxx_dss__l3, -}; - -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3430es1_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { - &omap3430es1_l4_core__dss, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { - &omap3xxx_l4_core__dss, -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { /* * The DSS HW needs all DSS clocks enabled during reset. The dss_core @@ -1460,10 +591,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { }, .opt_clks = dss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap3430es1_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), - .masters = omap3xxx_dss_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, }; @@ -1485,10 +612,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { }, .opt_clks = dss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap3xxx_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), - .masters = omap3xxx_dss_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), }; /* @@ -1513,27 +636,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = { .sysc = &omap3_dispc_sysc, }; -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { - &omap3xxx_l4_core__dss_dispc, -}; - static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap3_dispc_hwmod_class, @@ -1546,8 +648,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .module_offs = OMAP3430_DSS_MOD, }, }, - .slaves = omap3xxx_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), .flags = HWMOD_NO_IDLEST, .dev_attr = &omap2_3_dss_dispc_dev_attr }; @@ -1567,36 +667,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { }; /* dss_dsi1 */ -static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { - { - .pa_start = 0x4804FC00, - .pa_end = 0x4804FFFF, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dsi1_hwmod, - .clk = "dss_ick", - .addr = omap3xxx_dss_dsi1_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dsi1 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { - &omap3xxx_l4_core__dss_dsi1, -}; - static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { { .role = "sys_clk", .clk = "dss2_alwon_fck" }, }; @@ -1615,32 +685,9 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { }, .opt_clks = dss_dsi1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), - .slaves = omap3xxx_dss_dsi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), .flags = HWMOD_NO_IDLEST, }; -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { - &omap3xxx_l4_core__dss_rfbi, -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_ick" }, }; @@ -1658,32 +705,9 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { }, .opt_clks = dss_rfbi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap3xxx_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), .flags = HWMOD_NO_IDLEST, }; -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { - &omap3xxx_l4_core__dss_venc, -}; - static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { /* required only on OMAP3430 */ { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, @@ -1702,13 +726,10 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = { }, .opt_clks = dss_venc_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), - .slaves = omap3xxx_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), .flags = HWMOD_NO_IDLEST, }; /* I2C1 */ - static struct omap_i2c_dev_attr i2c1_dev_attr = { .fifo_depth = 8, /* bytes */ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | @@ -1716,10 +737,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = { OMAP_I2C_FLAG_BUS_SHIFT_2, }; -static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { - &omap3_l4_core__i2c1, -}; - static struct omap_hwmod omap3xxx_i2c1_hwmod = { .name = "i2c1", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, @@ -1735,14 +752,11 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = { .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, }, }, - .slaves = omap3xxx_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), .class = &i2c_class, .dev_attr = &i2c1_dev_attr, }; /* I2C2 */ - static struct omap_i2c_dev_attr i2c2_dev_attr = { .fifo_depth = 8, /* bytes */ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | @@ -1750,10 +764,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = { OMAP_I2C_FLAG_BUS_SHIFT_2, }; -static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { - &omap3_l4_core__i2c2, -}; - static struct omap_hwmod omap3xxx_i2c2_hwmod = { .name = "i2c2", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, @@ -1769,14 +779,11 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = { .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, }, }, - .slaves = omap3xxx_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), .class = &i2c_class, .dev_attr = &i2c2_dev_attr, }; /* I2C3 */ - static struct omap_i2c_dev_attr i2c3_dev_attr = { .fifo_depth = 64, /* bytes */ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | @@ -1795,10 +802,6 @@ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { - &omap3_l4_core__i2c3, -}; - static struct omap_hwmod omap3xxx_i2c3_hwmod = { .name = "i2c3", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, @@ -1814,114 +817,10 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = { .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, }, }, - .slaves = omap3xxx_i2c3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), .class = &i2c_class, .dev_attr = &i2c3_dev_attr, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { - { - .pa_start = 0x48310000, - .pa_end = 0x483101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_gpio1_hwmod, - .addr = omap3xxx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio2 */ -static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { - { - .pa_start = 0x49050000, - .pa_end = 0x490501ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio2_hwmod, - .addr = omap3xxx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio3 */ -static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { - { - .pa_start = 0x49052000, - .pa_end = 0x490521ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio3_hwmod, - .addr = omap3xxx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio4 */ -static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { - { - .pa_start = 0x49054000, - .pa_end = 0x490541ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio4_hwmod, - .addr = omap3xxx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio5 */ -static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { - { - .pa_start = 0x49056000, - .pa_end = 0x490561ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio5_hwmod, - .addr = omap3xxx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio6 */ -static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { - { - .pa_start = 0x49058000, - .pa_end = 0x490581ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio6_hwmod, - .addr = omap3xxx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* * 'gpio' class * general purpose io module @@ -1944,7 +843,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { .rev = 1, }; -/* gpio_dev_attr*/ +/* gpio_dev_attr */ static struct omap_gpio_dev_attr gpio_dev_attr = { .bank_width = 32, .dbck_flag = true, @@ -1955,10 +854,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { - &omap3xxx_l4_wkup__gpio1, -}; - static struct omap_hwmod omap3xxx_gpio1_hwmod = { .name = "gpio1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -1975,8 +870,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, }, }, - .slaves = omap3xxx_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -1986,10 +879,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { - &omap3xxx_l4_per__gpio2, -}; - static struct omap_hwmod omap3xxx_gpio2_hwmod = { .name = "gpio2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2006,8 +895,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, }, }, - .slaves = omap3xxx_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2017,10 +904,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { - &omap3xxx_l4_per__gpio3, -}; - static struct omap_hwmod omap3xxx_gpio3_hwmod = { .name = "gpio3", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2037,8 +920,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, }, }, - .slaves = omap3xxx_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2048,10 +929,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { { .role = "dbclk", .clk = "gpio4_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { - &omap3xxx_l4_per__gpio4, -}; - static struct omap_hwmod omap3xxx_gpio4_hwmod = { .name = "gpio4", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2068,8 +945,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, }, }, - .slaves = omap3xxx_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2084,10 +959,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { { .role = "dbclk", .clk = "gpio5_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { - &omap3xxx_l4_per__gpio5, -}; - static struct omap_hwmod omap3xxx_gpio5_hwmod = { .name = "gpio5", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2104,8 +975,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, }, }, - .slaves = omap3xxx_gpio5_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2120,10 +989,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { { .role = "dbclk", .clk = "gpio6_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { - &omap3xxx_l4_per__gpio6, -}; - static struct omap_hwmod omap3xxx_gpio6_hwmod = { .name = "gpio6", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2140,20 +1005,10 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, }, }, - .slaves = omap3xxx_gpio6_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { - .master = &omap3xxx_dma_system_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* dma attributes */ static struct omap_dma_dev_attr dma_dev_attr = { .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | @@ -2180,34 +1035,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { }; /* dma_system */ -static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { - { - .pa_start = 0x48056000, - .pa_end = 0x48056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { - &omap3xxx_dma_system__l3, -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dma_system_hwmod, - .clk = "core_l4_ick", - .addr = omap3xxx_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { - &omap3xxx_l4_core__dma_system, -}; - static struct omap_hwmod omap3xxx_dma_system_hwmod = { .name = "dma", .class = &omap3xxx_dma_hwmod_class, @@ -2222,10 +1049,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, }, }, - .slaves = omap3xxx_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), - .masters = omap3xxx_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, }; @@ -2258,30 +1081,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48074000, - .pa_end = 0x480740ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap3xxx_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { - &omap3xxx_l4_core__mcbsp1, -}; - static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap3xxx_mcbsp_hwmod_class, @@ -2297,8 +1096,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, }, }, - .slaves = omap3xxx_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), }; /* mcbsp2 */ @@ -2309,30 +1106,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { - &omap3xxx_l4_per__mcbsp2, -}; - static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { .sidetone = "mcbsp2_sidetone", }; @@ -2352,8 +1125,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, }, }, - .slaves = omap3xxx_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), .dev_attr = &omap34xx_mcbsp2_dev_attr, }; @@ -2365,32 +1136,8 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp3 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { - &omap3xxx_l4_per__mcbsp3, -}; - static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { - .sidetone = "mcbsp3_sidetone", + .sidetone = "mcbsp3_sidetone", }; static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { @@ -2408,8 +1155,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, }, }, - .slaves = omap3xxx_mcbsp3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), .dev_attr = &omap34xx_mcbsp3_dev_attr, }; @@ -2427,30 +1172,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp4_hwmod, - .clk = "mcbsp4_ick", - .addr = omap3xxx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp4 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { - &omap3xxx_l4_per__mcbsp4, -}; - static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap3xxx_mcbsp_hwmod_class, @@ -2466,8 +1187,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, }, }, - .slaves = omap3xxx_mcbsp4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), }; /* mcbsp5 */ @@ -2484,30 +1203,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp5_hwmod, - .clk = "mcbsp5_ick", - .addr = omap3xxx_mcbsp5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp5 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { - &omap3xxx_l4_core__mcbsp5, -}; - static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap3xxx_mcbsp_hwmod_class, @@ -2523,11 +1218,9 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, }, }, - .slaves = omap3xxx_mcbsp5_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), }; -/* 'mcbsp sidetone' class */ +/* 'mcbsp sidetone' class */ static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { .sysc_offs = 0x0010, .sysc_flags = SYSC_HAS_AUTOIDLE, @@ -2545,30 +1238,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { - { - .name = "sidetone", - .pa_start = 0x49028000, - .pa_end = 0x490280ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp2_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_sidetone_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_sidetone_addrs, - .user = OCP_USER_MPU, -}; - -/* mcbsp2_sidetone slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { - &omap3xxx_l4_per__mcbsp2_sidetone, -}; - static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { .name = "mcbsp2_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, @@ -2583,8 +1252,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, }, }, - .slaves = omap3xxx_mcbsp2_sidetone_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), }; /* mcbsp3_sidetone */ @@ -2593,30 +1260,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { - { - .name = "sidetone", - .pa_start = 0x4902A000, - .pa_end = 0x4902A0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp3_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_sidetone_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_sidetone_addrs, - .user = OCP_USER_MPU, -}; - -/* mcbsp3_sidetone slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { - &omap3xxx_l4_per__mcbsp3_sidetone, -}; - static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { .name = "mcbsp3_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, @@ -2631,11 +1274,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, }, }, - .slaves = omap3xxx_mcbsp3_sidetone_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), }; - /* SR common */ static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { .clkact_shift = 20, @@ -2656,7 +1296,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { .sidle_shift = 24, - .enwkup_shift = 26 + .enwkup_shift = 26, }; static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { @@ -2678,12 +1318,13 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = { .sensor_voltdm_name = "mpu_iva", }; -static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { - &omap3_l4_core__sr1, +static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { + { .irq = 18 }, + { .irq = -1 } }; static struct omap_hwmod omap34xx_sr1_hwmod = { - .name = "sr1_hwmod", + .name = "sr1", .class = &omap34xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", .prcm = { @@ -2695,15 +1336,13 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, }, }, - .slaves = omap3_sr1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), .dev_attr = &sr1_dev_attr, .mpu_irqs = omap3_smartreflex_mpu_irqs, .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; static struct omap_hwmod omap36xx_sr1_hwmod = { - .name = "sr1_hwmod", + .name = "sr1", .class = &omap36xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", .prcm = { @@ -2715,8 +1354,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, }, }, - .slaves = omap3_sr1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), .dev_attr = &sr1_dev_attr, .mpu_irqs = omap3_smartreflex_mpu_irqs, }; @@ -2726,12 +1363,13 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = { .sensor_voltdm_name = "core", }; -static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { - &omap3_l4_core__sr2, +static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { + { .irq = 19 }, + { .irq = -1 } }; static struct omap_hwmod omap34xx_sr2_hwmod = { - .name = "sr2_hwmod", + .name = "sr2", .class = &omap34xx_smartreflex_hwmod_class, .main_clk = "sr2_fck", .prcm = { @@ -2743,15 +1381,13 @@ static struct omap_hwmod omap34xx_sr2_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .slaves = omap3_sr2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), .dev_attr = &sr2_dev_attr, .mpu_irqs = omap3_smartreflex_core_irqs, .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; static struct omap_hwmod omap36xx_sr2_hwmod = { - .name = "sr2_hwmod", + .name = "sr2", .class = &omap36xx_smartreflex_hwmod_class, .main_clk = "sr2_fck", .prcm = { @@ -2763,8 +1399,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .slaves = omap3_sr2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), .dev_attr = &sr2_dev_attr, .mpu_irqs = omap3_smartreflex_core_irqs, }; @@ -2790,34 +1424,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { .sysc = &omap3xxx_mailbox_sysc, }; -static struct omap_hwmod omap3xxx_mailbox_hwmod; static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { { .irq = 26 }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { - { - .pa_start = 0x48094000, - .pa_end = 0x480941ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mailbox_hwmod, - .addr = omap3xxx_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { - &omap3xxx_l4_core__mailbox, -}; - static struct omap_hwmod omap3xxx_mailbox_hwmod = { .name = "mailbox", .class = &omap3xxx_mailbox_hwmod_class, @@ -2832,53 +1443,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = { .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, }, }, - .slaves = omap3xxx_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), -}; - -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi1, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi2, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi3, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi4 interface */ -static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba0ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi4, - .clk = "mcspi4_ick", - .addr = omap34xx_mcspi4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* @@ -2905,10 +1469,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = { }; /* mcspi1 */ -static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { - &omap34xx_l4_core__mcspi1, -}; - static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { .num_chipselect = 4, }; @@ -2927,17 +1487,11 @@ static struct omap_hwmod omap34xx_mcspi1 = { .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, }, }, - .slaves = omap34xx_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { - &omap34xx_l4_core__mcspi2, -}; - static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { .num_chipselect = 2, }; @@ -2956,8 +1510,6 @@ static struct omap_hwmod omap34xx_mcspi2 = { .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, }, }, - .slaves = omap34xx_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi2_dev_attr, }; @@ -2976,10 +1528,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { - &omap34xx_l4_core__mcspi3, -}; - static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { .num_chipselect = 2, }; @@ -2998,13 +1546,11 @@ static struct omap_hwmod omap34xx_mcspi3 = { .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, }, }, - .slaves = omap34xx_mcspi3_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi3_dev_attr, }; -/* SPI4 */ +/* mcspi4 */ static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ { .irq = -1 } @@ -3016,10 +1562,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { - &omap34xx_l4_core__mcspi4, -}; - static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { .num_chipselect = 1, }; @@ -3038,15 +1580,11 @@ static struct omap_hwmod omap34xx_mcspi4 = { .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, }, }, - .slaves = omap34xx_mcspi4_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi4_dev_attr, }; -/* - * usbhsotg - */ +/* usbhsotg */ static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { .rev_offs = 0x0400, .sysc_offs = 0x0404, @@ -3063,6 +1601,7 @@ static struct omap_hwmod_class usbotg_class = { .name = "usbotg", .sysc = &omap3xxx_usbhsotg_sysc, }; + /* usb_otg_hs */ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { @@ -3085,10 +1624,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT }, }, - .masters = omap3xxx_usbhsotg_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), - .slaves = omap3xxx_usbhsotg_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), .class = &usbotg_class, /* @@ -3120,15 +1655,10 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = { .omap2 = { }, }, - .masters = am35xx_usbhsotg_masters, - .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), - .slaves = am35xx_usbhsotg_slaves, - .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), .class = &am35xx_usbotg_class, }; /* MMC/SD/SDIO common */ - static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { .rev_offs = 0x1fc, .sysc_offs = 0x10, @@ -3162,10 +1692,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { - &omap3xxx_l4_core__mmc1, -}; - static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -3193,8 +1719,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { }, }, .dev_attr = &mmc1_pre_es3_dev_attr, - .slaves = omap3xxx_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), .class = &omap34xx_mmc_class, }; @@ -3215,8 +1739,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { }, }, .dev_attr = &mmc1_dev_attr, - .slaves = omap3xxx_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), .class = &omap34xx_mmc_class, }; @@ -3237,10 +1759,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { - &omap3xxx_l4_core__mmc2, -}; - /* See 35xx errata 2.1.1.128 in SPRZ278F */ static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, @@ -3263,8 +1781,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { }, }, .dev_attr = &mmc2_pre_es3_dev_attr, - .slaves = omap3xxx_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), .class = &omap34xx_mmc_class, }; @@ -3284,8 +1800,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, }, }, - .slaves = omap3xxx_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), .class = &omap34xx_mmc_class, }; @@ -3306,10 +1820,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { - &omap3xxx_l4_core__mmc3, -}; - static struct omap_hwmod omap3xxx_mmc3_hwmod = { .name = "mmc3", .mpu_irqs = omap34xx_mmc3_mpu_irqs, @@ -3325,8 +1835,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, }, }, - .slaves = omap3xxx_mmc3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), .class = &omap34xx_mmc_class, }; @@ -3334,12 +1842,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { * 'usb_host_hs' class * high-speed multi-port usb host controller */ -static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { - .master = &omap3xxx_usb_host_hs_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { .rev_offs = 0x0000, @@ -3358,42 +1860,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { .sysc = &omap3xxx_usb_host_hs_sysc, }; -static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = { - &omap3xxx_usb_host_hs__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { - { - .name = "uhh", - .pa_start = 0x48064000, - .pa_end = 0x480643ff, - .flags = ADDR_TYPE_RT - }, - { - .name = "ohci", - .pa_start = 0x48064400, - .pa_end = 0x480647ff, - }, - { - .name = "ehci", - .pa_start = 0x48064800, - .pa_end = 0x48064cff, - }, - {} -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_usb_host_hs_hwmod, - .clk = "usbhost_ick", - .addr = omap3xxx_usb_host_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = { - &omap3xxx_l4_core__usb_host_hs, -}; - static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, }; @@ -3422,10 +1888,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { }, .opt_clks = omap3xxx_usb_host_hs_opt_clks, .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), - .slaves = omap3xxx_usb_host_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves), - .masters = omap3xxx_usb_host_hs_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters), /* * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock @@ -3501,6 +1963,1084 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { { .irq = -1 } }; +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap3xxx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_tll_hs_irqs, + .main_clk = "usbtll_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 3, + .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .idlest_reg_id = 3, + .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, + }, + }, +}; + +/* + * interfaces + */ + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L3 -> L4_PER interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_per_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { + { + .pa_start = 0x68000000, + .pa_end = 0x6800ffff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { + .master = &omap3xxx_mpu_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .addr = omap3xxx_l3_main_addrs, + .user = OCP_USER_MPU, +}; + +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { + .master = &omap3430es1_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { + .master = &omap3xxx_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { + .master = &omap3xxx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + +/* l3_core -> am35xx_usbhsotg interface */ +static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { + .master = &am35xx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_pre_es3_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_es3plus_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_pre_es3_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_es3plus_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> MMC3 interface */ +static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad1ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc3_hwmod, + .clk = "mmchs3_ick", + .addr = omap3xxx_mmc3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { + { + .pa_start = OMAP3_UART1_BASE, + .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap3xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { + { + .pa_start = OMAP3_UART2_BASE, + .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap3xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { + { + .pa_start = OMAP3_UART3_BASE, + .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap3xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART4 interface */ +static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_BASE, + .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap36xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = omap36xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* AM35xx: L4 CORE -> UART4 interface */ +static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_AM35XX_BASE, + .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = am35xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C3 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x48060000 + SZ_128 - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c3_hwmod, + .clk = "i2c3_ick", + .addr = omap3xxx_i2c3_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { + { + .pa_start = OMAP34XX_SR1_BASE, + .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { + { + .pa_start = OMAP34XX_SR2_BASE, + .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { + { + .pa_start = OMAP34XX_HSUSB_OTG_BASE, + .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = omap3xxx_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { + { + .pa_start = AM35XX_IPSS_USBOTGSS_BASE, + .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = am35xx_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; + +/* L4_WKUP -> L4_SEC interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_l4_sec_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_iva_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { + { + .pa_start = 0x48318000, + .pa_end = 0x48318000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap3xxx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x49032000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap3xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { + { + .pa_start = 0x49034000, + .pa_end = 0x49034000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap3xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { + { + .pa_start = 0x49036000, + .pa_end = 0x49036000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap3xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x49038000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap3xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { + { + .pa_start = 0x4903A000, + .pa_end = 0x4903A000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer6 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap3xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { + { + .pa_start = 0x4903C000, + .pa_end = 0x4903C000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer7 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap3xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { + { + .pa_start = 0x4903E000, + .pa_end = 0x4903E000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer8 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap3xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { + { + .pa_start = 0x49040000, + .pa_end = 0x49040000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap3xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { + .master = &omap3xxx_l4_sec_hwmod, + .slave = &omap3xxx_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap3xxx_timer12_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { + { + .pa_start = 0x48314000, + .pa_end = 0x4831407f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_wd_timer2_hwmod, + .clk = "wdt2_ick", + .addr = omap3xxx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3430es1_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { + { + .pa_start = 0x4804FC00, + .pa_end = 0x4804FFFF, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dsi1_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_dsi1_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = 0x48310000, + .pa_end = 0x483101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .addr = omap3xxx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = 0x49050000, + .pa_end = 0x490501ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .addr = omap3xxx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = 0x49052000, + .pa_end = 0x490521ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .addr = omap3xxx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = 0x49054000, + .pa_end = 0x490541ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .addr = omap3xxx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = 0x49056000, + .pa_end = 0x490561ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .addr = omap3xxx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = 0x49058000, + .pa_end = 0x490581ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .addr = omap3xxx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { + .master = &omap3xxx_dma_system_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x48056fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dma_system_hwmod, + .clk = "core_l4_ick", + .addr = omap3xxx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap3xxx_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap3xxx_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap3xxx_mcbsp5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x49028000, + .pa_end = 0x490280ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp2_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_sidetone_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_sidetone_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x4902A000, + .pa_end = 0x4902A0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp3_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_sidetone_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_sidetone_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { + { + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mailbox_hwmod, + .addr = omap3xxx_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi1, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi2, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi3, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi4 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba0ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi4, + .clk = "mcspi4_ick", + .addr = omap34xx_mcspi4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { + .master = &omap3xxx_usb_host_hs_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { + { + .name = "uhh", + .pa_start = 0x48064000, + .pa_end = 0x480643ff, + .flags = ADDR_TYPE_RT + }, + { + .name = "ohci", + .pa_start = 0x48064400, + .pa_end = 0x480647ff, + }, + { + .name = "ehci", + .pa_start = 0x48064800, + .pa_end = 0x48064cff, + }, + {} +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usb_host_hs_hwmod, + .clk = "usbhost_ick", + .addr = omap3xxx_usb_host_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { { .name = "tll", @@ -3519,183 +3059,156 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { - &omap3xxx_l4_core__usb_tll_hs, -}; - -static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap3xxx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap3xxx_usb_tll_hs_irqs, - .main_clk = "usbtll_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 3, - .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .idlest_reg_id = 3, - .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, - }, - }, - .slaves = omap3xxx_usb_tll_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), -}; - -static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { - &omap3xxx_l3_main_hwmod, - &omap3xxx_l4_core_hwmod, - &omap3xxx_l4_per_hwmod, - &omap3xxx_l4_wkup_hwmod, - &omap3xxx_mmc3_hwmod, - &omap3xxx_mpu_hwmod, - - &omap3xxx_timer1_hwmod, - &omap3xxx_timer2_hwmod, - &omap3xxx_timer3_hwmod, - &omap3xxx_timer4_hwmod, - &omap3xxx_timer5_hwmod, - &omap3xxx_timer6_hwmod, - &omap3xxx_timer7_hwmod, - &omap3xxx_timer8_hwmod, - &omap3xxx_timer9_hwmod, - &omap3xxx_timer10_hwmod, - &omap3xxx_timer11_hwmod, - - &omap3xxx_wd_timer2_hwmod, - &omap3xxx_uart1_hwmod, - &omap3xxx_uart2_hwmod, - &omap3xxx_uart3_hwmod, - - /* i2c class */ - &omap3xxx_i2c1_hwmod, - &omap3xxx_i2c2_hwmod, - &omap3xxx_i2c3_hwmod, - - /* gpio class */ - &omap3xxx_gpio1_hwmod, - &omap3xxx_gpio2_hwmod, - &omap3xxx_gpio3_hwmod, - &omap3xxx_gpio4_hwmod, - &omap3xxx_gpio5_hwmod, - &omap3xxx_gpio6_hwmod, - - /* dma_system class*/ - &omap3xxx_dma_system_hwmod, - - /* mcbsp class */ - &omap3xxx_mcbsp1_hwmod, - &omap3xxx_mcbsp2_hwmod, - &omap3xxx_mcbsp3_hwmod, - &omap3xxx_mcbsp4_hwmod, - &omap3xxx_mcbsp5_hwmod, - &omap3xxx_mcbsp2_sidetone_hwmod, - &omap3xxx_mcbsp3_sidetone_hwmod, - - - /* mcspi class */ - &omap34xx_mcspi1, - &omap34xx_mcspi2, - &omap34xx_mcspi3, - &omap34xx_mcspi4, - +static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l3_main__l4_core, + &omap3xxx_l3_main__l4_per, + &omap3xxx_mpu__l3_main, + &omap3xxx_l4_core__l4_wkup, + &omap3xxx_l4_core__mmc3, + &omap3_l4_core__uart1, + &omap3_l4_core__uart2, + &omap3_l4_per__uart3, + &omap3_l4_core__i2c1, + &omap3_l4_core__i2c2, + &omap3_l4_core__i2c3, + &omap3xxx_l4_wkup__l4_sec, + &omap3xxx_l4_wkup__timer1, + &omap3xxx_l4_per__timer2, + &omap3xxx_l4_per__timer3, + &omap3xxx_l4_per__timer4, + &omap3xxx_l4_per__timer5, + &omap3xxx_l4_per__timer6, + &omap3xxx_l4_per__timer7, + &omap3xxx_l4_per__timer8, + &omap3xxx_l4_per__timer9, + &omap3xxx_l4_core__timer10, + &omap3xxx_l4_core__timer11, + &omap3xxx_l4_wkup__wd_timer2, + &omap3xxx_l4_wkup__gpio1, + &omap3xxx_l4_per__gpio2, + &omap3xxx_l4_per__gpio3, + &omap3xxx_l4_per__gpio4, + &omap3xxx_l4_per__gpio5, + &omap3xxx_l4_per__gpio6, + &omap3xxx_dma_system__l3, + &omap3xxx_l4_core__dma_system, + &omap3xxx_l4_core__mcbsp1, + &omap3xxx_l4_per__mcbsp2, + &omap3xxx_l4_per__mcbsp3, + &omap3xxx_l4_per__mcbsp4, + &omap3xxx_l4_core__mcbsp5, + &omap3xxx_l4_per__mcbsp2_sidetone, + &omap3xxx_l4_per__mcbsp3_sidetone, + &omap34xx_l4_core__mcspi1, + &omap34xx_l4_core__mcspi2, + &omap34xx_l4_core__mcspi3, + &omap34xx_l4_core__mcspi4, NULL, }; -/* GP-only hwmods */ -static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { - &omap3xxx_timer12_hwmod, +/* GP-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_sec__timer12, NULL }; -/* 3430ES1-only hwmods */ -static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { - &omap3430es1_dss_core_hwmod, +/* 3430ES1-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { + &omap3430es1_dss__l3, + &omap3430es1_l4_core__dss, NULL }; -/* 3430ES2+-only hwmods */ -static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { - &omap3xxx_dss_core_hwmod, - &omap3xxx_usbhsotg_hwmod, - &omap3xxx_usb_host_hs_hwmod, - &omap3xxx_usb_tll_hs_hwmod, +/* 3430ES2+-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_dss__l3, + &omap3xxx_l4_core__dss, + &omap3xxx_usbhsotg__l3, + &omap3xxx_l4_core__usbhsotg, + &omap3xxx_usb_host_hs__l3_main_2, + &omap3xxx_l4_core__usb_host_hs, + &omap3xxx_l4_core__usb_tll_hs, NULL }; -/* <= 3430ES3-only hwmods */ -static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { - &omap3xxx_pre_es3_mmc1_hwmod, - &omap3xxx_pre_es3_mmc2_hwmod, +/* <= 3430ES3-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_core__pre_es3_mmc1, + &omap3xxx_l4_core__pre_es3_mmc2, NULL }; -/* 3430ES3+-only hwmods */ -static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { - &omap3xxx_es3plus_mmc1_hwmod, - &omap3xxx_es3plus_mmc2_hwmod, +/* 3430ES3+-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_core__es3plus_mmc1, + &omap3xxx_l4_core__es3plus_mmc2, NULL }; -/* 34xx-only hwmods (all ES revisions) */ -static __initdata struct omap_hwmod *omap34xx_hwmods[] = { - &omap3xxx_iva_hwmod, - &omap34xx_sr1_hwmod, - &omap34xx_sr2_hwmod, - &omap3xxx_mailbox_hwmod, +/* 34xx-only hwmod links (all ES revisions) */ +static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l3__iva, + &omap34xx_l4_core__sr1, + &omap34xx_l4_core__sr2, + &omap3xxx_l4_core__mailbox, NULL }; -/* 36xx-only hwmods (all ES revisions) */ -static __initdata struct omap_hwmod *omap36xx_hwmods[] = { - &omap3xxx_iva_hwmod, - &omap3xxx_uart4_hwmod, - &omap3xxx_dss_core_hwmod, - &omap36xx_sr1_hwmod, - &omap36xx_sr2_hwmod, - &omap3xxx_usbhsotg_hwmod, - &omap3xxx_mailbox_hwmod, - &omap3xxx_usb_host_hs_hwmod, - &omap3xxx_usb_tll_hs_hwmod, - &omap3xxx_es3plus_mmc1_hwmod, - &omap3xxx_es3plus_mmc2_hwmod, +/* 36xx-only hwmod links (all ES revisions) */ +static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l3__iva, + &omap36xx_l4_per__uart4, + &omap3xxx_dss__l3, + &omap3xxx_l4_core__dss, + &omap36xx_l4_core__sr1, + &omap36xx_l4_core__sr2, + &omap3xxx_usbhsotg__l3, + &omap3xxx_l4_core__usbhsotg, + &omap3xxx_l4_core__mailbox, + &omap3xxx_usb_host_hs__l3_main_2, + &omap3xxx_l4_core__usb_host_hs, + &omap3xxx_l4_core__usb_tll_hs, + &omap3xxx_l4_core__es3plus_mmc1, + &omap3xxx_l4_core__es3plus_mmc2, NULL }; -static __initdata struct omap_hwmod *am35xx_hwmods[] = { - &omap3xxx_dss_core_hwmod, /* XXX ??? */ - &am35xx_usbhsotg_hwmod, - &am35xx_uart4_hwmod, - &omap3xxx_usb_host_hs_hwmod, - &omap3xxx_usb_tll_hs_hwmod, - &omap3xxx_es3plus_mmc1_hwmod, - &omap3xxx_es3plus_mmc2_hwmod, +static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_dss__l3, + &omap3xxx_l4_core__dss, + &am35xx_usbhsotg__l3, + &am35xx_l4_core__usbhsotg, + &am35xx_l4_core__uart4, + &omap3xxx_usb_host_hs__l3_main_2, + &omap3xxx_l4_core__usb_host_hs, + &omap3xxx_l4_core__usb_tll_hs, + &omap3xxx_l4_core__es3plus_mmc1, + &omap3xxx_l4_core__es3plus_mmc2, NULL }; -static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { - /* dss class */ - &omap3xxx_dss_dispc_hwmod, - &omap3xxx_dss_dsi1_hwmod, - &omap3xxx_dss_rfbi_hwmod, - &omap3xxx_dss_venc_hwmod, +static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_core__dss_dispc, + &omap3xxx_l4_core__dss_dsi1, + &omap3xxx_l4_core__dss_rfbi, + &omap3xxx_l4_core__dss_venc, NULL }; int __init omap3xxx_hwmod_init(void) { int r; - struct omap_hwmod **h = NULL; + struct omap_hwmod_ocp_if **h = NULL; unsigned int rev; - /* Register hwmods common to all OMAP3 */ - r = omap_hwmod_register(omap3xxx_hwmods); + /* Register hwmod links common to all OMAP3 */ + r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); if (r < 0) return r; - /* Register GP-only hwmods. */ + /* Register GP-only hwmod links. */ if (omap_type() == OMAP2_DEVICE_TYPE_GP) { - r = omap_hwmod_register(omap3xxx_gp_hwmods); + r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); if (r < 0) return r; } @@ -3703,43 +3216,43 @@ int __init omap3xxx_hwmod_init(void) rev = omap_rev(); /* - * Register hwmods common to individual OMAP3 families, all + * Register hwmod links common to individual OMAP3 families, all * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) * All possible revisions should be included in this conditional. */ if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap34xx_hwmods; + h = omap34xx_hwmod_ocp_ifs; } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { - h = am35xx_hwmods; + h = am35xx_hwmod_ocp_ifs; } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) { - h = omap36xx_hwmods; + h = omap36xx_hwmod_ocp_ifs; } else { WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); return -EINVAL; }; - r = omap_hwmod_register(h); + r = omap_hwmod_register_links(h); if (r < 0) return r; /* - * Register hwmods specific to certain ES levels of a + * Register hwmod links specific to certain ES levels of a * particular family of silicon (e.g., 34xx ES1.0) */ h = NULL; if (rev == OMAP3430_REV_ES1_0) { - h = omap3430es1_hwmods; + h = omap3430es1_hwmod_ocp_ifs; } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap3430es2plus_hwmods; + h = omap3430es2plus_hwmod_ocp_ifs; }; if (h) { - r = omap_hwmod_register(h); + r = omap_hwmod_register_links(h); if (r < 0) return r; } @@ -3747,29 +3260,29 @@ int __init omap3xxx_hwmod_init(void) h = NULL; if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1) { - h = omap3430_pre_es3_hwmods; + h = omap3430_pre_es3_hwmod_ocp_ifs; } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap3430_es3plus_hwmods; + h = omap3430_es3plus_hwmod_ocp_ifs; }; if (h) - r = omap_hwmod_register(h); + r = omap_hwmod_register_links(h); if (r < 0) return r; /* * DSS code presumes that dss_core hwmod is handled first, * _before_ any other DSS related hwmods so register common - * DSS hwmods last to ensure that dss_core is already registered. - * Otherwise some change things may happen, for ex. if dispc - * is handled before dss_core and DSS is enabled in bootloader - * DIPSC will be reset with outputs enabled which sometimes leads - * to unrecoverable L3 error. - * XXX The long-term fix to this is to ensure modules are set up - * in dependency order in the hwmod core code. + * DSS hwmod links last to ensure that dss_core is already + * registered. Otherwise some change things may happen, for + * ex. if dispc is handled before dss_core and DSS is enabled + * in bootloader DISPC will be reset with outputs enabled + * which sometimes leads to unrecoverable L3 error. XXX The + * long-term fix to this is to ensure hwmods are set up in + * dependency order in the hwmod core code. */ - r = omap_hwmod_register(omap3xxx_dss_hwmods); + r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); return r; } diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 6abc75753e42..0d91dec5b4bc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1,7 +1,7 @@ /* * Hardware modules present on the OMAP44xx chips * - * Copyright (C) 2009-2011 Texas Instruments, Inc. + * Copyright (C) 2009-2012 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley @@ -44,38 +44,10 @@ #define OMAP44XX_IRQ_GIC_START 32 /* Base offset for all OMAP4 dma requests */ -#define OMAP44XX_DMA_REQ_START 1 - -/* Backward references (IPs with Bus Master capability) */ -static struct omap_hwmod omap44xx_aess_hwmod; -static struct omap_hwmod omap44xx_dma_system_hwmod; -static struct omap_hwmod omap44xx_dmm_hwmod; -static struct omap_hwmod omap44xx_dsp_hwmod; -static struct omap_hwmod omap44xx_dss_hwmod; -static struct omap_hwmod omap44xx_emif_fw_hwmod; -static struct omap_hwmod omap44xx_hsi_hwmod; -static struct omap_hwmod omap44xx_ipu_hwmod; -static struct omap_hwmod omap44xx_iss_hwmod; -static struct omap_hwmod omap44xx_iva_hwmod; -static struct omap_hwmod omap44xx_l3_instr_hwmod; -static struct omap_hwmod omap44xx_l3_main_1_hwmod; -static struct omap_hwmod omap44xx_l3_main_2_hwmod; -static struct omap_hwmod omap44xx_l3_main_3_hwmod; -static struct omap_hwmod omap44xx_l4_abe_hwmod; -static struct omap_hwmod omap44xx_l4_cfg_hwmod; -static struct omap_hwmod omap44xx_l4_per_hwmod; -static struct omap_hwmod omap44xx_l4_wkup_hwmod; -static struct omap_hwmod omap44xx_mmc1_hwmod; -static struct omap_hwmod omap44xx_mmc2_hwmod; -static struct omap_hwmod omap44xx_mpu_hwmod; -static struct omap_hwmod omap44xx_mpu_private_hwmod; -static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; -static struct omap_hwmod omap44xx_usb_host_hs_hwmod; -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; +#define OMAP44XX_DMA_REQ_START 1 /* - * Interconnects omap_hwmod structures - * hwmods that compose the global OMAP interconnect + * IP blocks */ /* @@ -92,51 +64,17 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { { .irq = -1 } }; -/* l3_main_1 -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { - { - .pa_start = 0x4e000000, - .pa_end = 0x4e0007ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_dmm_addrs, - .user = OCP_USER_MPU, -}; - -/* dmm slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { - &omap44xx_l3_main_1__dmm, - &omap44xx_mpu__dmm, -}; - static struct omap_hwmod omap44xx_dmm_hwmod = { .name = "dmm", .class = &omap44xx_dmm_hwmod_class, .clkdm_name = "l3_emif_clkdm", + .mpu_irqs = omap44xx_dmm_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_dmm_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), - .mpu_irqs = omap44xx_dmm_irqs, }; /* @@ -148,38 +86,6 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { }; /* emif_fw */ -/* dmm -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { - .master = &omap44xx_dmm_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { - { - .pa_start = 0x4a20c000, - .pa_end = 0x4a20c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_emif_fw_addrs, - .user = OCP_USER_MPU, -}; - -/* emif_fw slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { - &omap44xx_dmm__emif_fw, - &omap44xx_l4_cfg__emif_fw, -}; - static struct omap_hwmod omap44xx_emif_fw_hwmod = { .name = "emif_fw", .class = &omap44xx_emif_fw_hwmod_class, @@ -190,8 +96,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = { .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_emif_fw_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), }; /* @@ -203,28 +107,6 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = { }; /* l3_instr */ -/* iva -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_3 -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { - .master = &omap44xx_l3_main_3_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_instr slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { - &omap44xx_iva__l3_instr, - &omap44xx_l3_main_3__l3_instr, -}; - static struct omap_hwmod omap44xx_l3_instr_hwmod = { .name = "l3_instr", .class = &omap44xx_l3_hwmod_class, @@ -236,8 +118,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_l3_instr_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), }; /* l3_main_1 */ @@ -247,83 +127,6 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { { .irq = -1 } }; -/* dsp -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { - .master = &omap44xx_dss_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc1 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { - .master = &omap44xx_mmc1_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { - .master = &omap44xx_mmc2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { - { - .pa_start = 0x44000000, - .pa_end = 0x44000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_1_addrs, - .user = OCP_USER_MPU, -}; - -/* l3_main_1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { - &omap44xx_dsp__l3_main_1, - &omap44xx_dss__l3_main_1, - &omap44xx_l3_main_2__l3_main_1, - &omap44xx_l4_cfg__l3_main_1, - &omap44xx_mmc1__l3_main_1, - &omap44xx_mmc2__l3_main_1, - &omap44xx_mpu__l3_main_1, -}; - static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .name = "l3_main_1", .class = &omap44xx_l3_hwmod_class, @@ -335,97 +138,9 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l3_main_1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), }; /* l3_main_2 */ -/* dma_system -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { - .master = &omap44xx_dma_system_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* hsi -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { - .master = &omap44xx_hsi_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* ipu -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { - .master = &omap44xx_ipu_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iss -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { - .master = &omap44xx_iss_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iva -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { - { - .pa_start = 0x44800000, - .pa_end = 0x44801fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_2_addrs, - .user = OCP_USER_MPU, -}; - -/* l4_cfg -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_otg_hs -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { - .master = &omap44xx_usb_otg_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { - &omap44xx_dma_system__l3_main_2, - &omap44xx_hsi__l3_main_2, - &omap44xx_ipu__l3_main_2, - &omap44xx_iss__l3_main_2, - &omap44xx_iva__l3_main_2, - &omap44xx_l3_main_1__l3_main_2, - &omap44xx_l4_cfg__l3_main_2, - &omap44xx_usb_otg_hs__l3_main_2, -}; - static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .name = "l3_main_2", .class = &omap44xx_l3_hwmod_class, @@ -436,52 +151,9 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l3_main_2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), }; /* l3_main_3 */ -static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { - { - .pa_start = 0x45000000, - .pa_end = 0x45000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_3_addrs, - .user = OCP_USER_MPU, -}; - -/* l3_main_2 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { - &omap44xx_l3_main_1__l3_main_3, - &omap44xx_l3_main_2__l3_main_3, - &omap44xx_l4_cfg__l3_main_3, -}; - static struct omap_hwmod omap44xx_l3_main_3_hwmod = { .name = "l3_main_3", .class = &omap44xx_l3_hwmod_class, @@ -493,8 +165,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_l3_main_3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), }; /* @@ -506,46 +176,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { }; /* l4_abe */ -/* aess -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { - .master = &omap44xx_aess_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dsp -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { - &omap44xx_aess__l4_abe, - &omap44xx_dsp__l4_abe, - &omap44xx_l3_main_1__l4_abe, - &omap44xx_mpu__l4_abe, -}; - static struct omap_hwmod omap44xx_l4_abe_hwmod = { .name = "l4_abe", .class = &omap44xx_l4_hwmod_class, @@ -555,24 +185,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, }, }, - .slaves = omap44xx_l4_abe_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), }; /* l4_cfg */ -/* l3_main_1 -> l4_cfg */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_cfg_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { - &omap44xx_l3_main_1__l4_cfg, -}; - static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .name = "l4_cfg", .class = &omap44xx_l4_hwmod_class, @@ -583,24 +198,9 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l4_cfg_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), }; /* l4_per */ -/* l3_main_2 -> l4_per */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l4_per_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { - &omap44xx_l3_main_2__l4_per, -}; - static struct omap_hwmod omap44xx_l4_per_hwmod = { .name = "l4_per", .class = &omap44xx_l4_hwmod_class, @@ -611,24 +211,9 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l4_per_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), }; /* l4_wkup */ -/* l4_cfg -> l4_wkup */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l4_wkup_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { - &omap44xx_l4_cfg__l4_wkup, -}; - static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .name = "l4_wkup", .class = &omap44xx_l4_hwmod_class, @@ -639,8 +224,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), }; /* @@ -652,25 +235,10 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { }; /* mpu_private */ -/* mpu -> mpu_private */ -static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_mpu_private_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu_private slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { - &omap44xx_mpu__mpu_private, -}; - static struct omap_hwmod omap44xx_mpu_private_hwmod = { .name = "mpu_private", .class = &omap44xx_mpu_bus_hwmod_class, .clkdm_name = "mpuss_clkdm", - .slaves = omap44xx_mpu_private_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), }; /* @@ -756,53 +324,6 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { { .dma_req = -1 } }; -/* aess master ports */ -static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { - &omap44xx_aess__l4_abe, -}; - -static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { - { - .pa_start = 0x401f1000, - .pa_end = 0x401f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { - { - .pa_start = 0x490f1000, - .pa_end = 0x490f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* aess slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { - &omap44xx_l4_abe__aess, - &omap44xx_l4_abe__aess_dma, -}; - static struct omap_hwmod omap44xx_aess_hwmod = { .name = "aess", .class = &omap44xx_aess_hwmod_class, @@ -817,37 +338,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_aess_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), - .masters = omap44xx_aess_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), -}; - -/* - * 'bandgap' class - * bangap reference for ldo regulators - */ - -static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { - .name = "bandgap", -}; - -/* bandgap */ -static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { - { .role = "fclk", .clk = "bandgap_fclk" }, -}; - -static struct omap_hwmod omap44xx_bandgap_hwmod = { - .name = "bandgap", - .class = &omap44xx_bandgap_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, - }, - }, - .opt_clks = bandgap_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), }; /* @@ -870,30 +360,6 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = { }; /* counter_32k */ -static struct omap_hwmod omap44xx_counter_32k_hwmod; -static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { - { - .pa_start = 0x4a304000, - .pa_end = 0x4a30401f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_counter_32k_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_counter_32k_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* counter_32k slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { - &omap44xx_l4_wkup__counter_32k, -}; - static struct omap_hwmod omap44xx_counter_32k_hwmod = { .name = "counter_32k", .class = &omap44xx_counter_hwmod_class, @@ -906,8 +372,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_counter_32k_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), }; /* @@ -950,34 +414,6 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { { .irq = -1 } }; -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { - &omap44xx_dma_system__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { - { - .pa_start = 0x4a056000, - .pa_end = 0x4a056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dma_system_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { - &omap44xx_l4_cfg__dma_system, -}; - static struct omap_hwmod omap44xx_dma_system_hwmod = { .name = "dma_system", .class = &omap44xx_dma_hwmod_class, @@ -991,10 +427,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { }, }, .dev_attr = &dma_dev_attr, - .slaves = omap44xx_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), - .masters = omap44xx_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), }; /* @@ -1018,7 +450,6 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { }; /* dmic */ -static struct omap_hwmod omap44xx_dmic_hwmod; static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { { .irq = 114 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1029,50 +460,6 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4012e000, - .pa_end = 0x4012e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x4902e000, - .pa_end = 0x4902e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* dmic slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { - &omap44xx_l4_abe__dmic, - &omap44xx_l4_abe__dmic_dma, -}; - static struct omap_hwmod omap44xx_dmic_hwmod = { .name = "dmic", .class = &omap44xx_dmic_hwmod_class, @@ -1087,8 +474,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_dmic_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), }; /* @@ -1107,53 +492,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { }; static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; - -static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { { .name = "dsp", .rst_shift = 0 }, -}; - -/* dsp -> iva */ -static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "dpll_iva_m5x2_ck", -}; - -/* dsp master ports */ -static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { - &omap44xx_dsp__l3_main_1, - &omap44xx_dsp__l4_abe, - &omap44xx_dsp__iva, -}; - -/* l4_cfg -> dsp */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dsp_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dsp slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { - &omap44xx_l4_cfg__dsp, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_dsp_c0_hwmod = { - .name = "dsp_c0", - .class = &omap44xx_dsp_hwmod_class, - .clkdm_name = "tesla_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_dsp_c0_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, - }, - }, + { .name = "mmu_cache", .rst_shift = 1 }, }; static struct omap_hwmod omap44xx_dsp_hwmod = { @@ -1172,10 +512,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_dsp_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), - .masters = omap44xx_dsp_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), }; /* @@ -1196,53 +532,6 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = { }; /* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { - &omap44xx_dss__l3_main_1, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { - { - .pa_start = 0x58000000, - .pa_end = 0x5800007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { - { - .pa_start = 0x48040000, - .pa_end = 0x4804007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_addrs, - .user = OCP_USER_MPU, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { - &omap44xx_l3_main_2__dss, - &omap44xx_l4_per__dss, -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, { .role = "tv_clk", .clk = "dss_tv_clk" }, @@ -1263,10 +552,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = { }, .opt_clks = dss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap44xx_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), - .masters = omap44xx_dss_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), }; /* @@ -1293,7 +578,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { }; /* dss_dispc */ -static struct omap_hwmod omap44xx_dss_dispc_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { { .irq = 25 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1304,53 +588,11 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { - { - .pa_start = 0x58001000, - .pa_end = 0x58001fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dispc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { - { - .pa_start = 0x48041000, - .pa_end = 0x48041fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { .manager_count = 3, .has_framedonetv_irq = 1 }; -/* l4_per -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dispc_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { - &omap44xx_l3_main_2__dss_dispc, - &omap44xx_l4_per__dss_dispc, -}; - static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap44xx_dispc_hwmod_class, @@ -1364,8 +606,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), .dev_attr = &omap44xx_dss_dispc_dev_attr }; @@ -1391,7 +631,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { }; /* dss_dsi1 */ -static struct omap_hwmod omap44xx_dss_dsi1_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { { .irq = 53 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1402,48 +641,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { - { - .pa_start = 0x58004000, - .pa_end = 0x580041ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { - { - .pa_start = 0x48044000, - .pa_end = 0x480441ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi1_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_dsi1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { - &omap44xx_l3_main_2__dss_dsi1, - &omap44xx_l4_per__dss_dsi1, -}; - static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1463,12 +660,9 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { }, .opt_clks = dss_dsi1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), - .slaves = omap44xx_dss_dsi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), }; /* dss_dsi2 */ -static struct omap_hwmod omap44xx_dss_dsi2_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { { .irq = 84 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1479,48 +673,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { - { - .pa_start = 0x58005000, - .pa_end = 0x580051ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { - { - .pa_start = 0x48045000, - .pa_end = 0x480451ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi2_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_dsi2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { - &omap44xx_l3_main_2__dss_dsi2, - &omap44xx_l4_per__dss_dsi2, -}; - static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1540,8 +692,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { }, .opt_clks = dss_dsi2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), - .slaves = omap44xx_dss_dsi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), }; /* @@ -1565,7 +715,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { }; /* dss_hdmi */ -static struct omap_hwmod omap44xx_dss_hdmi_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { { .irq = 101 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1576,48 +725,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { - { - .pa_start = 0x58006000, - .pa_end = 0x58006fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_hdmi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { - { - .pa_start = 0x48046000, - .pa_end = 0x48046fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_hdmi_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_hdmi slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { - &omap44xx_l3_main_2__dss_hdmi, - &omap44xx_l4_per__dss_hdmi, -}; - static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1637,8 +744,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { }, .opt_clks = dss_hdmi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), - .slaves = omap44xx_dss_hdmi_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), }; /* @@ -1662,54 +767,11 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { }; /* dss_rfbi */ -static struct omap_hwmod omap44xx_dss_rfbi_hwmod; static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { - { - .pa_start = 0x58002000, - .pa_end = 0x580020ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_rfbi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { - { - .pa_start = 0x48042000, - .pa_end = 0x480420ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_rfbi_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { - &omap44xx_l3_main_2__dss_rfbi, - &omap44xx_l4_per__dss_rfbi, -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_fck" }, }; @@ -1728,8 +790,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { }, .opt_clks = dss_rfbi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap44xx_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), }; /* @@ -1742,49 +802,6 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = { }; /* dss_venc */ -static struct omap_hwmod omap44xx_dss_venc_hwmod; -static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { - { - .pa_start = 0x58003000, - .pa_end = 0x580030ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_venc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { - { - .pa_start = 0x48043000, - .pa_end = 0x480430ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_venc_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { - &omap44xx_l3_main_2__dss_venc, - &omap44xx_l4_per__dss_venc, -}; - static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, @@ -1796,8 +813,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), }; /* @@ -1830,35 +845,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { }; /* gpio1 */ -static struct omap_hwmod omap44xx_gpio1_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { { .irq = 29 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { - { - .pa_start = 0x4a310000, - .pa_end = 0x4a3101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_gpio1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { - &omap44xx_l4_wkup__gpio1, -}; - static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, }; @@ -1879,40 +870,14 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), }; /* gpio2 */ -static struct omap_hwmod omap44xx_gpio2_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { { .irq = 30 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { - { - .pa_start = 0x48055000, - .pa_end = 0x480551ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { - &omap44xx_l4_per__gpio2, -}; - static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbclk" }, }; @@ -1934,40 +899,14 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), }; /* gpio3 */ -static struct omap_hwmod omap44xx_gpio3_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { { .irq = 31 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { - { - .pa_start = 0x48057000, - .pa_end = 0x480571ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { - &omap44xx_l4_per__gpio3, -}; - static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbclk" }, }; @@ -1989,40 +928,14 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .opt_clks = gpio3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), }; /* gpio4 */ -static struct omap_hwmod omap44xx_gpio4_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { { .irq = 32 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { - { - .pa_start = 0x48059000, - .pa_end = 0x480591ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { - &omap44xx_l4_per__gpio4, -}; - static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { { .role = "dbclk", .clk = "gpio4_dbclk" }, }; @@ -2044,40 +957,14 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .opt_clks = gpio4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), }; /* gpio5 */ -static struct omap_hwmod omap44xx_gpio5_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { { .irq = 33 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { - { - .pa_start = 0x4805b000, - .pa_end = 0x4805b1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio5 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { - &omap44xx_l4_per__gpio5, -}; - static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { { .role = "dbclk", .clk = "gpio5_dbclk" }, }; @@ -2099,40 +986,14 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .opt_clks = gpio5_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio5_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), }; /* gpio6 */ -static struct omap_hwmod omap44xx_gpio6_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { { .irq = 34 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { - { - .pa_start = 0x4805d000, - .pa_end = 0x4805d1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio6_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio6 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { - &omap44xx_l4_per__gpio6, -}; - static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { { .role = "dbclk", .clk = "gpio6_dbclk" }, }; @@ -2154,8 +1015,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .opt_clks = gpio6_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio6_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), }; /* @@ -2190,34 +1049,6 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { { .irq = -1 } }; -/* hsi master ports */ -static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { - &omap44xx_hsi__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { - { - .pa_start = 0x4a058000, - .pa_end = 0x4a05bfff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> hsi */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_hsi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_hsi_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* hsi slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { - &omap44xx_l4_cfg__hsi, -}; - static struct omap_hwmod omap44xx_hsi_hwmod = { .name = "hsi", .class = &omap44xx_hsi_hwmod_class, @@ -2231,10 +1062,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_hsi_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), - .masters = omap44xx_hsi_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), }; /* @@ -2266,7 +1093,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* i2c1 */ -static struct omap_hwmod omap44xx_i2c1_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { { .irq = 56 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2278,29 +1104,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { - { - .pa_start = 0x48070000, - .pa_end = 0x480700ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { - &omap44xx_l4_per__i2c1, -}; - static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, @@ -2316,13 +1119,10 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c2 */ -static struct omap_hwmod omap44xx_i2c2_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { { .irq = 57 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2334,29 +1134,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { - { - .pa_start = 0x48072000, - .pa_end = 0x480720ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { - &omap44xx_l4_per__i2c2, -}; - static struct omap_hwmod omap44xx_i2c2_hwmod = { .name = "i2c2", .class = &omap44xx_i2c_hwmod_class, @@ -2372,13 +1149,10 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c3 */ -static struct omap_hwmod omap44xx_i2c3_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { { .irq = 61 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2390,29 +1164,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x480600ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { - &omap44xx_l4_per__i2c3, -}; - static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, @@ -2428,13 +1179,10 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c4 */ -static struct omap_hwmod omap44xx_i2c4_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { { .irq = 62 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2446,29 +1194,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { - { - .pa_start = 0x48350000, - .pa_end = 0x483500ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { - &omap44xx_l4_per__i2c4, -}; - static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, @@ -2484,8 +1209,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), .dev_attr = &i2c_dev_attr, }; @@ -2504,66 +1227,12 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { +static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "cpu0", .rst_shift = 0 }, -}; - -static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { { .name = "cpu1", .rst_shift = 1 }, -}; - -static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, }; -/* ipu master ports */ -static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { - &omap44xx_ipu__l3_main_2, -}; - -/* l3_main_2 -> ipu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_ipu_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* ipu slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { - &omap44xx_l3_main_2__ipu, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_ipu_c0_hwmod = { - .name = "ipu_c0", - .class = &omap44xx_ipu_hwmod_class, - .clkdm_name = "ducati_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_ipu_c0_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, - }, - }, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_ipu_c1_hwmod = { - .name = "ipu_c1", - .class = &omap44xx_ipu_hwmod_class, - .clkdm_name = "ducati_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_ipu_c1_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, - }, - }, -}; - static struct omap_hwmod omap44xx_ipu_hwmod = { .name = "ipu", .class = &omap44xx_ipu_hwmod_class, @@ -2580,10 +1249,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_ipu_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), - .masters = omap44xx_ipu_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), }; /* @@ -2630,34 +1295,6 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { { .dma_req = -1 } }; -/* iss master ports */ -static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { - &omap44xx_iss__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { - { - .pa_start = 0x52000000, - .pa_end = 0x520000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iss_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iss slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { - &omap44xx_l3_main_2__iss, -}; - static struct omap_hwmod_opt_clk iss_opt_clks[] = { { .role = "ctrlclk", .clk = "iss_ctrlclk" }, }; @@ -2678,10 +1315,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = { }, .opt_clks = iss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), - .slaves = omap44xx_iss_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), - .masters = omap44xx_iss_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), }; /* @@ -2702,75 +1335,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { }; static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { - { .name = "logic", .rst_shift = 2 }, -}; - -static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { { .name = "seq0", .rst_shift = 0 }, -}; - -static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { { .name = "seq1", .rst_shift = 1 }, -}; - -/* iva master ports */ -static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { - &omap44xx_iva__l3_main_2, - &omap44xx_iva__l3_instr, -}; - -static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { - { - .pa_start = 0x5a000000, - .pa_end = 0x5a07ffff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iva */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iva_addrs, - .user = OCP_USER_MPU, -}; - -/* iva slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { - &omap44xx_dsp__iva, - &omap44xx_l3_main_2__iva, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_iva_seq0_hwmod = { - .name = "iva_seq0", - .class = &omap44xx_iva_hwmod_class, - .clkdm_name = "ivahd_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_iva_seq0_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, - }, - }, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_iva_seq1_hwmod = { - .name = "iva_seq1", - .class = &omap44xx_iva_hwmod_class, - .clkdm_name = "ivahd_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_iva_seq1_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, - }, - }, + { .name = "logic", .rst_shift = 2 }, }; static struct omap_hwmod omap44xx_iva_hwmod = { @@ -2789,10 +1356,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_iva_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), - .masters = omap44xx_iva_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), }; /* @@ -2818,35 +1381,11 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { }; /* kbd */ -static struct omap_hwmod omap44xx_kbd_hwmod; static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { { .irq = 120 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { - { - .pa_start = 0x4a31c000, - .pa_end = 0x4a31c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> kbd */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_kbd_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_kbd_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* kbd slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { - &omap44xx_l4_wkup__kbd, -}; - static struct omap_hwmod omap44xx_kbd_hwmod = { .name = "kbd", .class = &omap44xx_kbd_hwmod_class, @@ -2860,8 +1399,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_kbd_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), }; /* @@ -2885,35 +1422,11 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { }; /* mailbox */ -static struct omap_hwmod omap44xx_mailbox_hwmod; static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { { .irq = 26 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { - { - .pa_start = 0x4a0f4000, - .pa_end = 0x4a0f41ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> mailbox */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_mailbox_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { - &omap44xx_l4_cfg__mailbox, -}; - static struct omap_hwmod omap44xx_mailbox_hwmod = { .name = "mailbox", .class = &omap44xx_mailbox_hwmod_class, @@ -2925,8 +1438,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), }; /* @@ -2949,7 +1460,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { }; /* mcbsp1 */ -static struct omap_hwmod omap44xx_mcbsp1_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { { .irq = 17 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2961,50 +1471,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40122000, - .pa_end = 0x401220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { - &omap44xx_l4_abe__mcbsp1, - &omap44xx_l4_abe__mcbsp1_dma, -}; - static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, @@ -3024,14 +1490,11 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), .opt_clks = mcbsp1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), }; /* mcbsp2 */ -static struct omap_hwmod omap44xx_mcbsp2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { { .irq = 22 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3043,50 +1506,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40124000, - .pa_end = 0x401240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { - &omap44xx_l4_abe__mcbsp2, - &omap44xx_l4_abe__mcbsp2_dma, -}; - static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, @@ -3106,14 +1525,11 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), .opt_clks = mcbsp2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), }; /* mcbsp3 */ -static struct omap_hwmod omap44xx_mcbsp3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { { .irq = 23 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3125,50 +1541,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40126000, - .pa_end = 0x401260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcbsp3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { - &omap44xx_l4_abe__mcbsp3, - &omap44xx_l4_abe__mcbsp3_dma, -}; - static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, @@ -3188,14 +1560,11 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), .opt_clks = mcbsp3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), }; /* mcbsp4 */ -static struct omap_hwmod omap44xx_mcbsp4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { { .irq = 16 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3207,29 +1576,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { - { - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcbsp4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { - &omap44xx_l4_per__mcbsp4, -}; - static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, @@ -3249,8 +1595,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), .opt_clks = mcbsp4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), }; @@ -3277,7 +1621,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { }; /* mcpdm */ -static struct omap_hwmod omap44xx_mcpdm_hwmod; static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { { .irq = 112 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3289,48 +1632,6 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { - { - .pa_start = 0x40132000, - .pa_end = 0x4013207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x4903207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcpdm slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { - &omap44xx_l4_abe__mcpdm, - &omap44xx_l4_abe__mcpdm_dma, -}; - static struct omap_hwmod omap44xx_mcpdm_hwmod = { .name = "mcpdm", .class = &omap44xx_mcpdm_hwmod_class, @@ -3345,8 +1646,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcpdm_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), }; /* @@ -3372,7 +1671,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { }; /* mcspi1 */ -static struct omap_hwmod omap44xx_mcspi1_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { { .irq = 65 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3390,29 +1688,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { - { - .pa_start = 0x48098000, - .pa_end = 0x480981ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { - &omap44xx_l4_per__mcspi1, -}; - /* mcspi1 dev_attr */ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { .num_chipselect = 4, @@ -3433,12 +1708,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { }, }, .dev_attr = &mcspi1_dev_attr, - .slaves = omap44xx_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), }; /* mcspi2 */ -static struct omap_hwmod omap44xx_mcspi2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { { .irq = 66 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3452,29 +1724,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { - { - .pa_start = 0x4809a000, - .pa_end = 0x4809a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { - &omap44xx_l4_per__mcspi2, -}; - /* mcspi2 dev_attr */ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { .num_chipselect = 2, @@ -3495,12 +1744,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { }, }, .dev_attr = &mcspi2_dev_attr, - .slaves = omap44xx_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), }; /* mcspi3 */ -static struct omap_hwmod omap44xx_mcspi3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { { .irq = 91 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3514,29 +1760,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { - { - .pa_start = 0x480b8000, - .pa_end = 0x480b81ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { - &omap44xx_l4_per__mcspi3, -}; - /* mcspi3 dev_attr */ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { .num_chipselect = 2, @@ -3557,12 +1780,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { }, }, .dev_attr = &mcspi3_dev_attr, - .slaves = omap44xx_mcspi3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), }; /* mcspi4 */ -static struct omap_hwmod omap44xx_mcspi4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { { .irq = 48 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3574,29 +1794,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { - &omap44xx_l4_per__mcspi4, -}; - /* mcspi4 dev_attr */ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { .num_chipselect = 1, @@ -3617,8 +1814,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { }, }, .dev_attr = &mcspi4_dev_attr, - .slaves = omap44xx_mcspi4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), }; /* @@ -3655,34 +1850,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { { .dma_req = -1 } }; -/* mmc1 master ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { - &omap44xx_mmc1__l3_main_1, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { - { - .pa_start = 0x4809c000, - .pa_end = 0x4809c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { - &omap44xx_l4_per__mmc1, -}; - /* mmc1 dev_attr */ static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, @@ -3703,10 +1870,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { }, }, .dev_attr = &mmc1_dev_attr, - .slaves = omap44xx_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), - .masters = omap44xx_mmc1_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), }; /* mmc2 */ @@ -3721,34 +1884,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { { .dma_req = -1 } }; -/* mmc2 master ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { - &omap44xx_mmc2__l3_main_1, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { - { - .pa_start = 0x480b4000, - .pa_end = 0x480b43ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { - &omap44xx_l4_per__mmc2, -}; - static struct omap_hwmod omap44xx_mmc2_hwmod = { .name = "mmc2", .class = &omap44xx_mmc_hwmod_class, @@ -3763,14 +1898,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), - .masters = omap44xx_mmc2_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), }; /* mmc3 */ -static struct omap_hwmod omap44xx_mmc3_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { { .irq = 94 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3782,29 +1912,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { - &omap44xx_l4_per__mmc3, -}; - static struct omap_hwmod omap44xx_mmc3_hwmod = { .name = "mmc3", .class = &omap44xx_mmc_hwmod_class, @@ -3819,12 +1926,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), }; /* mmc4 */ -static struct omap_hwmod omap44xx_mmc4_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { { .irq = 96 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3836,35 +1940,11 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { - { - .pa_start = 0x480d1000, - .pa_end = 0x480d13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { - &omap44xx_l4_per__mmc4, -}; - static struct omap_hwmod omap44xx_mmc4_hwmod = { .name = "mmc4", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mmc4_irqs, - .sdma_reqs = omap44xx_mmc4_sdma_reqs, .main_clk = "mmc4_fck", .prcm = { @@ -3874,12 +1954,9 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), }; /* mmc5 */ -static struct omap_hwmod omap44xx_mmc5_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { { .irq = 59 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3891,29 +1968,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { - { - .pa_start = 0x480d5000, - .pa_end = 0x480d53ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc5 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { - &omap44xx_l4_per__mmc5, -}; - static struct omap_hwmod omap44xx_mmc5_hwmod = { .name = "mmc5", .class = &omap44xx_mmc_hwmod_class, @@ -3928,8 +1982,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc5_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), }; /* @@ -3949,13 +2001,6 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { { .irq = -1 } }; -/* mpu master ports */ -static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { - &omap44xx_mpu__l3_main_1, - &omap44xx_mpu__l4_abe, - &omap44xx_mpu__dmm, -}; - static struct omap_hwmod omap44xx_mpu_hwmod = { .name = "mpu", .class = &omap44xx_mpu_hwmod_class, @@ -3969,8 +2014,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, }, }, - .masters = omap44xx_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), }; /* @@ -4004,35 +2047,11 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { .sensor_voltdm_name = "core", }; -static struct omap_hwmod omap44xx_smartreflex_core_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { { .irq = 19 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { - { - .pa_start = 0x4a0dd000, - .pa_end = 0x4a0dd03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_core_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_core_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* smartreflex_core slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { - &omap44xx_l4_cfg__smartreflex_core, -}; - static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .name = "smartreflex_core", .class = &omap44xx_smartreflex_hwmod_class, @@ -4047,8 +2066,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_smartreflex_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), .dev_attr = &smartreflex_core_dev_attr, }; @@ -4057,35 +2074,11 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { .sensor_voltdm_name = "iva", }; -static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { { .irq = 102 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { - { - .pa_start = 0x4a0db000, - .pa_end = 0x4a0db03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_iva */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_iva_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_iva_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* smartreflex_iva slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { - &omap44xx_l4_cfg__smartreflex_iva, -}; - static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .name = "smartreflex_iva", .class = &omap44xx_smartreflex_hwmod_class, @@ -4099,8 +2092,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_smartreflex_iva_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), .dev_attr = &smartreflex_iva_dev_attr, }; @@ -4109,35 +2100,11 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { .sensor_voltdm_name = "mpu", }; -static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { { .irq = 18 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { - { - .pa_start = 0x4a0d9000, - .pa_end = 0x4a0d903f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_mpu */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_mpu_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_mpu_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* smartreflex_mpu slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { - &omap44xx_l4_cfg__smartreflex_mpu, -}; - static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .name = "smartreflex_mpu", .class = &omap44xx_smartreflex_hwmod_class, @@ -4151,8 +2118,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_smartreflex_mpu_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), .dev_attr = &smartreflex_mpu_dev_attr, }; @@ -4180,30 +2145,6 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { }; /* spinlock */ -static struct omap_hwmod omap44xx_spinlock_hwmod; -static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { - { - .pa_start = 0x4a0f6000, - .pa_end = 0x4a0f6fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_spinlock_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_spinlock_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* spinlock slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { - &omap44xx_l4_cfg__spinlock, -}; - static struct omap_hwmod omap44xx_spinlock_hwmod = { .name = "spinlock", .class = &omap44xx_spinlock_hwmod_class, @@ -4214,8 +2155,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = { .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_spinlock_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), }; /* @@ -4267,35 +2206,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { }; /* timer1 */ -static struct omap_hwmod omap44xx_timer1_hwmod; static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { { .irq = 37 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { - { - .pa_start = 0x4a318000, - .pa_end = 0x4a31807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_timer1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { - &omap44xx_l4_wkup__timer1, -}; - static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, @@ -4310,40 +2225,14 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), }; /* timer2 */ -static struct omap_hwmod omap44xx_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { { .irq = 38 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { - { - .pa_start = 0x48032000, - .pa_end = 0x4803207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { - &omap44xx_l4_per__timer2, -}; - static struct omap_hwmod omap44xx_timer2_hwmod = { .name = "timer2", .class = &omap44xx_timer_1ms_hwmod_class, @@ -4358,40 +2247,14 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), }; /* timer3 */ -static struct omap_hwmod omap44xx_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { { .irq = 39 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { - { - .pa_start = 0x48034000, - .pa_end = 0x4803407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { - &omap44xx_l4_per__timer3, -}; - static struct omap_hwmod omap44xx_timer3_hwmod = { .name = "timer3", .class = &omap44xx_timer_hwmod_class, @@ -4406,40 +2269,14 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), }; /* timer4 */ -static struct omap_hwmod omap44xx_timer4_hwmod; static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { { .irq = 40 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { - { - .pa_start = 0x48036000, - .pa_end = 0x4803607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { - &omap44xx_l4_per__timer4, -}; - static struct omap_hwmod omap44xx_timer4_hwmod = { .name = "timer4", .class = &omap44xx_timer_hwmod_class, @@ -4454,59 +2291,14 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), }; /* timer5 */ -static struct omap_hwmod omap44xx_timer5_hwmod; static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { { .irq = 41 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { - { - .pa_start = 0x40138000, - .pa_end = 0x4013807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x4903807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer5 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { - &omap44xx_l4_abe__timer5, - &omap44xx_l4_abe__timer5_dma, -}; - static struct omap_hwmod omap44xx_timer5_hwmod = { .name = "timer5", .class = &omap44xx_timer_hwmod_class, @@ -4521,59 +2313,14 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), }; /* timer6 */ -static struct omap_hwmod omap44xx_timer6_hwmod; static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { { .irq = 42 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { - { - .pa_start = 0x4013a000, - .pa_end = 0x4013a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { - { - .pa_start = 0x4903a000, - .pa_end = 0x4903a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer6 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { - &omap44xx_l4_abe__timer6, - &omap44xx_l4_abe__timer6_dma, -}; - static struct omap_hwmod omap44xx_timer6_hwmod = { .name = "timer6", .class = &omap44xx_timer_hwmod_class, @@ -4589,59 +2336,14 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), }; /* timer7 */ -static struct omap_hwmod omap44xx_timer7_hwmod; static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { { .irq = 43 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { - { - .pa_start = 0x4013c000, - .pa_end = 0x4013c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { - { - .pa_start = 0x4903c000, - .pa_end = 0x4903c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer7 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { - &omap44xx_l4_abe__timer7, - &omap44xx_l4_abe__timer7_dma, -}; - static struct omap_hwmod omap44xx_timer7_hwmod = { .name = "timer7", .class = &omap44xx_timer_hwmod_class, @@ -4656,59 +2358,14 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), }; /* timer8 */ -static struct omap_hwmod omap44xx_timer8_hwmod; static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { { .irq = 44 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { - { - .pa_start = 0x4013e000, - .pa_end = 0x4013e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { - { - .pa_start = 0x4903e000, - .pa_end = 0x4903e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer8 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { - &omap44xx_l4_abe__timer8, - &omap44xx_l4_abe__timer8_dma, -}; - static struct omap_hwmod omap44xx_timer8_hwmod = { .name = "timer8", .class = &omap44xx_timer_hwmod_class, @@ -4723,40 +2380,14 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), }; /* timer9 */ -static struct omap_hwmod omap44xx_timer9_hwmod; static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { { .irq = 45 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { - { - .pa_start = 0x4803e000, - .pa_end = 0x4803e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer9_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { - &omap44xx_l4_per__timer9, -}; - static struct omap_hwmod omap44xx_timer9_hwmod = { .name = "timer9", .class = &omap44xx_timer_hwmod_class, @@ -4771,40 +2402,14 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), }; /* timer10 */ -static struct omap_hwmod omap44xx_timer10_hwmod; static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { { .irq = 46 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { - { - .pa_start = 0x48086000, - .pa_end = 0x4808607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer10 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer10_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { - &omap44xx_l4_per__timer10, -}; - static struct omap_hwmod omap44xx_timer10_hwmod = { .name = "timer10", .class = &omap44xx_timer_1ms_hwmod_class, @@ -4819,40 +2424,14 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), }; /* timer11 */ -static struct omap_hwmod omap44xx_timer11_hwmod; static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { { .irq = 47 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { - { - .pa_start = 0x48088000, - .pa_end = 0x4808807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer11 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer11_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { - &omap44xx_l4_per__timer11, -}; - static struct omap_hwmod omap44xx_timer11_hwmod = { .name = "timer11", .class = &omap44xx_timer_hwmod_class, @@ -4867,8 +2446,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), }; /* @@ -4894,7 +2471,6 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { }; /* uart1 */ -static struct omap_hwmod omap44xx_uart1_hwmod; static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { { .irq = 72 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4906,29 +2482,6 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { - { - .pa_start = 0x4806a000, - .pa_end = 0x4806a0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { - &omap44xx_l4_per__uart1, -}; - static struct omap_hwmod omap44xx_uart1_hwmod = { .name = "uart1", .class = &omap44xx_uart_hwmod_class, @@ -4943,12 +2496,9 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), }; /* uart2 */ -static struct omap_hwmod omap44xx_uart2_hwmod; static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { { .irq = 73 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4960,29 +2510,6 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { - { - .pa_start = 0x4806c000, - .pa_end = 0x4806c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { - &omap44xx_l4_per__uart2, -}; - static struct omap_hwmod omap44xx_uart2_hwmod = { .name = "uart2", .class = &omap44xx_uart_hwmod_class, @@ -4997,12 +2524,9 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), }; /* uart3 */ -static struct omap_hwmod omap44xx_uart3_hwmod; static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { { .irq = 74 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -5014,29 +2538,6 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { - { - .pa_start = 0x48020000, - .pa_end = 0x480200ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { - &omap44xx_l4_per__uart3, -}; - static struct omap_hwmod omap44xx_uart3_hwmod = { .name = "uart3", .class = &omap44xx_uart_hwmod_class, @@ -5052,12 +2553,9 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), }; /* uart4 */ -static struct omap_hwmod omap44xx_uart4_hwmod; static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { { .irq = 70 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -5069,29 +2567,6 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { - { - .pa_start = 0x4806e000, - .pa_end = 0x4806e0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { - &omap44xx_l4_per__uart4, -}; - static struct omap_hwmod omap44xx_uart4_hwmod = { .name = "uart4", .class = &omap44xx_uart_hwmod_class, @@ -5106,8 +2581,98 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), +}; + +/* + * 'usb_host_hs' class + * high-speed multi-port usb host controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap44xx_usb_host_hs_sysc, +}; + +/* usb_host_hs */ +static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, + { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap44xx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_host_hs_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .mpu_irqs = omap44xx_usb_host_hs_irqs, + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, }; /* @@ -5140,34 +2705,6 @@ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { { .irq = -1 } }; -/* usb_otg_hs master ports */ -static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { - &omap44xx_usb_otg_hs__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { - { - .pa_start = 0x4a0ab000, - .pa_end = 0x4a0ab003, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> usb_otg_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_otg_hs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_otg_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_otg_hs slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { - &omap44xx_l4_cfg__usb_otg_hs, -}; - static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { { .role = "xclk", .clk = "usb_otg_hs_xclk" }, }; @@ -5188,10 +2725,47 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { }, .opt_clks = usb_otg_hs_opt_clks, .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), - .slaves = omap44xx_usb_otg_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), - .masters = omap44xx_usb_otg_hs_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ + +static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap44xx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap44xx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap44xx_usb_tll_hs_irqs, + .main_clk = "usb_tll_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, }; /* @@ -5218,35 +2792,11 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { }; /* wd_timer2 */ -static struct omap_hwmod omap44xx_wd_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { { .irq = 80 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { - { - .pa_start = 0x4a314000, - .pa_end = 0x4a31407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_wd_timer2_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* wd_timer2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { - &omap44xx_l4_wkup__wd_timer2, -}; - static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap44xx_wd_timer_hwmod_class, @@ -5260,106 +2810,1746 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), }; /* wd_timer3 */ -static struct omap_hwmod omap44xx_wd_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { { .irq = 36 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { +static struct omap_hwmod omap44xx_wd_timer3_hwmod = { + .name = "wd_timer3", + .class = &omap44xx_wd_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .mpu_irqs = omap44xx_wd_timer3_irqs, + .main_clk = "wd_timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* + * interfaces + */ + +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { { - .pa_start = 0x40130000, - .pa_end = 0x4013007f, + .pa_start = 0x4e000000, + .pa_end = 0x4e0007ff, .flags = ADDR_TYPE_RT }, { } }; -/* l4_abe -> wd_timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { +/* mpu -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dmm_addrs, + .user = OCP_USER_MPU, +}; + +/* dmm -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { + .master = &omap44xx_dmm_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { + { + .pa_start = 0x4a20c000, + .pa_end = 0x4a20c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_emif_fw_addrs, + .user = OCP_USER_MPU, +}; + +/* iva -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { + .master = &omap44xx_l3_main_3_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { + .master = &omap44xx_dss_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { + .master = &omap44xx_mmc1_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { + .master = &omap44xx_mmc2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { + { + .pa_start = 0x44000000, + .pa_end = 0x44000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_1_addrs, + .user = OCP_USER_MPU, +}; + +/* dma_system -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { + .master = &omap44xx_dma_system_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* hsi -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { + .master = &omap44xx_hsi_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { + .master = &omap44xx_ipu_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iss -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { + .master = &omap44xx_iss_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iva -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { + { + .pa_start = 0x44800000, + .pa_end = 0x44801fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_2_addrs, + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_host_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { + .master = &omap44xx_usb_host_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_otg_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { + .master = &omap44xx_usb_otg_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { + { + .pa_start = 0x45000000, + .pa_end = 0x45000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_3_addrs, + .user = OCP_USER_MPU, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* aess -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { + .master = &omap44xx_aess_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_cfg_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l4_per_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l4_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l4_wkup_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_mpu_private_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { + { + .pa_start = 0x401f1000, + .pa_end = 0x401f13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> aess */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, + .slave = &omap44xx_aess_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_addrs, + .addr = omap44xx_aess_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { +static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { { - .pa_start = 0x49030000, - .pa_end = 0x4903007f, + .pa_start = 0x490f1000, + .pa_end = 0x490f13ff, .flags = ADDR_TYPE_RT }, { } }; -/* l4_abe -> wd_timer3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { +/* l4_abe -> aess (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, + .slave = &omap44xx_aess_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_dma_addrs, + .addr = omap44xx_aess_dma_addrs, .user = OCP_USER_SDMA, }; -/* wd_timer3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { - &omap44xx_l4_abe__wd_timer3, - &omap44xx_l4_abe__wd_timer3_dma, +static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { + { + .pa_start = 0x4a304000, + .pa_end = 0x4a30401f, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap44xx_wd_timer3_hwmod = { - .name = "wd_timer3", - .class = &omap44xx_wd_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_wd_timer3_irqs, - .main_clk = "wd_timer3_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_counter_32k_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_counter_32k_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a056fff, + .flags = ADDR_TYPE_RT }, - .slaves = omap44xx_wd_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), + { } }; -/* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ -static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { - .master = &omap44xx_usb_host_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4012e000, + .pa_end = 0x4012e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x4902e000, + .pa_end = 0x4902e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* dsp -> iva */ +static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "dpll_iva_m5x2_ck", + .user = OCP_USER_DSP, +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dsp_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { + { + .pa_start = 0x58000000, + .pa_end = 0x5800007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { + { + .pa_start = 0x48040000, + .pa_end = 0x4804007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { + { + .pa_start = 0x58001000, + .pa_end = 0x58001fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dispc_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { + { + .pa_start = 0x48041000, + .pa_end = 0x48041fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dispc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { + { + .pa_start = 0x58004000, + .pa_end = 0x580041ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { + { + .pa_start = 0x48044000, + .pa_end = 0x480441ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi1_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { + { + .pa_start = 0x58005000, + .pa_end = 0x580051ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { + { + .pa_start = 0x48045000, + .pa_end = 0x480451ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi2_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { + { + .pa_start = 0x58006000, + .pa_end = 0x58006fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_hdmi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { + { + .pa_start = 0x48046000, + .pa_end = 0x48046fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_hdmi_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { + { + .pa_start = 0x58002000, + .pa_end = 0x580020ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_rfbi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48042000, + .pa_end = 0x480420ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_rfbi_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { + { + .pa_start = 0x58003000, + .pa_end = 0x580030ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_venc_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { + { + .pa_start = 0x48043000, + .pa_end = 0x480430ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_venc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { + { + .pa_start = 0x4a310000, + .pa_end = 0x4a3101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_gpio1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { + { + .pa_start = 0x48055000, + .pa_end = 0x480551ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { + { + .pa_start = 0x48057000, + .pa_end = 0x480571ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { + { + .pa_start = 0x48059000, + .pa_end = 0x480591ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { + { + .pa_start = 0x4805b000, + .pa_end = 0x4805b1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { + { + .pa_start = 0x4805d000, + .pa_end = 0x4805d1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio6_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { + { + .pa_start = 0x4a058000, + .pa_end = 0x4a05bfff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> hsi */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_hsi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_hsi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x480700ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x480720ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x480600ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { + { + .pa_start = 0x48350000, + .pa_end = 0x483500ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_ipu_hwmod, .clk = "l3_div_ck", .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, +static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { + { + .pa_start = 0x52000000, + .pa_end = 0x520000ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap44xx_usb_host_hs_sysc, +/* l3_main_2 -> iss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iss_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { - &omap44xx_usb_host_hs__l3_main_2, +static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { + { + .pa_start = 0x5a000000, + .pa_end = 0x5a07ffff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> iva */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iva_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { + { + .pa_start = 0x4a31c000, + .pa_end = 0x4a31c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> kbd */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_kbd_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_kbd_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { + { + .pa_start = 0x4a0f4000, + .pa_end = 0x4a0f41ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> mailbox */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mailbox_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40122000, + .pa_end = 0x401220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp1 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40124000, + .pa_end = 0x401240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40126000, + .pa_end = 0x401260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { + { + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcbsp4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { + { + .pa_start = 0x40132000, + .pa_end = 0x4013207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x4903207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480981ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { + { + .pa_start = 0x480b8000, + .pa_end = 0x480b81ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b43ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { + { + .pa_start = 0x480d1000, + .pa_end = 0x480d13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { + { + .pa_start = 0x480d5000, + .pa_end = 0x480d53ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { + { + .pa_start = 0x4a0dd000, + .pa_end = 0x4a0dd03f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { + { + .pa_start = 0x4a0db000, + .pa_end = 0x4a0db03f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_iva */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_iva_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_iva_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { + { + .pa_start = 0x4a0d9000, + .pa_end = 0x4a0d903f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_mpu */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_mpu_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_mpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { + { + .pa_start = 0x4a0f6000, + .pa_end = 0x4a0f6fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> spinlock */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_spinlock_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_spinlock_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { + { + .pa_start = 0x4a318000, + .pa_end = 0x4a31807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_timer1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { + { + .pa_start = 0x48032000, + .pa_end = 0x4803207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { + { + .pa_start = 0x48034000, + .pa_end = 0x4803407f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { + { + .pa_start = 0x48036000, + .pa_end = 0x4803607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { + { + .pa_start = 0x40138000, + .pa_end = 0x4013807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x4903807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { + { + .pa_start = 0x4013a000, + .pa_end = 0x4013a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { + { + .pa_start = 0x4903a000, + .pa_end = 0x4903a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { + { + .pa_start = 0x4013c000, + .pa_end = 0x4013c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { + { + .pa_start = 0x4903c000, + .pa_end = 0x4903c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { + { + .pa_start = 0x4013e000, + .pa_end = 0x4013e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { + { + .pa_start = 0x4903e000, + .pa_end = 0x4903e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { + { + .pa_start = 0x4803e000, + .pa_end = 0x4803e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer9_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x4808607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer10_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x4808807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer11_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { + { + .pa_start = 0x4806a000, + .pa_end = 0x4806a0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { + { + .pa_start = 0x4806c000, + .pa_end = 0x4806c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { + { + .pa_start = 0x48020000, + .pa_end = 0x480200ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { + { + .pa_start = 0x4806e000, + .pa_end = 0x4806e0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { @@ -5382,12 +4572,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { {} }; -static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, - { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - +/* l4_cfg -> usb_host_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_host_hs_hwmod, @@ -5396,100 +4581,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { - &omap44xx_l4_cfg__usb_host_hs, -}; - -static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap44xx_usb_host_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_hs_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, +static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { + { + .pa_start = 0x4a0ab000, + .pa_end = 0x4a0ab003, + .flags = ADDR_TYPE_RT }, - .mpu_irqs = omap44xx_usb_host_hs_irqs, - .slaves = omap44xx_usb_host_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), - .masters = omap44xx_usb_host_hs_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), - - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ - - /* - * During system boot; If the hwmod framework resets the module - * the module will have smart idle settings; which can lead to deadlock - * (above Errata Id:i660); so, dont reset the module during boot; - * Use HWMOD_INIT_NO_RESET. - */ - - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | - HWMOD_INIT_NO_RESET, -}; - -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ -static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap44xx_usb_tll_hs_sysc, + { } }; -static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* l4_cfg -> usb_otg_hs */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_otg_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_otg_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { @@ -5502,6 +4609,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { {} }; +/* l4_cfg -> usb_tll_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_tll_hs_hwmod, @@ -5510,181 +4618,184 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { - &omap44xx_l4_cfg__usb_tll_hs, +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { + { + .pa_start = 0x4a314000, + .pa_end = 0x4a31407f, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap44xx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_tll_hs_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_wd_timer2_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { + { + .pa_start = 0x40130000, + .pa_end = 0x4013007f, + .flags = ADDR_TYPE_RT }, - .mpu_irqs = omap44xx_usb_tll_hs_irqs, - .slaves = omap44xx_usb_tll_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), + { } +}; + +/* l4_abe -> wd_timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_addrs, + .user = OCP_USER_MPU, }; -static __initdata struct omap_hwmod *omap44xx_hwmods[] = { - - /* dmm class */ - &omap44xx_dmm_hwmod, - - /* emif_fw class */ - &omap44xx_emif_fw_hwmod, - - /* l3 class */ - &omap44xx_l3_instr_hwmod, - &omap44xx_l3_main_1_hwmod, - &omap44xx_l3_main_2_hwmod, - &omap44xx_l3_main_3_hwmod, - - /* l4 class */ - &omap44xx_l4_abe_hwmod, - &omap44xx_l4_cfg_hwmod, - &omap44xx_l4_per_hwmod, - &omap44xx_l4_wkup_hwmod, - - /* mpu_bus class */ - &omap44xx_mpu_private_hwmod, - - /* aess class */ -/* &omap44xx_aess_hwmod, */ - - /* bandgap class */ - &omap44xx_bandgap_hwmod, - - /* counter class */ -/* &omap44xx_counter_32k_hwmod, */ - - /* dma class */ - &omap44xx_dma_system_hwmod, - - /* dmic class */ - &omap44xx_dmic_hwmod, - - /* dsp class */ - &omap44xx_dsp_hwmod, - &omap44xx_dsp_c0_hwmod, - - /* dss class */ - &omap44xx_dss_hwmod, - &omap44xx_dss_dispc_hwmod, - &omap44xx_dss_dsi1_hwmod, - &omap44xx_dss_dsi2_hwmod, - &omap44xx_dss_hdmi_hwmod, - &omap44xx_dss_rfbi_hwmod, - &omap44xx_dss_venc_hwmod, - - /* gpio class */ - &omap44xx_gpio1_hwmod, - &omap44xx_gpio2_hwmod, - &omap44xx_gpio3_hwmod, - &omap44xx_gpio4_hwmod, - &omap44xx_gpio5_hwmod, - &omap44xx_gpio6_hwmod, - - /* hsi class */ -/* &omap44xx_hsi_hwmod, */ - - /* i2c class */ - &omap44xx_i2c1_hwmod, - &omap44xx_i2c2_hwmod, - &omap44xx_i2c3_hwmod, - &omap44xx_i2c4_hwmod, - - /* ipu class */ - &omap44xx_ipu_hwmod, - &omap44xx_ipu_c0_hwmod, - &omap44xx_ipu_c1_hwmod, - - /* iss class */ -/* &omap44xx_iss_hwmod, */ - - /* iva class */ - &omap44xx_iva_hwmod, - &omap44xx_iva_seq0_hwmod, - &omap44xx_iva_seq1_hwmod, - - /* kbd class */ - &omap44xx_kbd_hwmod, - - /* mailbox class */ - &omap44xx_mailbox_hwmod, - - /* mcbsp class */ - &omap44xx_mcbsp1_hwmod, - &omap44xx_mcbsp2_hwmod, - &omap44xx_mcbsp3_hwmod, - &omap44xx_mcbsp4_hwmod, - - /* mcpdm class */ - &omap44xx_mcpdm_hwmod, - - /* mcspi class */ - &omap44xx_mcspi1_hwmod, - &omap44xx_mcspi2_hwmod, - &omap44xx_mcspi3_hwmod, - &omap44xx_mcspi4_hwmod, - - /* mmc class */ - &omap44xx_mmc1_hwmod, - &omap44xx_mmc2_hwmod, - &omap44xx_mmc3_hwmod, - &omap44xx_mmc4_hwmod, - &omap44xx_mmc5_hwmod, - - /* mpu class */ - &omap44xx_mpu_hwmod, - - /* smartreflex class */ - &omap44xx_smartreflex_core_hwmod, - &omap44xx_smartreflex_iva_hwmod, - &omap44xx_smartreflex_mpu_hwmod, - - /* spinlock class */ - &omap44xx_spinlock_hwmod, - - /* timer class */ - &omap44xx_timer1_hwmod, - &omap44xx_timer2_hwmod, - &omap44xx_timer3_hwmod, - &omap44xx_timer4_hwmod, - &omap44xx_timer5_hwmod, - &omap44xx_timer6_hwmod, - &omap44xx_timer7_hwmod, - &omap44xx_timer8_hwmod, - &omap44xx_timer9_hwmod, - &omap44xx_timer10_hwmod, - &omap44xx_timer11_hwmod, - - /* uart class */ - &omap44xx_uart1_hwmod, - &omap44xx_uart2_hwmod, - &omap44xx_uart3_hwmod, - &omap44xx_uart4_hwmod, - - /* usb host class */ - &omap44xx_usb_host_hs_hwmod, - &omap44xx_usb_tll_hs_hwmod, - - /* usb_otg_hs class */ - &omap44xx_usb_otg_hs_hwmod, - - /* wd_timer class */ - &omap44xx_wd_timer2_hwmod, - &omap44xx_wd_timer3_hwmod, +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { + { + .pa_start = 0x49030000, + .pa_end = 0x4903007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> wd_timer3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { + &omap44xx_l3_main_1__dmm, + &omap44xx_mpu__dmm, + &omap44xx_dmm__emif_fw, + &omap44xx_l4_cfg__emif_fw, + &omap44xx_iva__l3_instr, + &omap44xx_l3_main_3__l3_instr, + &omap44xx_dsp__l3_main_1, + &omap44xx_dss__l3_main_1, + &omap44xx_l3_main_2__l3_main_1, + &omap44xx_l4_cfg__l3_main_1, + &omap44xx_mmc1__l3_main_1, + &omap44xx_mmc2__l3_main_1, + &omap44xx_mpu__l3_main_1, + &omap44xx_dma_system__l3_main_2, + &omap44xx_hsi__l3_main_2, + &omap44xx_ipu__l3_main_2, + &omap44xx_iss__l3_main_2, + &omap44xx_iva__l3_main_2, + &omap44xx_l3_main_1__l3_main_2, + &omap44xx_l4_cfg__l3_main_2, + &omap44xx_usb_host_hs__l3_main_2, + &omap44xx_usb_otg_hs__l3_main_2, + &omap44xx_l3_main_1__l3_main_3, + &omap44xx_l3_main_2__l3_main_3, + &omap44xx_l4_cfg__l3_main_3, + &omap44xx_aess__l4_abe, + &omap44xx_dsp__l4_abe, + &omap44xx_l3_main_1__l4_abe, + &omap44xx_mpu__l4_abe, + &omap44xx_l3_main_1__l4_cfg, + &omap44xx_l3_main_2__l4_per, + &omap44xx_l4_cfg__l4_wkup, + &omap44xx_mpu__mpu_private, + &omap44xx_l4_abe__aess, + &omap44xx_l4_abe__aess_dma, + &omap44xx_l4_wkup__counter_32k, + &omap44xx_l4_cfg__dma_system, + &omap44xx_l4_abe__dmic, + &omap44xx_l4_abe__dmic_dma, + &omap44xx_dsp__iva, + &omap44xx_l4_cfg__dsp, + &omap44xx_l3_main_2__dss, + &omap44xx_l4_per__dss, + &omap44xx_l3_main_2__dss_dispc, + &omap44xx_l4_per__dss_dispc, + &omap44xx_l3_main_2__dss_dsi1, + &omap44xx_l4_per__dss_dsi1, + &omap44xx_l3_main_2__dss_dsi2, + &omap44xx_l4_per__dss_dsi2, + &omap44xx_l3_main_2__dss_hdmi, + &omap44xx_l4_per__dss_hdmi, + &omap44xx_l3_main_2__dss_rfbi, + &omap44xx_l4_per__dss_rfbi, + &omap44xx_l3_main_2__dss_venc, + &omap44xx_l4_per__dss_venc, + &omap44xx_l4_wkup__gpio1, + &omap44xx_l4_per__gpio2, + &omap44xx_l4_per__gpio3, + &omap44xx_l4_per__gpio4, + &omap44xx_l4_per__gpio5, + &omap44xx_l4_per__gpio6, + &omap44xx_l4_cfg__hsi, + &omap44xx_l4_per__i2c1, + &omap44xx_l4_per__i2c2, + &omap44xx_l4_per__i2c3, + &omap44xx_l4_per__i2c4, + &omap44xx_l3_main_2__ipu, + &omap44xx_l3_main_2__iss, + &omap44xx_l3_main_2__iva, + &omap44xx_l4_wkup__kbd, + &omap44xx_l4_cfg__mailbox, + &omap44xx_l4_abe__mcbsp1, + &omap44xx_l4_abe__mcbsp1_dma, + &omap44xx_l4_abe__mcbsp2, + &omap44xx_l4_abe__mcbsp2_dma, + &omap44xx_l4_abe__mcbsp3, + &omap44xx_l4_abe__mcbsp3_dma, + &omap44xx_l4_per__mcbsp4, + &omap44xx_l4_abe__mcpdm, + &omap44xx_l4_abe__mcpdm_dma, + &omap44xx_l4_per__mcspi1, + &omap44xx_l4_per__mcspi2, + &omap44xx_l4_per__mcspi3, + &omap44xx_l4_per__mcspi4, + &omap44xx_l4_per__mmc1, + &omap44xx_l4_per__mmc2, + &omap44xx_l4_per__mmc3, + &omap44xx_l4_per__mmc4, + &omap44xx_l4_per__mmc5, + &omap44xx_l4_cfg__smartreflex_core, + &omap44xx_l4_cfg__smartreflex_iva, + &omap44xx_l4_cfg__smartreflex_mpu, + &omap44xx_l4_cfg__spinlock, + &omap44xx_l4_wkup__timer1, + &omap44xx_l4_per__timer2, + &omap44xx_l4_per__timer3, + &omap44xx_l4_per__timer4, + &omap44xx_l4_abe__timer5, + &omap44xx_l4_abe__timer5_dma, + &omap44xx_l4_abe__timer6, + &omap44xx_l4_abe__timer6_dma, + &omap44xx_l4_abe__timer7, + &omap44xx_l4_abe__timer7_dma, + &omap44xx_l4_abe__timer8, + &omap44xx_l4_abe__timer8_dma, + &omap44xx_l4_per__timer9, + &omap44xx_l4_per__timer10, + &omap44xx_l4_per__timer11, + &omap44xx_l4_per__uart1, + &omap44xx_l4_per__uart2, + &omap44xx_l4_per__uart3, + &omap44xx_l4_per__uart4, + &omap44xx_l4_cfg__usb_host_hs, + &omap44xx_l4_cfg__usb_otg_hs, + &omap44xx_l4_cfg__usb_tll_hs, + &omap44xx_l4_wkup__wd_timer2, + &omap44xx_l4_abe__wd_timer3, + &omap44xx_l4_abe__wd_timer3_dma, NULL, }; int __init omap44xx_hwmod_init(void) { - return omap_hwmod_register(omap44xx_hwmods); + return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index ad5d8f04c0b8..7aa9156d50ab 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -19,18 +19,6 @@ #include "display.h" /* Common address space across OMAP2xxx */ -extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[]; -extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[]; -extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[]; -extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[]; /* Common address space across OMAP2xxx/3xxx */ @@ -54,6 +42,64 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; /* Common IP block data across OMAP2xxx */ extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[]; +extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; +extern struct omap_hwmod omap2xxx_l3_main_hwmod; +extern struct omap_hwmod omap2xxx_l4_core_hwmod; +extern struct omap_hwmod omap2xxx_l4_wkup_hwmod; +extern struct omap_hwmod omap2xxx_mpu_hwmod; +extern struct omap_hwmod omap2xxx_iva_hwmod; +extern struct omap_hwmod omap2xxx_timer1_hwmod; +extern struct omap_hwmod omap2xxx_timer2_hwmod; +extern struct omap_hwmod omap2xxx_timer3_hwmod; +extern struct omap_hwmod omap2xxx_timer4_hwmod; +extern struct omap_hwmod omap2xxx_timer5_hwmod; +extern struct omap_hwmod omap2xxx_timer6_hwmod; +extern struct omap_hwmod omap2xxx_timer7_hwmod; +extern struct omap_hwmod omap2xxx_timer8_hwmod; +extern struct omap_hwmod omap2xxx_timer9_hwmod; +extern struct omap_hwmod omap2xxx_timer10_hwmod; +extern struct omap_hwmod omap2xxx_timer11_hwmod; +extern struct omap_hwmod omap2xxx_timer12_hwmod; +extern struct omap_hwmod omap2xxx_wd_timer2_hwmod; +extern struct omap_hwmod omap2xxx_uart1_hwmod; +extern struct omap_hwmod omap2xxx_uart2_hwmod; +extern struct omap_hwmod omap2xxx_uart3_hwmod; +extern struct omap_hwmod omap2xxx_dss_core_hwmod; +extern struct omap_hwmod omap2xxx_dss_dispc_hwmod; +extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod; +extern struct omap_hwmod omap2xxx_dss_venc_hwmod; +extern struct omap_hwmod omap2xxx_gpio1_hwmod; +extern struct omap_hwmod omap2xxx_gpio2_hwmod; +extern struct omap_hwmod omap2xxx_gpio3_hwmod; +extern struct omap_hwmod omap2xxx_gpio4_hwmod; +extern struct omap_hwmod omap2xxx_mcspi1_hwmod; +extern struct omap_hwmod omap2xxx_mcspi2_hwmod; + +/* Common interface data across OMAP2xxx */ +extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; +extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main; +extern struct omap_hwmod_ocp_if omap2xxx_dss__l3; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup; +extern struct omap_hwmod_ocp_if omap2_l4_core__uart1; +extern struct omap_hwmod_ocp_if omap2_l4_core__uart2; +extern struct omap_hwmod_ocp_if omap2_l4_core__uart3; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; /* Common IP block data */ extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; @@ -94,6 +140,7 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[]; extern struct omap_hwmod_irq_info omap2_dma_system_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; /* OMAP hwmod classes - forward declarations */ extern struct omap_hwmod_class l3_hwmod_class; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 36fa90b6ece8..78564895e914 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -38,27 +38,6 @@ static inline int omap4_opp_init(void) } #endif -/* - * cpuidle mach specific parameters - * - * The board code can override the default C-states definition using - * omap3_pm_init_cpuidle - */ -struct cpuidle_params { - u32 exit_latency; /* exit_latency = sleep + wake-up latencies */ - u32 target_residency; - u8 valid; /* validates the C-state */ -}; - -#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE) -extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params); -#else -static -inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) -{ -} -#endif - extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 95442b69ae27..facfffca9eac 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -171,8 +171,6 @@ static int omap2_allow_mpu_retention(void) static void omap2_enter_mpu_retention(void) { - int only_idle = 0; - /* Putting MPU into the WFI state while a transfer is active * seems to cause the I2C block to timeout. Why? Good question. */ if (omap2_i2c_active()) @@ -195,7 +193,6 @@ static void omap2_enter_mpu_retention(void) omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); - only_idle = 1; } omap2_sram_idle(); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 703bd1099259..8b43aefba0ea 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -273,7 +273,7 @@ void omap_sram_idle(void) int per_next_state = PWRDM_POWER_ON; int core_next_state = PWRDM_POWER_ON; int per_going_off; - int core_prev_state, per_prev_state; + int core_prev_state; u32 sdrc_pwr = 0; mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); @@ -375,10 +375,8 @@ void omap_sram_idle(void) pwrdm_post_transition(); /* PER */ - if (per_next_state < PWRDM_POWER_ON) { - per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); + if (per_next_state < PWRDM_POWER_ON) omap2_gpio_resume_after_idle(); - } /* Disable IO-PAD and IO-CHAIN wakeup */ if (omap3_has_io_wakeup() && @@ -702,7 +700,7 @@ static void __init pm_errata_configure(void) static int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; - struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; + struct clockdomain *neon_clkdm, *mpu_clkdm; int ret; if (!cpu_is_omap34xx()) @@ -757,8 +755,6 @@ static int __init omap3_pm_init(void) neon_clkdm = clkdm_lookup("neon_clkdm"); mpu_clkdm = clkdm_lookup("mpu_clkdm"); - per_clkdm = clkdm_lookup("per_clkdm"); - core_clkdm = clkdm_lookup("core_clkdm"); #ifdef CONFIG_SUSPEND omap_pm_suspend = omap3_pm_suspend; diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index d28f848897d6..dfe00ddb5c60 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -237,7 +237,7 @@ void omap_prcm_irq_complete(void) */ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) { - int nr_regs = irq_setup->nr_regs; + int nr_regs; u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; int offset, i; struct irq_chip_generic *gc; @@ -246,6 +246,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) if (!irq_setup) return -EINVAL; + nr_regs = irq_setup->nr_regs; + if (prcm_irq_setup) { pr_err("PRCM: already initialized; won't reinitialize\n"); return -EINVAL; diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 9fc2f44188cb..678dd1d612e5 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -133,7 +133,7 @@ static void omap_serial_fill_default_pads(struct omap_board_data *bdata) static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} #endif -char *cmdline_find_option(char *str) +static char *cmdline_find_option(char *str) { extern char *saved_command_line; diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index c512bac69ec5..ecec873e78cd 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ struct omap_hwmod *oh; + struct resource irq_rsrc, mem_rsrc; size_t size; int res = 0; + int r; sprintf(name, "timer%d", gptimer_id); omap_hwmod_setup_one(name); @@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (!oh) return -ENODEV; - timer->irq = oh->mpu_irqs[0].irq; - timer->phys_base = oh->slaves[0]->addr->pa_start; - size = oh->slaves[0]->addr->pa_end - timer->phys_base; + r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); + if (r) + return -ENXIO; + timer->irq = irq_rsrc.start; + + r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); + if (r) + return -ENXIO; + timer->phys_base = mem_rsrc.start; + size = mem_rsrc.end - mem_rsrc.start; /* Static mapping, never released */ timer->io_base = ioremap(timer->phys_base, size); diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 994d8f591a1d..db84a46ce7fd 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps) tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps; if (tmp > 4) return -ERANGE; - if (tmp <= 0) + if (tmp == 0) tmp = 1; t.page_burst_access = (fclk_ps * tmp) / 1000; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 6604fc6ca58a..0673f0c10432 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -86,7 +86,6 @@ config MACH_WRT350N_V2 config MACH_TS78XX bool "Technologic Systems TS-78xx" - select PM help Say 'Y' here if you want your kernel to support the Technologic Systems TS-78xx platform. diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 3638e5c12b7e..eaac83d1df6f 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -76,7 +76,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, /* * Description of the windows needed by the platform code */ -static struct __initdata orion_addr_map_cfg addr_map_cfg = { +static struct orion_addr_map_cfg addr_map_cfg __initdata = { .num_wins = 8, .cpu_win_can_remap = cpu_win_can_remap, .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 24481666d2cd..e2e9db492d0c 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -205,7 +205,7 @@ int __init orion5x_find_tclk(void) return 166666667; } -static void orion5x_timer_init(void) +static void __init orion5x_timer_init(void) { orion5x_tclk = orion5x_find_tclk(); diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 2e6454c8d4ba..31bab92ce038 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -45,6 +45,7 @@ void orion5x_restart(char, const char *); */ struct pci_bus; struct pci_sys_data; +struct pci_dev; void orion5x_pcie_id(u32 *dev, u32 *rev); void orion5x_pci_disable(void); diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index e52108c9aaea..49a3fd630313 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -265,7 +265,6 @@ static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci db88f5281_pci __initdata = { .nr_controllers = 2, .preinit = db88f5281_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = db88f5281_pci_map_irq, diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index c3ed15b8ea25..8c06ccac44c2 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -86,7 +86,6 @@ static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci dns323_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = dns323_pci_map_irq, diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 47587b832842..1e458efafb9a 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -138,7 +138,6 @@ static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci kurobox_pro_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = kurobox_pro_pci_map_irq, diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h index eac68978a2c2..db70e79a1198 100644 --- a/arch/arm/mach-orion5x/mpp.h +++ b/arch/arm/mach-orion5x/mpp.h @@ -65,8 +65,8 @@ #define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1) #define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1) -#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1) +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1, 1, 1) +#define MPP9_GIGE MPP(9, 0x1, 0, 0, 1, 1, 1) #define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1) #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1) diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 65faaa34de61..1c16d045333e 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -89,7 +89,6 @@ static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci mss2_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = mss2_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 292038fc59fd..78a6a11d8216 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -149,7 +149,6 @@ rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci rd88f5181l_fxo_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5181l_fxo_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index c44eabaabc16..2f5dc54cd4cd 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -161,7 +161,6 @@ rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci rd88f5181l_ge_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5181l_ge_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index e3ce61711478..399130fac0b6 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -200,7 +200,6 @@ static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci rd88f5182_pci __initdata = { .nr_controllers = 2, .preinit = rd88f5182_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5182_pci_map_irq, diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index 2c5fab00d205..e91bf0ba4e8e 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -102,7 +102,6 @@ static void __init rd88f6183ap_ge_init(void) static struct hw_pci rd88f6183ap_ge_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = orion5x_pci_map_irq, diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 632a861ef82b..90e571dc4deb 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -122,7 +122,6 @@ static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci tsp2_pci __initdata = { .nr_controllers = 2, .preinit = tsp2_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = tsp2_pci_map_irq, diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 5d6408745582..b184f680e0db 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -170,7 +170,6 @@ static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci qnap_ts209_pci __initdata = { .nr_controllers = 2, .preinit = qnap_ts209_pci_preinit, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts209_pci_map_irq, diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 4e6ff759cd32..a5c2e64c4ece 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -140,7 +140,6 @@ static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci qnap_ts409_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts409_pci_map_irq, diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h index 151e89e1e676..97c393d39ae2 100644 --- a/arch/arm/mach-orion5x/ts78xx-fpga.h +++ b/arch/arm/mach-orion5x/ts78xx-fpga.h @@ -28,9 +28,9 @@ struct fpga_device { struct fpga_devices { /* Technologic Systems */ - struct fpga_device ts_rtc; - struct fpga_device ts_nand; - struct fpga_device ts_rng; + struct fpga_device ts_rtc; + struct fpga_device ts_nand; + struct fpga_device ts_rng; }; struct ts78xx_fpga_data { diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index c96f37472eda..a74f3cf54cc5 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -8,6 +8,8 @@ * warranty of any kind, whether express or implied. */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include <linux/kernel.h> #include <linux/init.h> #include <linux/sysfs.h> @@ -115,7 +117,7 @@ static struct platform_device ts78xx_ts_rtc_device = { * I've used the method TS use in their rtc7800.c example for the detection * * TODO: track down a guinea pig without an RTC to see if we can work out a - * better RTC detection routine + * better RTC detection routine */ static int ts78xx_ts_rtc_load(void) { @@ -141,10 +143,14 @@ static int ts78xx_ts_rtc_load(void) } else rc = platform_device_add(&ts78xx_ts_rtc_device); + if (rc) + pr_info("RTC could not be registered: %d\n", + rc); return rc; } } + pr_info("RTC not found\n"); return -ENODEV; }; @@ -292,11 +298,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = { }, }; -static struct resource ts78xx_ts_nand_resources = { - .start = TS_NAND_DATA, - .end = TS_NAND_DATA + 4, - .flags = IORESOURCE_MEM, -}; +static struct resource ts78xx_ts_nand_resources + = DEFINE_RES_MEM(TS_NAND_DATA, 4); static struct platform_device ts78xx_ts_nand_device = { .name = "gen_nand", @@ -319,6 +322,8 @@ static int ts78xx_ts_nand_load(void) } else rc = platform_device_add(&ts78xx_ts_nand_device); + if (rc) + pr_info("NAND could not be registered: %d\n", rc); return rc; }; @@ -332,11 +337,8 @@ static void ts78xx_ts_nand_unload(void) ****************************************************************************/ #define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044) -static struct resource ts78xx_ts_rng_resource = { - .flags = IORESOURCE_MEM, - .start = TS_RNG_DATA, - .end = TS_RNG_DATA + 4 - 1, -}; +static struct resource ts78xx_ts_rng_resource + = DEFINE_RES_MEM(TS_RNG_DATA, 4); static struct timeriomem_rng_data ts78xx_ts_rng_data = { .period = 1000000, /* one second */ @@ -363,6 +365,8 @@ static int ts78xx_ts_rng_load(void) } else rc = platform_device_add(&ts78xx_ts_rng_device); + if (rc) + pr_info("RNG could not be registered: %d\n", rc); return rc; }; @@ -402,7 +406,7 @@ static void ts78xx_fpga_supports(void) /* enable devices if magic matches */ switch ((ts78xx_fpga.id >> 8) & 0xffffff) { case TS7800_FPGA_MAGIC: - pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n", + pr_warning("unrecognised FPGA revision 0x%.2x\n", ts78xx_fpga.id & 0xff); ts78xx_fpga.supports.ts_rtc.present = 1; ts78xx_fpga.supports.ts_nand.present = 1; @@ -422,26 +426,20 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_rtc.present == 1) { tmp = ts78xx_ts_rtc_load(); - if (tmp) { - pr_info("TS-78xx: RTC not registered\n"); + if (tmp) ts78xx_fpga.supports.ts_rtc.present = 0; - } ret |= tmp; } if (ts78xx_fpga.supports.ts_nand.present == 1) { tmp = ts78xx_ts_nand_load(); - if (tmp) { - pr_info("TS-78xx: NAND not registered\n"); + if (tmp) ts78xx_fpga.supports.ts_nand.present = 0; - } ret |= tmp; } if (ts78xx_fpga.supports.ts_rng.present == 1) { tmp = ts78xx_ts_rng_load(); - if (tmp) { - pr_info("TS-78xx: RNG not registered\n"); + if (tmp) ts78xx_fpga.supports.ts_rng.present = 0; - } ret |= tmp; } @@ -466,7 +464,7 @@ static int ts78xx_fpga_load(void) { ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); - pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", + pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff); @@ -494,7 +492,7 @@ static int ts78xx_fpga_unload(void) * UrJTAG SVN since r1381 can be used to reprogram the FPGA */ if (ts78xx_fpga.id != fpga_id) { - pr_err("TS-78xx FPGA: magic/rev mismatch\n" + pr_err("FPGA magic/rev mismatch\n" "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); @@ -525,7 +523,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, int value, ret; if (ts78xx_fpga.state < 0) { - pr_err("TS-78xx FPGA: borked, you must powercycle asap\n"); + pr_err("FPGA borked, you must powercycle ASAP\n"); return -EBUSY; } @@ -533,10 +531,8 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, value = 1; else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) value = 0; - else { - pr_err("ts78xx_fpga_store: Invalid value\n"); + else return -EINVAL; - } if (ts78xx_fpga.state == value) return n; @@ -614,7 +610,7 @@ static void __init ts78xx_init(void) /* FPGA init */ ts78xx_fpga_devices_zero_init(); ret = ts78xx_fpga_load(); - ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); + ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr); if (ret) pr_err("sysfs_create_file failed: %d\n", ret); } diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 078c03f7cd52..754c12b6abf0 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -155,7 +155,6 @@ static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci wnr854t_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = wnr854t_pci_map_irq, diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index 46a9778171ce..45c21251eb1e 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -243,7 +243,6 @@ static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot, static struct hw_pci wrt350n_v2_pci __initdata = { .nr_controllers = 2, - .swizzle = pci_std_swizzle, .setup = orion5x_pci_sys_setup, .scan = orion5x_pci_sys_scan_bus, .map_irq = wrt350n_v2_pci_map_irq, diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c index 37c2de9b6f26..a7b9415d30f8 100644 --- a/arch/arm/mach-prima2/irq.c +++ b/arch/arm/mach-prima2/irq.c @@ -42,7 +42,8 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) static __init void sirfsoc_irq_init(void) { sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32); - sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32); + sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, + SIRFSOC_INTENAL_IRQ_END + 1 - 32); writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); @@ -68,7 +69,8 @@ void __init sirfsoc_of_irq_init(void) if (!sirfsoc_intc_base) panic("unable to map intc cpu registers\n"); - irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops, NULL); + irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0, + &irq_domain_simple_ops, NULL); of_node_put(np); diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index ebd9259f5ac9..d8f816c24a2f 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -181,11 +181,10 @@ static void cmx2xx_pci_preinit(void) } static struct hw_pci cmx2xx_pci __initdata = { - .swizzle = pci_std_swizzle, .map_irq = cmx2xx_pci_map_irq, .nr_controllers = 1, + .ops = &it8152_ops, .setup = it8152_pci_setup, - .scan = it8152_pci_scan_bus, .preinit = cmx2xx_pci_preinit, }; diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c index 298ececfa366..ba02cf8d80a2 100644 --- a/arch/arm/mach-s3c24xx/bast-ide.c +++ b/arch/arm/mach-s3c24xx/bast-ide.c @@ -37,21 +37,9 @@ static struct pata_platform_info bast_ide_platdata = { #define IDE_CS S3C2410_CS5 static struct resource bast_ide0_resource[] = { - [0] = { - .start = IDE_CS + BAST_PA_IDEPRI, - .end = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) , - .end = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_IDE0, - .end = IRQ_IDE0, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20), + [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20), + [2] = DEFINE_RES_IRQ(IRQ_IDE0), }; static struct platform_device bast_device_ide0 = { @@ -67,21 +55,9 @@ static struct platform_device bast_device_ide0 = { }; static struct resource bast_ide1_resource[] = { - [0] = { - .start = IDE_CS + BAST_PA_IDESEC, - .end = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), - .end = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_IDE1, - .end = IRQ_IDE1, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20), + [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20), + [2] = DEFINE_RES_IRQ(IRQ_IDE1), }; static struct platform_device bast_device_ide1 = { diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c index 4220cc60de3c..ea2c4b003d58 100644 --- a/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c @@ -65,13 +65,8 @@ #include "common.h" -static struct resource amlm5900_nor_resource = { - .start = 0x00000000, - .end = 0x01000000 - 1, - .flags = IORESOURCE_MEM, -}; - - +static struct resource amlm5900_nor_resource = + DEFINE_RES_MEM(0x00000000, SZ_16M); static struct mtd_partition amlm5900_mtd_partitions[] = { { diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c index 60c72c54c21e..5a7d0c0010f7 100644 --- a/arch/arm/mach-s3c24xx/mach-anubis.c +++ b/arch/arm/mach-s3c24xx/mach-anubis.c @@ -235,19 +235,9 @@ static struct pata_platform_info anubis_ide_platdata = { }; static struct resource anubis_ide0_resource[] = { - { - .start = S3C2410_CS3, - .end = S3C2410_CS3 + (8*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = S3C2410_CS3 + (1<<26) + (6*32), - .end = S3C2410_CS3 + (1<<26) + (7*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_IDE0, - .end = IRQ_IDE0, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32), + [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32), + [3] = DEFINE_RES_IRQ(IRQ_IDE0), }; static struct platform_device anubis_device_ide0 = { @@ -262,19 +252,9 @@ static struct platform_device anubis_device_ide0 = { }; static struct resource anubis_ide1_resource[] = { - { - .start = S3C2410_CS4, - .end = S3C2410_CS4 + (8*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = S3C2410_CS4 + (1<<26) + (6*32), - .end = S3C2410_CS4 + (1<<26) + (7*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_IDE0, - .end = IRQ_IDE0, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32), + [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32), + [2] = DEFINE_RES_IRQ(IRQ_IDE0), }; static struct platform_device anubis_device_ide1 = { @@ -298,16 +278,8 @@ static struct ax_plat_data anubis_asix_platdata = { }; static struct resource anubis_asix_resource[] = { - [0] = { - .start = S3C2410_CS5, - .end = S3C2410_CS5 + (0x20 * 0x20) -1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = IRQ_ASIX, - .end = IRQ_ASIX, - .flags = IORESOURCE_IRQ - } + [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20), + [1] = DEFINE_RES_IRQ(IRQ_ASIX), }; static struct platform_device anubis_device_asix = { @@ -323,21 +295,9 @@ static struct platform_device anubis_device_asix = { /* SM501 */ static struct resource anubis_sm501_resource[] = { - [0] = { - .start = S3C2410_CS2, - .end = S3C2410_CS2 + SZ_8M, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C2410_CS2 + SZ_64M - SZ_2M, - .end = S3C2410_CS2 + SZ_64M - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_EINT0, - .end = IRQ_EINT0, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M), + [1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M), + [2] = DEFINE_RES_IRQ(IRQ_EINT0), }; static struct sm501_initdata anubis_sm501_initdata = { diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c index d7ae49c90118..7a05abf1270b 100644 --- a/arch/arm/mach-s3c24xx/mach-at2440evb.c +++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c @@ -118,21 +118,10 @@ static struct s3c2410_platform_nand __initdata at2440evb_nand_info = { /* DM9000AEP 10/100 ethernet controller */ static struct resource at2440evb_dm9k_resource[] = { - [0] = { - .start = S3C2410_CS3, - .end = S3C2410_CS3 + 3, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C2410_CS3 + 4, - .end = S3C2410_CS3 + 7, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = IRQ_EINT7, - .end = IRQ_EINT7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - } + [0] = DEFINE_RES_MEM(S3C2410_CS3, 4), + [1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4), + [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHEDGE), }; static struct dm9000_plat_data at2440evb_dm9k_pdata = { diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c index 53219c02eca0..1cf1720682d3 100644 --- a/arch/arm/mach-s3c24xx/mach-bast.c +++ b/arch/arm/mach-s3c24xx/mach-bast.c @@ -310,22 +310,10 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = { /* DM9000 */ static struct resource bast_dm9k_resource[] = { - [0] = { - .start = S3C2410_CS5 + BAST_PA_DM9000, - .end = S3C2410_CS5 + BAST_PA_DM9000 + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40, - .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_DM9000, - .end = IRQ_DM9000, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - } - + [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4), + [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40), + [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), }; /* for the moment we limit ourselves to 16bit IO until some @@ -400,21 +388,9 @@ static struct ax_plat_data bast_asix_platdata = { }; static struct resource bast_asix_resource[] = { - [0] = { - .start = S3C2410_CS5 + BAST_PA_ASIXNET, - .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), - .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_ASIX, - .end = IRQ_ASIX, - .flags = IORESOURCE_IRQ - } + [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20), + [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1), + [2] = DEFINE_RES_IRQ(IRQ_ASIX), }; static struct platform_device bast_device_asix = { @@ -430,11 +406,8 @@ static struct platform_device bast_device_asix = { /* Asix AX88796 10/100 ethernet controller parallel port */ static struct resource bast_asixpp_resource[] = { - [0] = { - .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), - .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1, - .flags = IORESOURCE_MEM, - } + [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \ + 0x30 * 0x20), }; static struct platform_device bast_device_axpp = { diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c index ba5d85394105..0f29f64a3eeb 100644 --- a/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/arch/arm/mach-s3c24xx/mach-gta02.c @@ -387,11 +387,8 @@ static struct physmap_flash_data gta02_nor_flash_data = { .width = 2, }; -static struct resource gta02_nor_flash_resource = { - .start = GTA02_FLASH_BASE, - .end = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource gta02_nor_flash_resource = + DEFINE_RES_MEM(GTA02_FLASH_BASE, GTA02_FLASH_SIZE); static struct platform_device gta02_nor_flash = { .name = "physmap-flash", diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index 6b21ba107eab..bb8d008d5a5c 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c @@ -253,13 +253,8 @@ static struct pda_power_pdata power_supply_info = { }; static struct resource power_supply_resources[] = { - [0] = { - .name = "ac", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | - IORESOURCE_IRQ_HIGHEDGE, - .start = IRQ_EINT2, - .end = IRQ_EINT2, - }, + [0] = DEFINE_RES_NAMED(IRQ_EINT2, 1, "ac", IORESOURCE_IRQ \ + | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE), }; static struct platform_device power_supply = { diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index 5d66fb218a41..f092b188ab70 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -292,21 +292,10 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = { /* DM9000AEP 10/100 ethernet controller */ static struct resource mini2440_dm9k_resource[] = { - [0] = { - .start = MACH_MINI2440_DM9K_BASE, - .end = MACH_MINI2440_DM9K_BASE + 3, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = MACH_MINI2440_DM9K_BASE + 4, - .end = MACH_MINI2440_DM9K_BASE + 7, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = IRQ_EINT7, - .end = IRQ_EINT7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - } + [0] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE, 4), + [1] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE + 4, 4), + [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHEDGE), }; /* diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c index 5198e3e1c5be..5c05ba1c330f 100644 --- a/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c @@ -84,11 +84,7 @@ static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = { /* NOR Flash on NexVision NexCoder 2440 board */ static struct resource nexcoder_nor_resource[] = { - [0] = { - .start = S3C2410_CS0, - .end = S3C2410_CS0 + (8*1024*1024) - 1, - .flags = IORESOURCE_MEM, - } + [0] = DEFINE_RES_MEM(S3C2410_CS0, SZ_8M), }; static struct map_info nexcoder_nor_map = { diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c index c5daeb612a88..95d077255024 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/arch/arm/mach-s3c24xx/mach-osiris.c @@ -244,16 +244,8 @@ static struct s3c2410_platform_nand __initdata osiris_nand_info = { /* PCMCIA control and configuration */ static struct resource osiris_pcmcia_resource[] = { - [0] = { - .start = 0x0f000000, - .end = 0x0f100000, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x0c000000, - .end = 0x0c100000, - .flags = IORESOURCE_MEM, - } + [0] = DEFINE_RES_MEM(0x0f000000, SZ_1M), + [1] = DEFINE_RES_MEM(0x0c000000, SZ_1M), }; static struct platform_device osiris_pcmcia = { diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c index 5f1e0eeb38a9..bc4b6efb3b27 100644 --- a/arch/arm/mach-s3c24xx/mach-otom.c +++ b/arch/arm/mach-s3c24xx/mach-otom.c @@ -77,11 +77,7 @@ static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = { /* NOR Flash on NexVision OTOM board */ static struct resource otom_nor_resource[] = { - [0] = { - .start = S3C2410_CS0, - .end = S3C2410_CS0 + (4*1024*1024) - 1, - .flags = IORESOURCE_MEM, - } + [0] = DEFINE_RES_MEM(S3C2410_CS0, SZ_4M), }; static struct platform_device otom_device_nor = { diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index 91c16d9d2459..b868dddcb836 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c @@ -180,16 +180,8 @@ static struct s3c2410fb_mach_info qt2410_fb_info __initdata = { /* CS8900 */ static struct resource qt2410_cs89x0_resources[] = { - [0] = { - .start = 0x19000000, - .end = 0x19000000 + 16, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_EINT9, - .end = IRQ_EINT9, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(0x19000000, 17), + [1] = DEFINE_RES_IRQ(IRQ_EINT9), }; static struct platform_device qt2410_cs89x0 = { diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index 200debb4c72d..a6762aae4727 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -152,13 +152,8 @@ static struct pda_power_pdata power_supply_info = { }; static struct resource power_supply_resources[] = { - [0] = { - .name = "ac", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | - IORESOURCE_IRQ_HIGHEDGE, - .start = IRQ_EINT2, - .end = IRQ_EINT2, - }, + [0] = DEFINE_RES_NAMED(IRQ_EINT2, 1, "ac", IORESOURCE_IRQ \ + | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE), }; static struct platform_device power_supply = { diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c index 1114666f0efb..fe990289ee7d 100644 --- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c +++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c @@ -56,11 +56,8 @@ #include "common.h" -static struct resource tct_hammer_nor_resource = { - .start = 0x00000000, - .end = 0x01000000 - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource tct_hammer_nor_resource = + DEFINE_RES_MEM(0x00000000, SZ_16M); static struct mtd_partition tct_hammer_mtd_partitions[] = { { diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c index 87608d45dac4..bd5f189f0424 100644 --- a/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/arch/arm/mach-s3c24xx/mach-vr1000.c @@ -187,40 +187,17 @@ static struct platform_device serial_device = { /* DM9000 ethernet devices */ static struct resource vr1000_dm9k0_resource[] = { - [0] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 3, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = IRQ_VR1000_DM9000A, - .end = IRQ_VR1000_DM9000A, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - } - + [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4), + [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40), + [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), }; static struct resource vr1000_dm9k1_resource[] = { - [0] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = IRQ_VR1000_DM9000N, - .end = IRQ_VR1000_DM9000N, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - } + [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4), + [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40), + [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), }; /* for the moment we limit ourselves to 16bit IO until some diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c24xx/simtec-nor.c index b9d6d4f92c03..029744fcaacb 100644 --- a/arch/arm/mach-s3c24xx/simtec-nor.c +++ b/arch/arm/mach-s3c24xx/simtec-nor.c @@ -55,11 +55,7 @@ static struct physmap_flash_data simtec_nor_pdata = { }; static struct resource simtec_nor_resource[] = { - [0] = { - .start = S3C2410_CS1 + 0x4000000, - .end = S3C2410_CS1 + 0x4000000 + SZ_8M - 1, - .flags = IORESOURCE_MEM, - } + [0] = DEFINE_RES_MEM(S3C2410_CS1 + 0x4000000, SZ_8M), }; static struct platform_device simtec_device_nor = { diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c index 93470b158a4e..124fd5d63006 100644 --- a/arch/arm/mach-s3c64xx/dev-audio.c +++ b/arch/arm/mach-s3c64xx/dev-audio.c @@ -57,21 +57,9 @@ static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev) } static struct resource s3c64xx_iis0_resource[] = { - [0] = { - .start = S3C64XX_PA_IIS0, - .end = S3C64XX_PA_IIS0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_OUT, - .end = DMACH_I2S0_OUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_IN, - .end = DMACH_I2S0_IN, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_IIS0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S0_OUT), + [2] = DEFINE_RES_DMA(DMACH_I2S0_IN), }; static struct s3c_audio_pdata i2sv3_pdata = { @@ -95,21 +83,9 @@ struct platform_device s3c64xx_device_iis0 = { EXPORT_SYMBOL(s3c64xx_device_iis0); static struct resource s3c64xx_iis1_resource[] = { - [0] = { - .start = S3C64XX_PA_IIS1, - .end = S3C64XX_PA_IIS1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_OUT, - .end = DMACH_I2S1_OUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_IN, - .end = DMACH_I2S1_IN, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_IIS1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S1_OUT), + [2] = DEFINE_RES_DMA(DMACH_I2S1_IN), }; struct platform_device s3c64xx_device_iis1 = { @@ -124,21 +100,9 @@ struct platform_device s3c64xx_device_iis1 = { EXPORT_SYMBOL(s3c64xx_device_iis1); static struct resource s3c64xx_iisv4_resource[] = { - [0] = { - .start = S3C64XX_PA_IISV4, - .end = S3C64XX_PA_IISV4 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_HSI_I2SV40_TX, - .end = DMACH_HSI_I2SV40_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_HSI_I2SV40_RX, - .end = DMACH_HSI_I2SV40_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_IISV4, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_HSI_I2SV40_TX), + [2] = DEFINE_RES_DMA(DMACH_HSI_I2SV40_RX), }; static struct s3c_audio_pdata i2sv4_pdata = { @@ -187,21 +151,9 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev) } static struct resource s3c64xx_pcm0_resource[] = { - [0] = { - .start = S3C64XX_PA_PCM0, - .end = S3C64XX_PA_PCM0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), }; static struct s3c_audio_pdata s3c_pcm0_pdata = { @@ -220,21 +172,9 @@ struct platform_device s3c64xx_device_pcm0 = { EXPORT_SYMBOL(s3c64xx_device_pcm0); static struct resource s3c64xx_pcm1_resource[] = { - [0] = { - .start = S3C64XX_PA_PCM1, - .end = S3C64XX_PA_PCM1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM1_TX, - .end = DMACH_PCM1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM1_RX, - .end = DMACH_PCM1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), }; static struct s3c_audio_pdata s3c_pcm1_pdata = { @@ -265,31 +205,11 @@ static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev) } static struct resource s3c64xx_ac97_resource[] = { - [0] = { - .start = S3C64XX_PA_AC97, - .end = S3C64XX_PA_AC97 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_AC97_PCMOUT, - .end = DMACH_AC97_PCMOUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_AC97_PCMIN, - .end = DMACH_AC97_PCMIN, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_AC97_MICIN, - .end = DMACH_AC97_MICIN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .start = IRQ_AC97, - .end = IRQ_AC97, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_AC97, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), + [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), + [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), + [4] = DEFINE_RES_IRQ(IRQ_AC97), }; static struct s3c_audio_pdata s3c_ac97_pdata; diff --git a/arch/arm/mach-s3c64xx/dev-uart.c b/arch/arm/mach-s3c64xx/dev-uart.c index c681b99eda08..46e18d77ea93 100644 --- a/arch/arm/mach-s3c64xx/dev-uart.c +++ b/arch/arm/mach-s3c64xx/dev-uart.c @@ -31,55 +31,23 @@ /* 64xx uarts are closer together */ static struct resource s3c64xx_uart0_resource[] = { - [0] = { - .start = S3C_PA_UART0, - .end = S3C_PA_UART0 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART0, - .end = IRQ_UART0, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C_PA_UART0, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_UART0), }; static struct resource s3c64xx_uart1_resource[] = { - [0] = { - .start = S3C_PA_UART1, - .end = S3C_PA_UART1 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART1, - .end = IRQ_UART1, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C_PA_UART1, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_UART1), }; static struct resource s3c6xx_uart2_resource[] = { - [0] = { - .start = S3C_PA_UART2, - .end = S3C_PA_UART2 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART2, - .end = IRQ_UART2, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C_PA_UART2, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_UART2), }; static struct resource s3c64xx_uart3_resource[] = { - [0] = { - .start = S3C_PA_UART3, - .end = S3C_PA_UART3 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_UART3, - .end = IRQ_UART3, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S3C_PA_UART3, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_UART3), }; diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index b86f2779e4e6..f252691fb209 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -165,21 +165,10 @@ static void __init anw6410_dm9000_enable(void) } static struct resource anw6410_dm9000_resource[] = { - [0] = { - .start = ANW6410_PA_DM9000, - .end = ANW6410_PA_DM9000 + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = ANW6410_PA_DM9000 + 4, - .end = ANW6410_PA_DM9000 + 4 + 500, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_EINT(15), - .end = IRQ_EINT(15), - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, - }, + [0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4), + [1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501), + [2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \ + | IRQF_TRIGGER_HIGH), }; static struct dm9000_plat_data anw6410_dm9000_pdata = { diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index e20bf5835365..164467cbb7ea 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -232,21 +232,10 @@ static struct platform_device crag6410_gpio_keydev = { }; static struct resource crag6410_dm9k_resource[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN5, - .end = S3C64XX_PA_XM0CSN5 + 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C64XX_PA_XM0CSN5 + (1 << 8), - .end = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = S3C_EINT(17), - .end = S3C_EINT(17), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2), + [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2), + [2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), }; static struct dm9000_plat_data mini6410_dm9k_pdata = { @@ -262,12 +251,7 @@ static struct platform_device crag6410_dm9k_device = { }; static struct resource crag6410_mmgpio_resource[] = { - [0] = { - .name = "dat", - .start = S3C64XX_PA_XM0CSN4 + 1, - .end = S3C64XX_PA_XM0CSN4 + 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"), }; static struct platform_device crag6410_mmgpio = { diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index c34c2ab22ead..b2166d4a5538 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -85,21 +85,10 @@ static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = { /* DM9000AEP 10/100 ethernet controller */ static struct resource mini6410_dm9k_resource[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN1, - .end = S3C64XX_PA_XM0CSN1 + 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C64XX_PA_XM0CSN1 + 4, - .end = S3C64XX_PA_XM0CSN1 + 5, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = S3C_EINT(7), - .end = S3C_EINT(7), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - } + [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2), + [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2), + [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), }; static struct dm9000_plat_data mini6410_dm9k_pdata = { diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c index be2a9a22ab74..5c08266cea21 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c64xx/mach-real6410.c @@ -86,21 +86,10 @@ static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = { /* DM9000AEP 10/100 ethernet controller */ static struct resource real6410_dm9k_resource[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN1, - .end = S3C64XX_PA_XM0CSN1 + 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C64XX_PA_XM0CSN1 + 4, - .end = S3C64XX_PA_XM0CSN1 + 5, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = S3C_EINT(7), - .end = S3C_EINT(7), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - } + [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2), + [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2), + [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), }; static struct dm9000_plat_data real6410_dm9k_pdata = { diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index d55bc96d9582..1ecd0485a9b6 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -182,16 +182,9 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { */ static struct resource smdk6410_smsc911x_resources[] = { - [0] = { - .start = S3C64XX_PA_XM0CSN1, - .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C_EINT(10), - .end = S3C_EINT(10), - .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW, - }, + [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, SZ_64K), + [1] = DEFINE_RES_NAMED(S3C_EINT(10), 1, NULL, IORESOURCE_IRQ \ + | IRQ_TYPE_LEVEL_LOW), }; static struct smsc911x_platform_config smdk6410_smsc911x_pdata = { diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c index 35f1f226dabb..91113ddc51da 100644 --- a/arch/arm/mach-s5p64x0/dev-audio.c +++ b/arch/arm/mach-s5p64x0/dev-audio.c @@ -51,21 +51,9 @@ static struct s3c_audio_pdata s5p6440_i2s_pdata = { }; static struct resource s5p64x0_i2s0_resource[] = { - [0] = { - .start = S5P64X0_PA_I2S, - .end = S5P64X0_PA_I2S + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_TX, - .end = DMACH_I2S0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_RX, - .end = DMACH_I2S0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5P64X0_PA_I2S, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), }; struct platform_device s5p6440_device_iis = { @@ -130,21 +118,9 @@ static struct s3c_audio_pdata s5p6450_i2s_pdata = { }; static struct resource s5p6450_i2s1_resource[] = { - [0] = { - .start = S5P6450_PA_I2S1, - .end = S5P6450_PA_I2S1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_TX, - .end = DMACH_I2S1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_RX, - .end = DMACH_I2S1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5P6450_PA_I2S1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), }; struct platform_device s5p6450_device_iis1 = { @@ -158,21 +134,9 @@ struct platform_device s5p6450_device_iis1 = { }; static struct resource s5p6450_i2s2_resource[] = { - [0] = { - .start = S5P6450_PA_I2S2, - .end = S5P6450_PA_I2S2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S2_TX, - .end = DMACH_I2S2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S2_RX, - .end = DMACH_I2S2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5P6450_PA_I2S2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), }; struct platform_device s5p6450_device_iis2 = { @@ -208,21 +172,9 @@ static struct s3c_audio_pdata s5p6440_pcm_pdata = { }; static struct resource s5p6440_pcm0_resource[] = { - [0] = { - .start = S5P64X0_PA_PCM, - .end = S5P64X0_PA_PCM + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5P64X0_PA_PCM, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), }; struct platform_device s5p6440_device_pcm = { diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c index ab2d27172cbc..9d4bde3f1110 100644 --- a/arch/arm/mach-s5pc100/dev-audio.c +++ b/arch/arm/mach-s5pc100/dev-audio.c @@ -56,26 +56,10 @@ static struct s3c_audio_pdata i2sv5_pdata = { }; static struct resource s5pc100_iis0_resource[] = { - [0] = { - .start = S5PC100_PA_I2S0, - .end = S5PC100_PA_I2S0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_TX, - .end = DMACH_I2S0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_RX, - .end = DMACH_I2S0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_I2S0S_TX, - .end = DMACH_I2S0S_TX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PC100_PA_I2S0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), + [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), }; struct platform_device s5pc100_device_iis0 = { @@ -103,21 +87,9 @@ static struct s3c_audio_pdata i2sv3_pdata = { }; static struct resource s5pc100_iis1_resource[] = { - [0] = { - .start = S5PC100_PA_I2S1, - .end = S5PC100_PA_I2S1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_TX, - .end = DMACH_I2S1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_RX, - .end = DMACH_I2S1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PC100_PA_I2S1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), }; struct platform_device s5pc100_device_iis1 = { @@ -131,21 +103,9 @@ struct platform_device s5pc100_device_iis1 = { }; static struct resource s5pc100_iis2_resource[] = { - [0] = { - .start = S5PC100_PA_I2S2, - .end = S5PC100_PA_I2S2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S2_TX, - .end = DMACH_I2S2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S2_RX, - .end = DMACH_I2S2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PC100_PA_I2S2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), }; struct platform_device s5pc100_device_iis2 = { @@ -184,21 +144,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = { }; static struct resource s5pc100_pcm0_resource[] = { - [0] = { - .start = S5PC100_PA_PCM0, - .end = S5PC100_PA_PCM0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PC100_PA_PCM0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), }; struct platform_device s5pc100_device_pcm0 = { @@ -212,21 +160,9 @@ struct platform_device s5pc100_device_pcm0 = { }; static struct resource s5pc100_pcm1_resource[] = { - [0] = { - .start = S5PC100_PA_PCM1, - .end = S5PC100_PA_PCM1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM1_TX, - .end = DMACH_PCM1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM1_RX, - .end = DMACH_PCM1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PC100_PA_PCM1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), }; struct platform_device s5pc100_device_pcm1 = { @@ -247,31 +183,11 @@ static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev) } static struct resource s5pc100_ac97_resource[] = { - [0] = { - .start = S5PC100_PA_AC97, - .end = S5PC100_PA_AC97 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_AC97_PCMOUT, - .end = DMACH_AC97_PCMOUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_AC97_PCMIN, - .end = DMACH_AC97_PCMIN, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_AC97_MICIN, - .end = DMACH_AC97_MICIN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .start = IRQ_AC97, - .end = IRQ_AC97, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S5PC100_PA_AC97, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), + [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), + [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), + [4] = DEFINE_RES_IRQ(IRQ_AC97), }; static struct s3c_audio_pdata s3c_ac97_pdata = { @@ -308,16 +224,8 @@ static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev) } static struct resource s5pc100_spdif_resource[] = { - [0] = { - .start = S5PC100_PA_SPDIF, - .end = S5PC100_PA_SPDIF + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPDIF, - .end = DMACH_SPDIF, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PC100_PA_SPDIF, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_SPDIF), }; static struct s3c_audio_pdata s5p_spdif_pdata = { diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 63f5d82004b5..8367749c3eec 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -59,26 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = { }; static struct resource s5pv210_iis0_resource[] = { - [0] = { - .start = S5PV210_PA_IIS0, - .end = S5PV210_PA_IIS0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_TX, - .end = DMACH_I2S0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_RX, - .end = DMACH_I2S0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_I2S0S_TX, - .end = DMACH_I2S0S_TX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_IIS0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), + [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), }; struct platform_device s5pv210_device_iis0 = { @@ -106,21 +90,9 @@ static struct s3c_audio_pdata i2sv3_pdata = { }; static struct resource s5pv210_iis1_resource[] = { - [0] = { - .start = S5PV210_PA_IIS1, - .end = S5PV210_PA_IIS1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_TX, - .end = DMACH_I2S1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_RX, - .end = DMACH_I2S1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_IIS1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), }; struct platform_device s5pv210_device_iis1 = { @@ -134,21 +106,9 @@ struct platform_device s5pv210_device_iis1 = { }; static struct resource s5pv210_iis2_resource[] = { - [0] = { - .start = S5PV210_PA_IIS2, - .end = S5PV210_PA_IIS2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S2_TX, - .end = DMACH_I2S2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S2_RX, - .end = DMACH_I2S2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_IIS2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), + [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), }; struct platform_device s5pv210_device_iis2 = { @@ -188,21 +148,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = { }; static struct resource s5pv210_pcm0_resource[] = { - [0] = { - .start = S5PV210_PA_PCM0, - .end = S5PV210_PA_PCM0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_PCM0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), }; struct platform_device s5pv210_device_pcm0 = { @@ -216,21 +164,9 @@ struct platform_device s5pv210_device_pcm0 = { }; static struct resource s5pv210_pcm1_resource[] = { - [0] = { - .start = S5PV210_PA_PCM1, - .end = S5PV210_PA_PCM1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM1_TX, - .end = DMACH_PCM1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM1_RX, - .end = DMACH_PCM1_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_PCM1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), }; struct platform_device s5pv210_device_pcm1 = { @@ -244,21 +180,9 @@ struct platform_device s5pv210_device_pcm1 = { }; static struct resource s5pv210_pcm2_resource[] = { - [0] = { - .start = S5PV210_PA_PCM2, - .end = S5PV210_PA_PCM2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM2_TX, - .end = DMACH_PCM2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM2_RX, - .end = DMACH_PCM2_RX, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_PCM2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_PCM2_TX), + [2] = DEFINE_RES_DMA(DMACH_PCM2_RX), }; struct platform_device s5pv210_device_pcm2 = { @@ -279,31 +203,11 @@ static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev) } static struct resource s5pv210_ac97_resource[] = { - [0] = { - .start = S5PV210_PA_AC97, - .end = S5PV210_PA_AC97 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_AC97_PCMOUT, - .end = DMACH_AC97_PCMOUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_AC97_PCMIN, - .end = DMACH_AC97_PCMIN, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_AC97_MICIN, - .end = DMACH_AC97_MICIN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .start = IRQ_AC97, - .end = IRQ_AC97, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_AC97, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), + [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), + [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), + [4] = DEFINE_RES_IRQ(IRQ_AC97), }; static struct s3c_audio_pdata s3c_ac97_pdata = { @@ -334,16 +238,8 @@ static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev) } static struct resource s5pv210_spdif_resource[] = { - [0] = { - .start = S5PV210_PA_SPDIF, - .end = S5PV210_PA_SPDIF + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPDIF, - .end = DMACH_SPDIF, - .flags = IORESOURCE_DMA, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_SPDIF, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_SPDIF), }; static struct s3c_audio_pdata samsung_spdif_pdata = { diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 91d4ad8bcc73..fa1b61209fd9 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -119,21 +119,10 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = { }; static struct resource smdkv210_dm9000_resources[] = { - [0] = { - .start = S5PV210_PA_SROM_BANK5, - .end = S5PV210_PA_SROM_BANK5, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S5PV210_PA_SROM_BANK5 + 2, - .end = S5PV210_PA_SROM_BANK5 + 2, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_EINT(9), - .end = IRQ_EINT(9), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, + [0] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5, 1), + [1] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5 + 2, 1), + [2] = DEFINE_RES_NAMED(IRQ_EINT(9), 1, NULL, IORESOURCE_IRQ \ + | IORESOURCE_IRQ_HIGHLEVEL), }; static struct dm9000_plat_data smdkv210_dm9000_platdata = { diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c index b49108b890a8..ff02e2da99f2 100644 --- a/arch/arm/mach-sa1100/pci-nanoengine.c +++ b/arch/arm/mach-sa1100/pci-nanoengine.c @@ -129,12 +129,6 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot, return NANOENGINE_IRQ_GPIO_PCI; } -struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys, - &sys->resources); -} - static struct resource pci_io_ports = DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO"); @@ -274,7 +268,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) static struct hw_pci nanoengine_pci __initdata = { .map_irq = pci_nanoengine_map_irq, .nr_controllers = 1, - .scan = pci_nanoengine_scan_bus, + .ops = &pci_nano_ops, .setup = pci_nanoengine_setup, }; diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index 7cb79a092f31..9089407d5326 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c @@ -29,10 +29,9 @@ extern void __init via82c505_preinit(void); static struct hw_pci shark_pci __initdata = { .setup = via82c505_setup, - .swizzle = pci_std_swizzle, .map_irq = shark_map_irq, .nr_controllers = 1, - .scan = via82c505_scan_bus, + .ops = &via82c505_ops, .preinit = via82c505_preinit, }; diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index cb224a344af0..0891ec6e27f5 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -365,23 +365,13 @@ static struct platform_device mipidsi0_device = { }; /* SDHI0 */ -static irqreturn_t ag5evm_sdhi0_gpio_cd(int irq, void *arg) -{ - struct device *dev = arg; - struct sh_mobile_sdhi_info *info = dev->platform_data; - struct tmio_mmc_data *pdata = info->pdata; - - tmio_mmc_cd_wakeup(pdata); - - return IRQ_HANDLED; -} - static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED, .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, + .cd_gpio = GPIO_PORT251, }; static struct resource sdhi0_resources[] = { @@ -557,7 +547,6 @@ static void __init ag5evm_init(void) lcd_backlight_reset(); /* enable SDHI0 on CN15 [SD I/F] */ - gpio_request(GPIO_FN_SDHICD0, NULL); gpio_request(GPIO_FN_SDHIWP0, NULL); gpio_request(GPIO_FN_SDHICMD0, NULL); gpio_request(GPIO_FN_SDHICLK0, NULL); @@ -566,13 +555,6 @@ static void __init ag5evm_init(void) gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); - if (!request_irq(intcs_evt2irq(0x3c0), ag5evm_sdhi0_gpio_cd, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "sdhi0 cd", &sdhi0_device.dev)) - sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD; - else - pr_warn("Unable to setup SDHI0 GPIO IRQ\n"); - /* enable SDHI1 on CN4 [WLAN I/F] */ gpio_request(GPIO_FN_SDHICLK1, NULL); gpio_request(GPIO_FN_SDHICMD1_PU, NULL); diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index f49e28abe0ab..8c6202bb6aeb 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1011,21 +1011,12 @@ static int slot_cn7_get_cd(struct platform_device *pdev) } /* SDHI0 */ -static irqreturn_t mackerel_sdhi0_gpio_cd(int irq, void *arg) -{ - struct device *dev = arg; - struct sh_mobile_sdhi_info *info = dev->platform_data; - struct tmio_mmc_data *pdata = info->pdata; - - tmio_mmc_cd_wakeup(pdata); - - return IRQ_HANDLED; -} - static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, + .tmio_flags = TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, + .cd_gpio = GPIO_PORT172, }; static struct resource sdhi0_resources[] = { @@ -1384,7 +1375,6 @@ static void __init mackerel_init(void) { u32 srcr4; struct clk *clk; - int ret; /* External clock source */ clk_set_rate(&sh7372_dv_clki_clk, 27000000); @@ -1481,7 +1471,6 @@ static void __init mackerel_init(void) irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); /* enable SDHI0 */ - gpio_request(GPIO_FN_SDHICD0, NULL); gpio_request(GPIO_FN_SDHIWP0, NULL); gpio_request(GPIO_FN_SDHICMD0, NULL); gpio_request(GPIO_FN_SDHICLK0, NULL); @@ -1490,13 +1479,6 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); - ret = request_irq(evt2irq(0x3340), mackerel_sdhi0_gpio_cd, - IRQF_TRIGGER_FALLING, "sdhi0 cd", &sdhi0_device.dev); - if (!ret) - sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD; - else - pr_err("Cannot get IRQ #%d: %d\n", evt2irq(0x3340), ret); - #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) /* enable SDHI1 */ gpio_request(GPIO_FN_SDHICMD1, NULL); diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 6ac015c89206..b202c1272526 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -16,6 +16,59 @@ __CPUINIT +/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks! + * + * The secondary kernel init calls v7_flush_dcache_all before it enables + * the L1; however, the L1 comes out of reset in an undefined state, so + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch + * of cache lines with uninitialized data and uninitialized tags to get + * written out to memory, which does really unpleasant things to the main + * processor. We fix this by performing an invalidate, rather than a + * clean + invalidate, before jumping into the kernel. + * + * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs + * to be called for both secondary cores startup and primary core resume + * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + +ENTRY(shmobile_invalidate_start) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(shmobile_invalidate_start) + /* * Reset vector for secondary CPUs. * This will be mapped at address 0 by SBAR register. @@ -24,4 +77,5 @@ .align 12 ENTRY(shmobile_secondary_vector) ldr pc, 1f -1: .long secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET +1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET +ENDPROC(shmobile_secondary_vector) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 83ad3fe0a75f..c85e6ecda606 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -4,7 +4,6 @@ extern void shmobile_earlytimer_init(void); extern struct sys_timer shmobile_timer; struct twd_local_timer; -void shmobile_twd_init(struct twd_local_timer *twd_local_timer); extern void shmobile_setup_console(void); extern void shmobile_secondary_vector(void); extern int shmobile_platform_cpu_kill(unsigned int cpu); @@ -82,5 +81,6 @@ extern int r8a7779_platform_cpu_kill(unsigned int cpu); extern void r8a7779_secondary_init(unsigned int cpu); extern int r8a7779_boot_secondary(unsigned int cpu); extern void r8a7779_smp_prepare_cpus(void); +extern void r8a7779_register_twd(void); #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 12c6f529ab89..e98e46f6cf55 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -262,10 +262,14 @@ void __init r8a7779_add_standard_devices(void) ARRAY_SIZE(r8a7779_late_devices)); } +/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ +void __init __weak r8a7779_register_twd(void) { } + static void __init r8a7779_earlytimer_init(void) { r8a7779_clock_init(); shmobile_earlytimer_init(); + r8a7779_register_twd(); } void __init r8a7779_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 5bebffc10455..04a0dfe75493 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -688,10 +688,14 @@ void __init sh73a0_add_standard_devices(void) ARRAY_SIZE(sh73a0_late_devices)); } +/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ +void __init __weak sh73a0_register_twd(void) { } + static void __init sh73a0_earlytimer_init(void) { sh73a0_clock_init(); shmobile_earlytimer_init(); + sh73a0_register_twd(); } void __init sh73a0_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index b62e19d4c9af..6d1d0238cbf7 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -64,8 +64,15 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; +#ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); +void __init r8a7779_register_twd(void) +{ + twd_local_timer_register(&twd_local_timer); +} +#endif + static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { void __iomem *scu_base = scu_base_addr(); @@ -84,7 +91,6 @@ unsigned int __init r8a7779_get_core_count(void) { void __iomem *scu_base = scu_base_addr(); - shmobile_twd_init(&twd_local_timer); return scu_get_core_count(scu_base); } diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 14ad8b052f1a..e36c41c4ab40 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -42,7 +42,13 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(scu_lock); static unsigned long tmp; +#ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); +void __init sh73a0_register_twd(void) +{ + twd_local_timer_register(&twd_local_timer); +} +#endif static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) { @@ -62,7 +68,6 @@ unsigned int __init sh73a0_get_core_count(void) { void __iomem *scu_base = scu_base_addr(); - shmobile_twd_init(&twd_local_timer); return scu_get_core_count(scu_base); } diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 2fba5f3d1c8a..8b79e7917a23 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -46,15 +46,6 @@ static void __init shmobile_timer_init(void) { } -void __init shmobile_twd_init(struct twd_local_timer *twd_local_timer) -{ -#ifdef CONFIG_HAVE_ARM_TWD - int err = twd_local_timer_register(twd_local_timer); - if (err) - pr_err("twd_local_timer_register failed %d\n", err); -#endif -} - struct sys_timer shmobile_timer = { .init = shmobile_timer_init, }; diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 0952494f481a..72ae62003520 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -37,7 +37,6 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/setup.h> -#include <asm/hardware/gic.h> #include <mach/iomap.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index fef66a7486ed..f07488e0bd32 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -53,10 +53,10 @@ static void flowctrl_update(u8 offset, u32 value) void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) { - return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); + return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); } void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) { - return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); + return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); } diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h index 3c9339058bec..9077092812c0 100644 --- a/arch/arm/mach-tegra/include/mach/dma.h +++ b/arch/arm/mach-tegra/include/mach/dma.h @@ -51,8 +51,6 @@ #define TEGRA_DMA_REQ_SEL_OWR 25 #define TEGRA_DMA_REQ_SEL_INVALID 31 -#if defined(CONFIG_TEGRA_SYSTEM_DMA) - struct tegra_dma_req; struct tegra_dma_channel; @@ -151,5 +149,3 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch); int __init tegra_dma_init(void); #endif - -#endif diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index 54a816ff3847..0e09137506ec 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -475,7 +475,6 @@ static struct hw_pci tegra_pcie_hw __initdata = { .nr_controllers = 2, .setup = tegra_pcie_setup, .scan = tegra_pcie_scan_bus, - .swizzle = pci_std_swizzle, .map_irq = tegra_pcie_map_irq, }; diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 1eed8d4a80ef..315672c7bd48 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -124,7 +124,7 @@ static u64 tegra_rtc_read_ms(void) } /* - * read_persistent_clock - Return time from a persistent clock. + * tegra_read_persistent_clock - Return time from a persistent clock. * * Reads the time from a source which isn't disabled during PM, the * 32k sync timer. Convert the cycles elapsed since last read into @@ -133,7 +133,7 @@ static u64 tegra_rtc_read_ms(void) * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ -void read_persistent_clock(struct timespec *ts) +static void tegra_read_persistent_clock(struct timespec *ts) { u64 delta; struct timespec *tsp = &persistent_ts; @@ -243,6 +243,7 @@ static void __init tegra_init_timer(void) tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_register_device(&tegra_clockevent); tegra_twd_init(); + register_persistent_clock(NULL, tegra_read_persistent_clock); } struct sys_timer tegra_timer = { diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index ef7099eea0f2..0e8470a3fbeb 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -10,10 +10,6 @@ config UX500_SOC_COMMON select ARM_ERRATA_764369 select CACHE_L2X0 -config UX500_SOC_DB5500 - bool - select MFD_DB5500_PRCMU - config UX500_SOC_DB8500 bool select MFD_DB8500_PRCMU @@ -45,15 +41,8 @@ config MACH_SNOWBALL help Include support for the snowball development platform. -config MACH_U5500 - bool "U5500 Development platform" - select UX500_SOC_DB5500 - help - Include support for the U5500 development platform. - config UX500_AUTO_PLATFORM def_bool y - depends on !MACH_U5500 select MACH_MOP500 help At least one platform needs to be selected in order to build @@ -74,18 +63,4 @@ config UX500_DEBUG_UART Choose the UART on which kernel low-level debug messages should be output. -config U5500_MODEM_IRQ - bool "Modem IRQ support" - depends on UX500_SOC_DB5500 - default y - help - Add support for handling IRQ:s from modem side - -config U5500_MBOX - bool "Mailbox support" - depends on U5500_MODEM_IRQ - default y - help - Add support for U5500 mailbox communication with modem side - endif diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 465b9ec9510a..fc7db5df970b 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -5,16 +5,11 @@ obj-y := clock.o cpu.o devices.o devices-common.o \ id.o usb.o timer.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o -obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ board-mop500-regulators.o \ board-mop500-uib.o board-mop500-stuib.o \ board-mop500-u8500uib.o \ board-mop500-pins.o -obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o -obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o - diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c deleted file mode 100644 index 836112eedde7..000000000000 --- a/arch/arm/mach-ux500/board-u5500-sdi.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Hanumath Prasad <ulf.hansson@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/amba/mmci.h> -#include <linux/mmc/host.h> - -#include <plat/pincfg.h> -#include <plat/gpio-nomadik.h> -#include <mach/db5500-regs.h> -#include <plat/ste_dma40.h> - -#include "pins-db5500.h" -#include "devices-db5500.h" -#include "ste-dma40-db5500.h" - -static pin_cfg_t u5500_sdi_pins[] = { - /* SDI0 (POP eMMC) */ - GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW, -}; - -#ifdef CONFIG_STE_DMA40 -struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; - -static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; -#endif - -static struct mmci_platform_data u5500_sdi0_data = { - .ocr_mask = MMC_VDD_165_195, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | - MMC_CAP_8_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED, - .gpio_cd = -1, - .gpio_wp = -1, -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &u5500_sdi0_dma_cfg_rx, - .dma_tx_param = &u5500_sdi0_dma_cfg_tx, -#endif -}; - -void __init u5500_sdi_init(struct device *parent) -{ - nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins)); - - db5500_add_sdi0(parent, &u5500_sdi0_data); -} diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c deleted file mode 100644 index 0ff4be72a809..000000000000 --- a/arch/arm/mach-ux500/board-u5500.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <linux/irq.h> -#include <linux/i2c.h> -#include <linux/mfd/abx500/ab5500.h> - -#include <asm/hardware/gic.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <plat/pincfg.h> -#include <plat/i2c.h> -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> -#include <mach/devices.h> -#include <mach/setup.h> - -#include "pins-db5500.h" -#include "devices-db5500.h" -#include <linux/led-lm3530.h> - -/* - * GPIO - */ - -static pin_cfg_t u5500_pins[] = { - /* I2C */ - GPIO218_I2C2_SCL | PIN_INPUT_PULLUP, - GPIO219_I2C2_SDA | PIN_INPUT_PULLUP, - - /* DISPLAY_ENABLE */ - GPIO226_GPIO | PIN_OUTPUT_LOW, - - /* Backlight Enbale */ - GPIO224_GPIO | PIN_OUTPUT_HIGH, -}; -/* - * I2C - */ - -#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ -static struct nmk_i2c_controller u5500_i2c##id##_data = { \ - /* \ - * slave data setup time, which is \ - * 250 ns,100ns,10ns which is 14,6,2 \ - * respectively for a 48 Mhz \ - * i2c clock \ - */ \ - .slsu = _slsu, \ - /* Tx FIFO threshold */ \ - .tft = _tft, \ - /* Rx FIFO threshold */ \ - .rft = _rft, \ - /* std. mode operation */ \ - .clk_freq = clk, \ - .sm = _sm, \ -} -/* - * The board uses TODO <3> i2c controllers, initialize all of - * them with slave data setup time of 250 ns, - * Tx & Rx FIFO threshold values as 1 and standard - * mode of operation - */ - -U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST); - -static struct lm3530_platform_data u5500_als_platform_data = { - .mode = LM3530_BL_MODE_MANUAL, - .als_input_mode = LM3530_INPUT_ALS1, - .max_current = LM3530_FS_CURR_26mA, - .pwm_pol_hi = true, - .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms, - .brt_ramp_law = 1, /* Linear */ - .brt_ramp_fall = LM3530_RAMP_TIME_8s, - .brt_ramp_rise = LM3530_RAMP_TIME_8s, - .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm, - .als2_resistor_sel = LM3530_ALS_IMPD_Z, - .als_vmin = 730, /* mV */ - .als_vmax = 1020, /* mV */ - .brt_val = 0x7F, /* Max brightness */ -}; - -static struct i2c_board_info __initdata u5500_i2c2_devices[] = { - { - /* Backlight */ - I2C_BOARD_INFO("lm3530-led", 0x36), - .platform_data = &u5500_als_platform_data, - }, -}; - -static void __init u5500_i2c_init(struct device *parent) -{ - db5500_add_i2c2(parent, &u5500_i2c2_data); - i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices)); -} - -static struct ab5500_platform_data ab5500_plf_data = { - .irq = { - .base = 0, - .count = 0, - }, - .init_settings = NULL, - .init_settings_sz = 0, - .pm_power_off = false, -}; - -static struct platform_device ab5500_device = { - .name = "ab5500-core", - .id = 0, - .dev = { - .platform_data = &ab5500_plf_data, - }, - .num_resources = 0, -}; - -static struct platform_device *u5500_platform_devices[] __initdata = { - &ab5500_device, -}; - -static void __init u5500_uart_init(struct device *parent) -{ - db5500_add_uart0(parent, NULL); - db5500_add_uart1(parent, NULL); - db5500_add_uart2(parent, NULL); -} - -static void __init u5500_init_machine(void) -{ - struct device *parent = NULL; - int i; - - parent = u5500_init_devices(); - nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins)); - - u5500_i2c_init(parent); - u5500_sdi_init(parent); - u5500_uart_init(parent); - - for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++) - u5500_platform_devices[i]->dev.parent = parent; - - platform_add_devices(u5500_platform_devices, - ARRAY_SIZE(u5500_platform_devices)); -} - -MACHINE_START(U5500, "ST-Ericsson U5500 Platform") - .atag_offset = 0x100, - .map_io = u5500_map_io, - .init_irq = ux500_init_irq, - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = u5500_init_machine, -MACHINE_END diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 77a75ed0df67..df91344aa2db 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -36,9 +36,7 @@ static int __init ux500_l2x0_unlock(void) static int __init ux500_l2x0_init(void) { - if (cpu_is_u5500()) - l2x0_base = __io_address(U5500_L2CC_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) l2x0_base = __io_address(U8500_L2CC_BASE); else ux500_unknown_soc(); diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index ec35f0aa5665..9feb6bc7f20e 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -149,9 +149,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) unsigned long mturate; unsigned long retclk; - if (cpu_is_u5500()) - addr = __io_address(U5500_PRCMU_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) addr = __io_address(U8500_PRCMU_BASE); else ux500_unknown_soc(); @@ -705,14 +703,6 @@ late_initcall(clk_init_smp_twd_cpufreq); int __init clk_init(void) { - if (cpu_is_u5500()) { - /* Clock tree for U5500 not implemented yet */ - clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; - clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; - clk_uartclk.rate = 36360000; - clk_sdmmcclk.rate = 99900000; - } - clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); clkdev_add(&clk_smp_twd_lookup); diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c deleted file mode 100644 index bca47f32082f..000000000000 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <linux/io.h> -#include <linux/irq.h> - -#include <asm/mach/map.h> -#include <asm/pmu.h> - -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> -#include <mach/devices.h> -#include <mach/setup.h> -#include <mach/irqs.h> -#include <mach/usb.h> - -#include "devices-db5500.h" -#include "ste-dma40-db5500.h" - -static struct map_desc u5500_uart_io_desc[] __initdata = { - __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K), -}; - -static struct map_desc u5500_io_desc[] __initdata = { - /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ - __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K), - __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K), - __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K), - - __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), - __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), - __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), -}; - -static struct resource mbox0_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX0_PEER_START, - .end = U5500_MBOX0_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX0_LOCAL_START, - .end = U5500_MBOX0_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR0_VIRT_IRQ, - .end = MBOX_PAIR0_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource mbox1_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX1_PEER_START, - .end = U5500_MBOX1_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX1_LOCAL_START, - .end = U5500_MBOX1_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR1_VIRT_IRQ, - .end = MBOX_PAIR1_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource mbox2_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX2_PEER_START, - .end = U5500_MBOX2_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX2_LOCAL_START, - .end = U5500_MBOX2_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR2_VIRT_IRQ, - .end = MBOX_PAIR2_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device mbox0_device = { - .id = 0, - .name = "mbox", - .resource = mbox0_resources, - .num_resources = ARRAY_SIZE(mbox0_resources), -}; - -static struct platform_device mbox1_device = { - .id = 1, - .name = "mbox", - .resource = mbox1_resources, - .num_resources = ARRAY_SIZE(mbox1_resources), -}; - -static struct platform_device mbox2_device = { - .id = 2, - .name = "mbox", - .resource = mbox2_resources, - .num_resources = ARRAY_SIZE(mbox2_resources), -}; - -static struct platform_device *db5500_platform_devs[] __initdata = { - &mbox0_device, - &mbox1_device, - &mbox2_device, -}; - -static resource_size_t __initdata db5500_gpio_base[] = { - U5500_GPIOBANK0_BASE, - U5500_GPIOBANK1_BASE, - U5500_GPIOBANK2_BASE, - U5500_GPIOBANK3_BASE, - U5500_GPIOBANK4_BASE, - U5500_GPIOBANK5_BASE, - U5500_GPIOBANK6_BASE, - U5500_GPIOBANK7_BASE, -}; - -static void __init db5500_add_gpios(struct device *parent) -{ - struct nmk_gpio_platform_data pdata = { - /* No custom data yet */ - }; - - dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base), - IRQ_DB5500_GPIO0, &pdata); -} - -void __init u5500_map_io(void) -{ - /* - * Map the UARTs early so that the DEBUG_LL stuff continues to work. - */ - iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc)); - - ux500_map_io(); - - iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); - - _PRCMU_BASE = __io_address(U5500_PRCMU_BASE); -} - -static void __init db5500_pmu_init(void) -{ - struct resource res[] = { - [0] = { - .start = IRQ_DB5500_PMU0, - .end = IRQ_DB5500_PMU0, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = IRQ_DB5500_PMU1, - .end = IRQ_DB5500_PMU1, - .flags = IORESOURCE_IRQ, - }, - }; - - platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU, - res, ARRAY_SIZE(res)); -} - -static int usb_db5500_rx_dma_cfg[] = { - DB5500_DMA_DEV4_USB_OTG_IEP_1_9, - DB5500_DMA_DEV5_USB_OTG_IEP_2_10, - DB5500_DMA_DEV6_USB_OTG_IEP_3_11, - DB5500_DMA_DEV20_USB_OTG_IEP_4_12, - DB5500_DMA_DEV21_USB_OTG_IEP_5_13, - DB5500_DMA_DEV22_USB_OTG_IEP_6_14, - DB5500_DMA_DEV23_USB_OTG_IEP_7_15, - DB5500_DMA_DEV38_USB_OTG_IEP_8 -}; - -static int usb_db5500_tx_dma_cfg[] = { - DB5500_DMA_DEV4_USB_OTG_OEP_1_9, - DB5500_DMA_DEV5_USB_OTG_OEP_2_10, - DB5500_DMA_DEV6_USB_OTG_OEP_3_11, - DB5500_DMA_DEV20_USB_OTG_OEP_4_12, - DB5500_DMA_DEV21_USB_OTG_OEP_5_13, - DB5500_DMA_DEV22_USB_OTG_OEP_6_14, - DB5500_DMA_DEV23_USB_OTG_OEP_7_15, - DB5500_DMA_DEV38_USB_OTG_OEP_8 -}; - -static const char *db5500_read_soc_id(void) -{ - return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n"); -} - -static struct device * __init db5500_soc_device_init(void) -{ - const char *soc_id = db5500_read_soc_id(); - - return ux500_soc_device_init(soc_id); -} - -struct device * __init u5500_init_devices(void) -{ - struct device *parent; - int i; - - parent = db5500_soc_device_init(); - - db5500_add_gpios(parent); - db5500_pmu_init(); - db5500_dma_init(parent); - db5500_add_rtc(parent); - db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); - - for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++) - db5500_platform_devs[i]->dev.parent = parent; - - platform_add_devices(db5500_platform_devs, - ARRAY_SIZE(db5500_platform_devs)); - - return parent; -} diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index d11f3892a27d..4b4e59b30d81 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -10,7 +10,6 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/mfd/db8500-prcmu.h> -#include <linux/mfd/db5500-prcmu.h> #include <linux/clksrc-dbx500-prcmu.h> #include <linux/sys_soc.h> #include <linux/err.h> @@ -40,10 +39,7 @@ void __init ux500_init_irq(void) void __iomem *dist_base; void __iomem *cpu_base; - if (cpu_is_u5500()) { - dist_base = __io_address(U5500_GIC_DIST_BASE); - cpu_base = __io_address(U5500_GIC_CPU_BASE); - } else if (cpu_is_u8500()) { + if (cpu_is_u8500()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE); } else @@ -60,8 +56,6 @@ void __init ux500_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ - if (cpu_is_u5500()) - db5500_prcmu_early_init(); if (cpu_is_u8500()) db8500_prcmu_early_init(); clk_init(); diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c index c5312a4b49f5..dfdd4a54668d 100644 --- a/arch/arm/mach-ux500/devices-common.c +++ b/arch/arm/mach-ux500/devices-common.c @@ -11,7 +11,6 @@ #include <linux/irq.h> #include <linux/slab.h> #include <linux/platform_device.h> -#include <linux/amba/bus.h> #include <plat/gpio-nomadik.h> @@ -19,38 +18,6 @@ #include "devices-common.h" -struct amba_device * -dbx500_add_amba_device(struct device *parent, const char *name, - resource_size_t base, int irq, void *pdata, - unsigned int periphid) -{ - struct amba_device *dev; - int ret; - - dev = amba_device_alloc(name, base, SZ_4K); - if (!dev) - return ERR_PTR(-ENOMEM); - - dev->dma_mask = DMA_BIT_MASK(32); - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - - dev->irq[0] = irq; - - dev->periphid = periphid; - - dev->dev.platform_data = pdata; - - dev->dev.parent = parent; - - ret = amba_device_add(dev, &iomem_resource); - if (ret) { - amba_device_put(dev); - return ERR_PTR(ret); - } - - return dev; -} - static struct platform_device * dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq, struct nmk_gpio_platform_data *pdata) diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h index 39c74ec82add..f75bcb2ab13b 100644 --- a/arch/arm/mach-ux500/devices-common.h +++ b/arch/arm/mach-ux500/devices-common.h @@ -11,13 +11,9 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/sys_soc.h> +#include <linux/amba/bus.h> #include <plat/i2c.h> -extern struct amba_device * -dbx500_add_amba_device(struct device *parent, const char *name, - resource_size_t base, int irq, void *pdata, - unsigned int periphid); - struct spi_master_cntlr; static inline struct amba_device * @@ -25,8 +21,8 @@ dbx500_add_msp_spi(struct device *parent, const char *name, resource_size_t base, int irq, struct spi_master_cntlr *pdata) { - return dbx500_add_amba_device(parent, name, base, irq, - pdata, 0); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, 0); } static inline struct amba_device * @@ -34,8 +30,8 @@ dbx500_add_spi(struct device *parent, const char *name, resource_size_t base, int irq, struct spi_master_cntlr *pdata, u32 periphid) { - return dbx500_add_amba_device(parent, name, base, irq, - pdata, periphid); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, periphid); } struct mmci_platform_data; @@ -44,8 +40,8 @@ static inline struct amba_device * dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base, int irq, struct mmci_platform_data *pdata, u32 periphid) { - return dbx500_add_amba_device(parent, name, base, irq, - pdata, periphid); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, periphid); } struct amba_pl011_data; @@ -54,7 +50,7 @@ static inline struct amba_device * dbx500_add_uart(struct device *parent, const char *name, resource_size_t base, int irq, struct amba_pl011_data *pdata) { - return dbx500_add_amba_device(parent, name, base, irq, pdata, 0); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); } struct nmk_i2c_controller; @@ -85,7 +81,8 @@ dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq, static inline struct amba_device * dbx500_add_rtc(struct device *parent, resource_size_t base, int irq) { - return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0); + return amba_apb_device_add(parent, "rtc-pl031", base, SZ_4K, irq, + 0, NULL, 0); } struct nmk_gpio_platform_data; diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h deleted file mode 100644 index e70955502c35..000000000000 --- a/arch/arm/mach-ux500/devices-db5500.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __DEVICES_DB5500_H -#define __DEVICES_DB5500_H - -#include "devices-common.h" - -#define db5500_add_i2c1(parent, pdata) \ - dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata) -#define db5500_add_i2c2(parent, pdata) \ - dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata) -#define db5500_add_i2c3(parent, pdata) \ - dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata) - -#define db5500_add_msp0_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \ - IRQ_DB5500_MSP0, pdata) -#define db5500_add_msp1_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \ - IRQ_DB5500_MSP1, pdata) -#define db5500_add_msp2_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \ - IRQ_DB5500_MSP2, pdata) - -#define db5500_add_msp0_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \ - IRQ_DB5500_MSP0, pdata) -#define db5500_add_msp1_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \ - IRQ_DB5500_MSP1, pdata) -#define db5500_add_msp2_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \ - IRQ_DB5500_MSP2, pdata) - -#define db5500_add_rtc(parent) \ - dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC); - -#define db5500_add_usb(parent, rx_cfg, tx_cfg) \ - ux500_add_usb(parent, U5500_USBOTG_BASE, \ - IRQ_DB5500_USBOTG, rx_cfg, tx_cfg) - -#define db5500_add_sdi0(parent, pdata) \ - dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \ - IRQ_DB5500_SDMMC0, pdata, \ - 0x10480180) -#define db5500_add_sdi1(parent, pdata) \ - dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \ - IRQ_DB5500_SDMMC1, pdata, \ - 0x10480180) -#define db5500_add_sdi2(parent, pdata) \ - dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \ - IRQ_DB5500_SDMMC2, pdata \ - 0x10480180) -#define db5500_add_sdi3(parent, pdata) \ - dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \ - IRQ_DB5500_SDMMC3, pdata \ - 0x10480180) -#define db5500_add_sdi4(parent, pdata) \ - dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \ - IRQ_DB5500_SDMMC4, pdata \ - 0x10480180) - -/* This one has a bad peripheral ID in the U5500 silicon */ -#define db5500_add_spi0(parent, pdata) \ - dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \ - IRQ_DB5500_SPI0, pdata, \ - 0x10080023) -#define db5500_add_spi1(parent, pdata) \ - dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \ - IRQ_DB5500_SPI1, pdata, \ - 0x10080023) -#define db5500_add_spi2(parent, pdata) \ - dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \ - IRQ_DB5500_SPI2, pdata \ - 0x10080023) -#define db5500_add_spi3(parent, pdata) \ - dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \ - IRQ_DB5500_SPI3, pdata \ - 0x10080023) - -#define db5500_add_uart0(parent, plat) \ - dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \ - IRQ_DB5500_UART0, plat) -#define db5500_add_uart1(parent, plat) \ - dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \ - IRQ_DB5500_UART1, plat) -#define db5500_add_uart2(parent, plat) \ - dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \ - IRQ_DB5500_UART2, plat) -#define db5500_add_uart3(parent, plat) \ - dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \ - IRQ_DB5500_UART3, plat) - -#endif diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index 9fd93e9da529..6fc7eb24d9a0 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -31,7 +31,7 @@ static inline struct amba_device * db8500_add_ssp(struct device *parent, const char *name, resource_size_t base, int irq, struct pl022_ssp_controller *pdata) { - return dbx500_add_amba_device(parent, name, base, irq, pdata, 0); + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); } diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c deleted file mode 100644 index 41e9470fa0e6..000000000000 --- a/arch/arm/mach-ux500/dma-db5500.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson - * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson - * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson - * - * License terms: GNU General Public License (GPL), version 2 - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <plat/ste_dma40.h> -#include <mach/setup.h> -#include <mach/hardware.h> - -#include "ste-dma40-db5500.h" - -static struct resource dma40_resources[] = { - [0] = { - .start = U5500_DMA_BASE, - .end = U5500_DMA_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - .name = "base", - }, - [1] = { - .start = U5500_DMA_LCPA_BASE, - .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - .name = "lcpa", - }, - [2] = { - .start = IRQ_DB5500_DMA, - .end = IRQ_DB5500_DMA, - .flags = IORESOURCE_IRQ - } -}; - -/* Default configuration for physical memcpy */ -static struct stedma40_chan_cfg dma40_memcpy_conf_phy = { - .mode = STEDMA40_MODE_PHYSICAL, - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_PHY_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_PHY_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* Default configuration for logical memcpy */ -static struct stedma40_chan_cfg dma40_memcpy_conf_log = { - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_LOG_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_LOG_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* - * Mapping between soruce event lines and physical device address This was - * created assuming that the event line is tied to a device and therefore the - * address is constant, however this is not true for at least USB, and the - * values are just placeholders for USB. This table is preserved and used for - * now. - */ -static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = { - [DB5500_DMA_DEV24_SDMMC0_RX] = -1, - [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1, - [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1, - [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1, - [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1, - [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1, - [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1, - [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1, - [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1, -}; - -/* Mapping between destination event lines and physical device address */ -static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = { - [DB5500_DMA_DEV24_SDMMC0_TX] = -1, - [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1, - [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1, - [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1, - [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1, - [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1, - [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1, - [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1, - [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1, -}; - -static int dma40_memcpy_event[] = { - DB5500_DMA_MEMCPY_TX_1, - DB5500_DMA_MEMCPY_TX_2, - DB5500_DMA_MEMCPY_TX_3, - DB5500_DMA_MEMCPY_TX_4, - DB5500_DMA_MEMCPY_TX_5, -}; - -static struct stedma40_platform_data dma40_plat_data = { - .dev_len = ARRAY_SIZE(dma40_rx_map), - .dev_rx = dma40_rx_map, - .dev_tx = dma40_tx_map, - .memcpy = dma40_memcpy_event, - .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), - .memcpy_conf_phy = &dma40_memcpy_conf_phy, - .memcpy_conf_log = &dma40_memcpy_conf_log, - .disabled_channels = {-1}, -}; - -static struct platform_device dma40_device = { - .dev = { - .platform_data = &dma40_plat_data, - }, - .name = "dma40", - .id = 0, - .num_resources = ARRAY_SIZE(dma40_resources), - .resource = dma40_resources -}; - -void __init db5500_dma_init(struct device *parent) -{ - int ret; - - dma40_device.dev.parent = parent; - ret = platform_device_register(&dma40_device); - if (ret) - dev_err(&dma40_device.dev, "unable to register device: %d\n", ret); - -} diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h deleted file mode 100644 index 8e714bcb099f..000000000000 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_DB5500_REGS_H -#define __MACH_DB5500_REGS_H - -#define U5500_PER1_BASE 0xA0020000 -#define U5500_PER2_BASE 0xA0010000 -#define U5500_PER3_BASE 0x80140000 -#define U5500_PER4_BASE 0x80150000 -#define U5500_PER5_BASE 0x80100000 -#define U5500_PER6_BASE 0x80120000 - -#define U5500_GIC_DIST_BASE 0xA0411000 -#define U5500_GIC_CPU_BASE 0xA0410100 -#define U5500_DMA_BASE 0x90030000 -#define U5500_STM_BASE 0x90020000 -#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000) -#define U5500_MCDE_BASE 0xA0400000 -#define U5500_MODEM_BASE 0xB0000000 -#define U5500_L2CC_BASE 0xA0412000 -#define U5500_SCU_BASE 0xA0410000 -#define U5500_DSI1_BASE 0xA0401000 -#define U5500_DSI2_BASE 0xA0402000 -#define U5500_SIA_BASE 0xA0100000 -#define U5500_SVA_BASE 0x80200000 -#define U5500_HSEM_BASE 0xA0000000 -#define U5500_NAND0_BASE 0x60000000 -#define U5500_NAND1_BASE 0x70000000 -#define U5500_TWD_BASE 0xa0410600 -#define U5500_ICN_BASE 0xA0040000 -#define U5500_B2R2_BASE 0xa0200000 -#define U5500_BOOT_ROM_BASE 0x90000000 - -#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) -#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) -#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) -#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) -#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) -#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) -#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) -#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) - -#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) -#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) -#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) - -#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) -#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) -#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) -#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) - -#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) -#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) -#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) -#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) -#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) -#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) -#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) -#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) -#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) -#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) -#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) -#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) -#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000) -#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) -#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) -#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000) -#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000) - -#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) -#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) -#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) -#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) -#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) -#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) -#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) -#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) -#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) -#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) -#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) -#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) -#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) -#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) -#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) -#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) -#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) - -#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) -#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) -#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) -#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) -#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100) -#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) -#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) -#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) -#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) -#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) -#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) - -#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE -#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80) -#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE -#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE -#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE -#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE -#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) -#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) - -#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000) -#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40) -#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F) -#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60) -#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F) -#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80) -#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F) -#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0) -#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF) -#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00) -#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F) -#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) -#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) - -#define U5500_ACCCON_BASE_SEC (0xBFFF0000) -#define U5500_ACCCON_BASE (0xBFFF1000) -#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) -#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) -#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4) - -#define U5500_ESRAM_BASE 0x40000000 -#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 -#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) - -#define U5500_MCDE_SIZE 0x1000 -#define U5500_DSI_LINK_SIZE 0x1000 -#define U5500_DSI_LINK_COUNT 0x2 -#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE) -#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE) - -#endif diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index 8d74d927d4e2..67035223334a 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -20,10 +20,6 @@ * built, so that there's some hint during the build that something is wrong. */ -#ifdef CONFIG_UX500_SOC_DB5500 -#define __UX500_UART(n) U5500_UART##n##_BASE -#endif - #ifdef CONFIG_UX500_SOC_DB8500 #define __UX500_UART(n) U8500_UART##n##_BASE #endif diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 5f6cb71fc62d..9b5eb69a0154 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -10,7 +10,6 @@ struct platform_device; struct amba_device; -extern struct platform_device u5500_gpio_devs[]; extern struct platform_device u8500_gpio_devs[]; extern struct amba_device ux500_pl031_device; diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index f84698936d36..cf6fac3d1eeb 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -28,7 +28,6 @@ #define io_p2v(n) __io_address(n) #include <mach/db8500-regs.h> -#include <mach/db5500-regs.h> #define MSP_TX_RX_REG_OFFSET 0 diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h deleted file mode 100644 index 29d972c7717b..000000000000 --- a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_BOARD_U5500_H -#define __MACH_IRQS_BOARD_U5500_H - -#define AB5500_NR_IRQS 5 -#define IRQ_AB5500_BASE IRQ_BOARD_START -#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS) - -#define U5500_IRQ_END IRQ_AB5500_END - -#if IRQ_BOARD_END < U5500_IRQ_END -#undef IRQ_BOARD_END -#define IRQ_BOARD_END U5500_IRQ_END -#endif - -#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h deleted file mode 100644 index 77239776a6f2..000000000000 --- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_DB5500_H -#define __MACH_IRQS_DB5500_H - -#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4) -#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6) -#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7) -#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8) -#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9) -#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10) -#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11) -#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12) -#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13) -#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14) -#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15) -#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16) -#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17) -#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18) -#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19) -#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20) -#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21) -#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22) -#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23) -#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24) -#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25) -#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26) -#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27) -#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28) -#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29) -#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30) -#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31) -#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33) -#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34) -#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35) -#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36) -#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37) -#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38) -#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39) -#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40) -#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41) -#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42) -#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43) -#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44) -#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45) -#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46) -#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47) -#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48) -#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50) -#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52) -#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53) -#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55) -#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56) -#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57) -#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59) -#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) -#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) -#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) -#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65) -#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) -#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) -#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) -#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108) -#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109) -#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110) -#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112) -#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113) -#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114) -#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115) -#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116) -#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118) -#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119) -#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120) -#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121) -#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122) -#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123) -#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124) -#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) -#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) - -#ifdef CONFIG_UX500_SOC_DB5500 - -/* - * After the GPIO ones we reserve a range of IRQ:s in which virtual - * IRQ:s representing modem IRQ:s can be allocated - */ -#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START -#define IRQ_MODEM_EVENTS_NBR 72 -#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR) - -/* List of virtual IRQ:s that are allocated from the range above */ -#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43) -#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45) -#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41) - -/* - * We may have several SoCs, but only one will run at a - * time, so the one with most IRQs will bump this ahead, - * but the IRQ_SOC_START remains the same for either SoC. - */ -#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END -#undef IRQ_SOC_END -#define IRQ_SOC_END IRQ_MODEM_EVENTS_END -#endif - -#endif /* CONFIG_UX500_SOC_DB5500 */ - -#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index c23a6b5f0c4e..d06dcf6208fa 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -36,7 +36,6 @@ /* This will be overridden by SoC-specific irq headers */ #define IRQ_SOC_END IRQ_SOC_START -#include <mach/irqs-db5500.h> #include <mach/irqs-db8500.h> #define IRQ_BOARD_START IRQ_SOC_END @@ -47,10 +46,6 @@ #include <mach/irqs-board-mop500.h> #endif -#ifdef CONFIG_MACH_U5500 -#include <mach/irqs-board-u5500.h> -#endif - #define NR_IRQS IRQ_BOARD_END #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h deleted file mode 100644 index 7f9da4d2fbda..000000000000 --- a/arch/arm/mach-ux500/include/mach/mbox-db5500.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __INC_STE_MBOX_H -#define __INC_STE_MBOX_H - -#define MBOX_BUF_SIZE 16 -#define MBOX_NAME_SIZE 8 - -/** - * mbox_recv_cb_t - Definition of the mailbox callback. - * @mbox_msg: The mailbox message. - * @priv: The clients private data as specified in the call to mbox_setup. - * - * This function will be called upon reception of new mailbox messages. - */ -typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv); - -/** - * struct mbox - Mailbox instance struct - * @list: Linked list head. - * @pdev: Pointer to device struct. - * @cb: Callback function. Will be called - * when new data is received. - * @client_data: Clients private data. Will be sent back - * in the callback function. - * @virtbase_peer: Virtual address for outgoing mailbox. - * @virtbase_local: Virtual address for incoming mailbox. - * @buffer: Then internal queue for outgoing messages. - * @name: Name of this mailbox. - * @buffer_available: Completion variable to achieve "blocking send". - * This variable will be signaled when there is - * internal buffer space available. - * @client_blocked: To keep track if any client is currently - * blocked. - * @lock: Spinlock to protect this mailbox instance. - * @write_index: Index in internal buffer to write to. - * @read_index: Index in internal buffer to read from. - * @allocated: Indicates whether this particular mailbox - * id has been allocated by someone. - */ -struct mbox { - struct list_head list; - struct platform_device *pdev; - mbox_recv_cb_t *cb; - void *client_data; - void __iomem *virtbase_peer; - void __iomem *virtbase_local; - u32 buffer[MBOX_BUF_SIZE]; - char name[MBOX_NAME_SIZE]; - struct completion buffer_available; - u8 client_blocked; - spinlock_t lock; - u8 write_index; - u8 read_index; - bool allocated; -}; - -/** - * mbox_setup - Set up a mailbox and return its instance. - * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU, - * 2 for modem DSP. - * @mbox_cb: Pointer to the callback function to be called when a new message - * is received. - * @priv: Client user data which will be returned in the callback. - * - * Returns a mailbox instance to be specified in subsequent calls to mbox_send. - */ -struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv); - -/** - * mbox_send - Send a mailbox message. - * @mbox: Mailbox instance (returned by mbox_setup) - * @mbox_msg: The mailbox message to send. - * @block: Specifies whether this call will block until send is possible, - * or return an error if the mailbox buffer is full. - * - * Returns 0 on success or a negative error code on error. -ENOMEM indicates - * that the internal buffer is full and you have to try again later (or - * specify "block" in order to block until send is possible). - */ -int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block); - -#endif /*INC_STE_MBOX_H*/ diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index 3dc00ffa7bfa..4e369f1645ec 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -15,18 +15,12 @@ #include <linux/init.h> void __init ux500_map_io(void); -extern void __init u5500_map_io(void); extern void __init u8500_map_io(void); -extern struct device * __init u5500_init_devices(void); extern struct device * __init u8500_init_devices(void); extern void __init ux500_init_irq(void); -extern void __init u5500_sdi_init(struct device *parent); - -extern void __init db5500_dma_init(struct device *parent); - extern struct device *ux500_soc_device_init(const char *soc_id); struct amba_device; diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 6fb3c4b0105d..34775baadaea 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -50,11 +50,8 @@ static void flush(void) static inline void arch_decomp_setup(void) { - /* Check in run time if we run on an U8500 or U5500 */ - if (machine_is_u5500()) - ux500_uart_base = U5500_UART0_BASE; - else - ux500_uart_base = U8500_UART2_BASE; + /* Use machine_is_foo() macro if you need to switch base someday */ + ux500_uart_base = U8500_UART2_BASE; } #define arch_decomp_wdog() /* nothing to do here */ diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c deleted file mode 100644 index 0127490218cd..000000000000 --- a/arch/arm/mach-ux500/mbox-db5500.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -/* - * Mailbox nomenclature: - * - * APE MODEM - * mbox pairX - * .......................... - * . . - * . peer . - * . send ---- . - * . --> | | . - * . | | . - * . ---- . - * . . - * . local . - * . rec ---- . - * . | | <-- . - * . | | . - * . ---- . - * ......................... - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/completion.h> -#include <mach/mbox-db5500.h> - -#define MBOX_NAME "mbox" - -#define MBOX_FIFO_DATA 0x000 -#define MBOX_FIFO_ADD 0x004 -#define MBOX_FIFO_REMOVE 0x008 -#define MBOX_FIFO_THRES_FREE 0x00C -#define MBOX_FIFO_THRES_OCCUP 0x010 -#define MBOX_FIFO_STATUS 0x014 - -#define MBOX_DISABLE_IRQ 0x4 -#define MBOX_ENABLE_IRQ 0x0 -#define MBOX_LATCH 1 - -/* Global list of all mailboxes */ -static struct list_head mboxs = LIST_HEAD_INIT(mboxs); - -static struct mbox *get_mbox_with_id(u8 id) -{ - u8 i; - struct list_head *pos = &mboxs; - for (i = 0; i <= id; i++) - pos = pos->next; - - return (struct mbox *) list_entry(pos, struct mbox, list); -} - -int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block) -{ - int res = 0; - - spin_lock(&mbox->lock); - - dev_dbg(&(mbox->pdev->dev), - "About to buffer 0x%X to mailbox 0x%X." - " ri = %d, wi = %d\n", - mbox_msg, (u32)mbox, mbox->read_index, - mbox->write_index); - - /* Check if write buffer is full */ - while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) { - if (!block) { - dev_dbg(&(mbox->pdev->dev), - "Buffer full in non-blocking call! " - "Returning -ENOMEM!\n"); - res = -ENOMEM; - goto exit; - } - spin_unlock(&mbox->lock); - dev_dbg(&(mbox->pdev->dev), - "Buffer full in blocking call! Sleeping...\n"); - mbox->client_blocked = 1; - wait_for_completion(&mbox->buffer_available); - dev_dbg(&(mbox->pdev->dev), - "Blocking send was woken up! Trying again...\n"); - spin_lock(&mbox->lock); - } - - mbox->buffer[mbox->write_index] = mbox_msg; - mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE; - - /* - * Indicate that we want an IRQ as soon as there is a slot - * in the FIFO - */ - writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - -exit: - spin_unlock(&mbox->lock); - return res; -} -EXPORT_SYMBOL(mbox_send); - -#if defined(CONFIG_DEBUG_FS) -/* - * Expected input: <value> <nbr sends> - * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times - */ -static ssize_t mbox_write_fifo(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - unsigned long mbox_mess; - unsigned long nbr_sends; - unsigned long i; - char int_buf[16]; - char *token; - char *val; - - struct mbox *mbox = (struct mbox *) dev->platform_data; - - strncpy((char *) &int_buf, buf, sizeof(int_buf)); - token = (char *) &int_buf; - - /* Parse message */ - val = strsep(&token, " "); - if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0)) - mbox_mess = 0xDEADBEEF; - - val = strsep(&token, " "); - if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0)) - nbr_sends = 1; - - dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n", - mbox_mess, nbr_sends, (u32) mbox); - - for (i = 0; i < nbr_sends; i++) - mbox_send(mbox, mbox_mess, true); - - return count; -} - -static ssize_t mbox_read_fifo(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - int mbox_value; - struct mbox *mbox = (struct mbox *) dev->platform_data; - - if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0) - return sprintf(buf, "Mailbox is empty\n"); - - mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); - writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); - - return sprintf(buf, "0x%X\n", mbox_value); -} - -static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo); - -static int mbox_show(struct seq_file *s, void *data) -{ - struct list_head *pos; - u8 mbox_index = 0; - - list_for_each(pos, &mboxs) { - struct mbox *m = - (struct mbox *) list_entry(pos, struct mbox, list); - if (m == NULL) { - seq_printf(s, - "Unable to retrieve mailbox %d\n", - mbox_index); - continue; - } - - spin_lock(&m->lock); - if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) { - seq_printf(s, "MAILBOX %d not setup or corrupt\n", - mbox_index); - spin_unlock(&m->lock); - continue; - } - - seq_printf(s, - "===========================\n" - " MAILBOX %d\n" - " PEER MAILBOX DUMP\n" - "---------------------------\n" - "FIFO: 0x%X (%d)\n" - "Free Threshold: 0x%.2X (%d)\n" - "Occupied Threshold: 0x%.2X (%d)\n" - "Status: 0x%.2X (%d)\n" - " Free spaces (ot): %d (%d)\n" - " Occup spaces (ot): %d (%d)\n" - "===========================\n" - " LOCAL MAILBOX DUMP\n" - "---------------------------\n" - "FIFO: 0x%.X (%d)\n" - "Free Threshold: 0x%.2X (%d)\n" - "Occupied Threshold: 0x%.2X (%d)\n" - "Status: 0x%.2X (%d)\n" - " Free spaces (ot): %d (%d)\n" - " Occup spaces (ot): %d (%d)\n" - "===========================\n" - "write_index: %d\n" - "read_index : %d\n" - "===========================\n" - "\n", - mbox_index, - readl(m->virtbase_peer + MBOX_FIFO_DATA), - readl(m->virtbase_peer + MBOX_FIFO_DATA), - readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_peer + MBOX_FIFO_STATUS), - readl(m->virtbase_peer + MBOX_FIFO_STATUS), - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1, - readl(m->virtbase_local + MBOX_FIFO_DATA), - readl(m->virtbase_local + MBOX_FIFO_DATA), - readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_local + MBOX_FIFO_STATUS), - readl(m->virtbase_local + MBOX_FIFO_STATUS), - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1, - m->write_index, m->read_index); - mbox_index++; - spin_unlock(&m->lock); - } - - return 0; -} - -static int mbox_open(struct inode *inode, struct file *file) -{ - return single_open(file, mbox_show, NULL); -} - -static const struct file_operations mbox_operations = { - .owner = THIS_MODULE, - .open = mbox_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif - -static irqreturn_t mbox_irq(int irq, void *arg) -{ - u32 mbox_value; - int nbr_occup; - int nbr_free; - struct mbox *mbox = (struct mbox *) arg; - - spin_lock(&mbox->lock); - - dev_dbg(&(mbox->pdev->dev), - "mbox IRQ [%d] received. ri = %d, wi = %d\n", - irq, mbox->read_index, mbox->write_index); - - /* - * Check if we have any outgoing messages, and if there is space for - * them in the FIFO. - */ - if (mbox->read_index != mbox->write_index) { - /* - * Check by reading FREE for LOCAL since that indicates - * OCCUP for PEER - */ - nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS) - >> 4) & 0x7; - dev_dbg(&(mbox->pdev->dev), - "Status indicates %d empty spaces in the FIFO!\n", - nbr_free); - - while ((nbr_free > 0) && - (mbox->read_index != mbox->write_index)) { - /* Write the message and latch it into the FIFO */ - writel(mbox->buffer[mbox->read_index], - (mbox->virtbase_peer + MBOX_FIFO_DATA)); - writel(MBOX_LATCH, - (mbox->virtbase_peer + MBOX_FIFO_ADD)); - dev_dbg(&(mbox->pdev->dev), - "Wrote message 0x%X to addr 0x%X\n", - mbox->buffer[mbox->read_index], - (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA)); - - nbr_free--; - mbox->read_index = - (mbox->read_index + 1) % MBOX_BUF_SIZE; - } - - /* - * Check if we still want IRQ:s when there is free - * space to send - */ - if (mbox->read_index != mbox->write_index) { - dev_dbg(&(mbox->pdev->dev), - "Still have messages to send, but FIFO full. " - "Request IRQ again!\n"); - writel(MBOX_ENABLE_IRQ, - mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - } else { - dev_dbg(&(mbox->pdev->dev), - "No more messages to send. " - "Do not request IRQ again!\n"); - writel(MBOX_DISABLE_IRQ, - mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - } - - /* - * Check if we can signal any blocked clients that it is OK to - * start buffering again - */ - if (mbox->client_blocked && - (((mbox->write_index + 1) % MBOX_BUF_SIZE) - != mbox->read_index)) { - dev_dbg(&(mbox->pdev->dev), - "Waking up blocked client\n"); - complete(&mbox->buffer_available); - mbox->client_blocked = 0; - } - } - - /* Check if we have any incoming messages */ - nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7; - if (nbr_occup == 0) - goto exit; - - if (mbox->cb == NULL) { - dev_dbg(&(mbox->pdev->dev), "No receive callback registered, " - "leaving %d incoming messages in fifo!\n", nbr_occup); - goto exit; - } - - /* Read and acknowledge the message */ - mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); - writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); - - /* Notify consumer of new mailbox message */ - dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n", - mbox_value); - mbox->cb(mbox_value, mbox->client_data); - -exit: - dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n", - mbox->read_index, mbox->write_index); - spin_unlock(&mbox->lock); - - return IRQ_HANDLED; -} - -/* Setup is executed once for each mbox pair */ -struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) -{ - struct resource *resource; - int irq; - int res; - struct mbox *mbox; - - mbox = get_mbox_with_id(mbox_id); - if (mbox == NULL) { - dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n", - mbox_id); - goto exit; - } - - /* - * Check if mailbox has been allocated to someone else, - * otherwise allocate it - */ - if (mbox->allocated) { - dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n", - mbox_id); - mbox = NULL; - goto exit; - } - mbox->allocated = true; - - dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n", - mbox_id, (u32)mbox); - - mbox->client_data = priv; - mbox->cb = mbox_cb; - - /* Get addr for peer mailbox and ioremap it */ - resource = platform_get_resource_byname(mbox->pdev, - IORESOURCE_MEM, - "mbox_peer"); - if (resource == NULL) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox peer resource\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "Resource name: %s start: 0x%X, end: 0x%X\n", - resource->name, resource->start, resource->end); - mbox->virtbase_peer = ioremap(resource->start, resource_size(resource)); - if (!mbox->virtbase_peer) { - dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n", - resource->start, resource->end, (u32) mbox->virtbase_peer); - - /* Get addr for local mailbox and ioremap it */ - resource = platform_get_resource_byname(mbox->pdev, - IORESOURCE_MEM, - "mbox_local"); - if (resource == NULL) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox local resource\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "Resource name: %s start: 0x%X, end: 0x%X\n", - resource->name, resource->start, resource->end); - mbox->virtbase_local = ioremap(resource->start, resource_size(resource)); - if (!mbox->virtbase_local) { - dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n", - resource->start, resource->end, (u32) mbox->virtbase_peer); - - init_completion(&mbox->buffer_available); - mbox->client_blocked = 0; - - /* Get IRQ for mailbox and allocate it */ - irq = platform_get_irq_byname(mbox->pdev, "mbox_irq"); - if (irq < 0) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox irq resource\n"); - mbox = NULL; - goto exit; - } - - dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq); - res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox); - if (res < 0) { - dev_err(&(mbox->pdev->dev), - "Unable to allocate mbox irq %d\n", irq); - mbox = NULL; - goto exit; - } - - /* Set up mailbox to not launch IRQ on free space in mailbox */ - writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - - /* - * Set up mailbox to launch IRQ on new message if we have - * a callback set. If not, do not raise IRQ, but keep message - * in FIFO for manual retrieval - */ - if (mbox_cb != NULL) - writel(MBOX_ENABLE_IRQ, - mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); - else - writel(MBOX_DISABLE_IRQ, - mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); - -#if defined(CONFIG_DEBUG_FS) - res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo); - if (res != 0) - dev_warn(&(mbox->pdev->dev), - "Unable to create mbox sysfs entry"); - - (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL, - NULL, &mbox_operations); -#endif - - dev_info(&(mbox->pdev->dev), - "Mailbox driver with index %d initiated!\n", mbox_id); - -exit: - return mbox; -} -EXPORT_SYMBOL(mbox_setup); - - -int __init mbox_probe(struct platform_device *pdev) -{ - struct mbox local_mbox; - struct mbox *mbox; - int res = 0; - dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev); - - memset(&local_mbox, 0x0, sizeof(struct mbox)); - - /* Associate our mbox data with the platform device */ - res = platform_device_add_data(pdev, - (void *) &local_mbox, - sizeof(struct mbox)); - if (res != 0) { - dev_err(&(pdev->dev), - "Unable to allocate driver platform data!\n"); - goto exit; - } - - mbox = (struct mbox *) pdev->dev.platform_data; - mbox->pdev = pdev; - mbox->write_index = 0; - mbox->read_index = 0; - - INIT_LIST_HEAD(&(mbox->list)); - list_add_tail(&(mbox->list), &mboxs); - - sprintf(mbox->name, "%s", MBOX_NAME); - spin_lock_init(&mbox->lock); - - dev_info(&(pdev->dev), "Mailbox driver loaded\n"); - -exit: - return res; -} - -static struct platform_driver mbox_driver = { - .driver = { - .name = MBOX_NAME, - .owner = THIS_MODULE, - }, -}; - -static int __init mbox_init(void) -{ - return platform_driver_probe(&mbox_driver, mbox_probe); -} - -module_init(mbox_init); - -void __exit mbox_exit(void) -{ - platform_driver_unregister(&mbox_driver); -} - -module_exit(mbox_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("MBOX driver"); diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c deleted file mode 100644 index 6b86416c94c9..000000000000 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/slab.h> - -#include <mach/id.h> - -#define MODEM_INTCON_BASE_ADDR 0xBFFD3000 -#define MODEM_INTCON_SIZE 0xFFF - -#define DEST_IRQ41_OFFSET 0x2A4 -#define DEST_IRQ43_OFFSET 0x2AC -#define DEST_IRQ45_OFFSET 0x2B4 - -#define PRIO_IRQ41_OFFSET 0x6A4 -#define PRIO_IRQ43_OFFSET 0x6AC -#define PRIO_IRQ45_OFFSET 0x6B4 - -#define ALLOW_IRQ_OFFSET 0x104 - -#define MODEM_INTCON_CPU_NBR 0x1 -#define MODEM_INTCON_PRIO_HIGH 0x0 - -#define MODEM_INTCON_ALLOW_IRQ41 0x0200 -#define MODEM_INTCON_ALLOW_IRQ43 0x0800 -#define MODEM_INTCON_ALLOW_IRQ45 0x2000 - -#define MODEM_IRQ_REG_OFFSET 0x4 - -struct modem_irq { - void __iomem *modem_intcon_base; -}; - - -static void setup_modem_intcon(void __iomem *modem_intcon_base) -{ - /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */ - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET); - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET); - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET); - - /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */ - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET); - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET); - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET); - - /* IC_ALLOW_ARRAY - IRQ enable */ - writel(MODEM_INTCON_ALLOW_IRQ41 | - MODEM_INTCON_ALLOW_IRQ43 | - MODEM_INTCON_ALLOW_IRQ45, - modem_intcon_base + ALLOW_IRQ_OFFSET); -} - -static irqreturn_t modem_cpu_irq_handler(int irq, void *data) -{ - int real_irq; - int virt_irq; - struct modem_irq *mi = (struct modem_irq *)data; - - /* Read modem side IRQ number from modem IRQ controller */ - real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF; - virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq; - - pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X " - "which will be 0x%X (%d) which translates to " - "virtual IRQ 0x%X (%d)!\n", - (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET, - real_irq, - real_irq & 0xFF, - real_irq & 0xFF, - virt_irq, - virt_irq); - - if (virt_irq != 0) - generic_handle_irq(virt_irq); - - pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq); - - return IRQ_HANDLED; -} - -static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) -{ - irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - - pr_debug("modem_irq: Created virtual IRQ %d\n", irq); -} - -static int modem_irq_init(void) -{ - int err; - static struct irq_chip modem_irq_chip; - struct modem_irq *mi; - - if (!cpu_is_u5500()) - return -ENODEV; - - pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n", - IRQ_DB5500_MODEM); - - mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL); - if (!mi) { - pr_err("modem_irq: Could not allocate device\n"); - return -ENOMEM; - } - - mi->modem_intcon_base = - ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE); - pr_debug("modem_irq: ioremapped modem_intcon_base from " - "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR, - (u32)mi->modem_intcon_base); - - setup_modem_intcon(mi->modem_intcon_base); - - modem_irq_chip = dummy_irq_chip; - modem_irq_chip.name = "modem_irq"; - - /* Create the virtual IRQ:s needed */ - create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip); - create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip); - create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip); - - err = request_threaded_irq(IRQ_DB5500_MODEM, NULL, - modem_cpu_irq_handler, IRQF_ONESHOT, - "modem_irq", mi); - if (err) - pr_err("modem_irq: Could not register IRQ %d\n", - IRQ_DB5500_MODEM); - - return 0; -} - -arch_initcall(modem_irq_init); diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h deleted file mode 100644 index bf50c21fe69d..000000000000 --- a/arch/arm/mach-ux500/pins-db5500.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License, version 2 - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - */ - -#ifndef __MACH_DB5500_PINS_H -#define __MACH_DB5500_PINS_H - -#define GPIO0_GPIO PIN_CFG(0, GPIO) -#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A) - -#define GPIO1_GPIO PIN_CFG(1, GPIO) -#define GPIO1_SM_A3 PIN_CFG(1, ALT_A) - -#define GPIO2_GPIO PIN_CFG(2, GPIO) -#define GPIO2_SM_A4 PIN_CFG(2, ALT_A) -#define GPIO2_SM_AVD PIN_CFG(2, ALT_B) - -#define GPIO3_GPIO PIN_CFG(3, GPIO) -#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A) - -#define GPIO4_GPIO PIN_CFG(4, GPIO) -#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A) - -#define GPIO5_GPIO PIN_CFG(5, GPIO) -#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A) -#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B) - -#define GPIO6_GPIO PIN_CFG(6, GPIO) -#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A) -#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B) - -#define GPIO7_GPIO PIN_CFG(7, GPIO) -#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A) -#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B) - -#define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A) -#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B) - -#define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A) -#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B) - -#define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A) -#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B) - -#define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A) -#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B) - -#define GPIO12_GPIO PIN_CFG(12, GPIO) -#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A) -#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B) - -#define GPIO13_GPIO PIN_CFG(13, GPIO) -#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A) -#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B) -#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C) - -#define GPIO14_GPIO PIN_CFG(14, GPIO) -#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A) -#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B) -#define GPIO14_SM_CKO PIN_CFG(14, ALT_C) - -#define GPIO15_GPIO PIN_CFG(15, GPIO) -#define GPIO15_SM_A5 PIN_CFG(15, ALT_A) -#define GPIO15_SM_CLE PIN_CFG(15, ALT_B) - -#define GPIO16_GPIO PIN_CFG(16, GPIO) -#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A) -#define GPIO16_SM_OEn PIN_CFG(16, ALT_B) - -#define GPIO17_GPIO PIN_CFG(17, GPIO) -#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A) -#define GPIO17_SM_WEn PIN_CFG(17, ALT_B) - -#define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_SM_A6 PIN_CFG(18, ALT_A) -#define GPIO18_SM_ALE PIN_CFG(18, ALT_B) -#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C) - -#define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A) -#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B) - -#define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A) -#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B) - -#define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A) -#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B) - -#define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A) -#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B) - -#define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A) -#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B) -#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C) - -#define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A) -#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B) -#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C) - -#define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A) -#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B) -#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C) - -#define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A) -#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B) - -#define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A) -#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B) - -#define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_U0_TXD PIN_CFG(28, ALT_A) -#define GPIO28_SM_A0 PIN_CFG(28, ALT_B) - -#define GPIO29_GPIO PIN_CFG(29, GPIO) -#define GPIO29_U0_RXD PIN_CFG(29, ALT_A) -#define GPIO29_SM_A1 PIN_CFG(29, ALT_B) -#define GPIO29_PWM_0 PIN_CFG(29, ALT_C) - -#define GPIO30_GPIO PIN_CFG(30, GPIO) -#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) -#define GPIO30_SM_A2 PIN_CFG(30, ALT_B) -#define GPIO30_PWM_1 PIN_CFG(30, ALT_C) - -#define GPIO31_GPIO PIN_CFG(31, GPIO) -#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A) -#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B) -#define GPIO31_PWM_2 PIN_CFG(31, ALT_C) - -#define GPIO32_GPIO PIN_CFG(32, GPIO) -#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A) -#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B) - -#define GPIO33_GPIO PIN_CFG(33, GPIO) -#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A) -#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B) - -#define GPIO34_GPIO PIN_CFG(34, GPIO) -#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A) -#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B) - -#define GPIO35_GPIO PIN_CFG(35, GPIO) -#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A) -#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B) - -#define GPIO64_GPIO PIN_CFG(64, GPIO) -#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A) -#define GPIO64_U0_TXD PIN_CFG(64, ALT_B) - -#define GPIO65_GPIO PIN_CFG(65, GPIO) -#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A) -#define GPIO65_U0_RXD PIN_CFG(65, ALT_B) - -#define GPIO66_GPIO PIN_CFG(66, GPIO) -#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A) - -#define GPIO67_GPIO PIN_CFG(67, GPIO) -#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A) - -#define GPIO68_GPIO PIN_CFG(68, GPIO) -#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A) - -#define GPIO69_GPIO PIN_CFG(69, GPIO) -#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A) - -#define GPIO70_GPIO PIN_CFG(70, GPIO) -#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A) - -#define GPIO71_GPIO PIN_CFG(71, GPIO) -#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A) - -#define GPIO72_GPIO PIN_CFG(72, GPIO) -#define GPIO72_USB_STP PIN_CFG(72, ALT_A) - -#define GPIO73_GPIO PIN_CFG(73, GPIO) -#define GPIO73_USB_DIR PIN_CFG(73, ALT_A) - -#define GPIO74_GPIO PIN_CFG(74, GPIO) -#define GPIO74_USB_NXT PIN_CFG(74, ALT_A) - -#define GPIO75_GPIO PIN_CFG(75, GPIO) -#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A) - -#define GPIO76_GPIO PIN_CFG(76, GPIO) - -#define GPIO77_GPIO PIN_CFG(77, GPIO) -#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A) - -#define GPIO78_GPIO PIN_CFG(78, GPIO) -#define GPIO78_IRQn PIN_CFG(78, ALT_A) - -#define GPIO79_GPIO PIN_CFG(79, GPIO) -#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A) - -#define GPIO80_GPIO PIN_CFG(80, GPIO) -#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A) - -#define GPIO81_GPIO PIN_CFG(81, GPIO) -#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A) - -#define GPIO82_GPIO PIN_CFG(82, GPIO) -#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A) - -#define GPIO96_GPIO PIN_CFG(96, GPIO) -#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A) -#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B) -#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C) - -#define GPIO97_GPIO PIN_CFG(97, GPIO) -#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A) -#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B) -#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C) - -#define GPIO98_GPIO PIN_CFG(98, GPIO) -#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A) -#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B) -#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C) - -#define GPIO99_GPIO PIN_CFG(99, GPIO) -#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A) -#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B) -#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C) - -#define GPIO100_GPIO PIN_CFG(100, GPIO) -#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A) - -#define GPIO101_GPIO PIN_CFG(101, GPIO) -#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A) - -#define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_KP_I0 PIN_CFG(128, ALT_A) -#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B) - -#define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_KP_O0 PIN_CFG(129, ALT_A) -#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B) - -#define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_KP_I1 PIN_CFG(130, ALT_A) -#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B) - -#define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_KP_O1 PIN_CFG(131, ALT_A) -#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B) - -#define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_KP_I2 PIN_CFG(132, ALT_A) -#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B) -#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C) - -#define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_KP_O2 PIN_CFG(133, ALT_A) -#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B) -#define GPIO133_U0_RXD PIN_CFG(133, ALT_C) - -#define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_KP_I3 PIN_CFG(134, ALT_A) -#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B) -#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C) - -#define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_KP_O3 PIN_CFG(135, ALT_A) -#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B) -#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C) - -#define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_KP_I4 PIN_CFG(136, ALT_A) -#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B) -#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C) - -#define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_KP_O4 PIN_CFG(137, ALT_A) -#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B) -#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C) - -#define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_KP_I5 PIN_CFG(138, ALT_A) -#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B) -#define GPIO138_U0_TXD PIN_CFG(138, ALT_C) - -#define GPIO139_GPIO PIN_CFG(139, GPIO) -#define GPIO139_KP_O5 PIN_CFG(139, ALT_A) -#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B) -#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C) - -#define GPIO140_GPIO PIN_CFG(140, GPIO) -#define GPIO140_KP_I6 PIN_CFG(140, ALT_A) -#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B) -#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C) - -#define GPIO141_GPIO PIN_CFG(141, GPIO) -#define GPIO141_KP_O6 PIN_CFG(141, ALT_A) -#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B) -#define GPIO141_U0_RXD PIN_CFG(141, ALT_C) - -#define GPIO142_GPIO PIN_CFG(142, GPIO) -#define GPIO142_KP_I7 PIN_CFG(142, ALT_A) -#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B) -#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C) - -#define GPIO143_GPIO PIN_CFG(143, GPIO) -#define GPIO143_KP_O7 PIN_CFG(143, ALT_A) -#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B) -#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C) - -#define GPIO144_GPIO PIN_CFG(144, GPIO) -#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A) -#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B) -#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C) - -#define GPIO145_GPIO PIN_CFG(145, GPIO) -#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A) -#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B) -#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C) - -#define GPIO146_GPIO PIN_CFG(146, GPIO) -#define GPIO146_PWM_0 PIN_CFG(146, ALT_A) -#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B) - -#define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_PWM_1 PIN_CFG(147, ALT_A) -#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B) - -#define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_PWM_2 PIN_CFG(148, ALT_A) -#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B) - -#define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A) - -#define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A) - -#define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A) - -#define GPIO163_GPIO PIN_CFG(163, GPIO) - -#define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_GPS_START PIN_CFG(164, ALT_A) - -#define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A) -#define GPIO165_U3_RXD PIN_CFG(165, ALT_B) -#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C) - -#define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A) -#define GPIO166_U3_TXD PIN_CFG(166, ALT_B) -#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C) - -#define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A) -#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B) -#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C) - -#define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A) -#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B) -#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C) - -#define GPIO169_GPIO PIN_CFG(169, GPIO) -#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A) -#define GPIO169_DDR_RC PIN_CFG(169, ALT_B) -#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C) - -#define GPIO170_GPIO PIN_CFG(170, GPIO) -#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A) - -#define GPIO171_GPIO PIN_CFG(171, GPIO) -#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A) -#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B) -#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C) - -#define GPIO172_GPIO PIN_CFG(172, GPIO) -#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A) -#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B) -#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C) - -#define GPIO173_GPIO PIN_CFG(173, GPIO) -#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A) -#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B) -#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C) - -#define GPIO174_GPIO PIN_CFG(174, GPIO) -#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A) -#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B) -#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C) - -#define GPIO175_GPIO PIN_CFG(175, GPIO) -#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A) -#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B) -#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C) - -#define GPIO176_GPIO PIN_CFG(176, GPIO) -#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A) -#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B) - -#define GPIO177_GPIO PIN_CFG(177, GPIO) -#define GPIO177_U2_RXD PIN_CFG(177, ALT_A) -#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B) -#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C) - -#define GPIO178_GPIO PIN_CFG(178, GPIO) -#define GPIO178_U2_TXD PIN_CFG(178, ALT_A) -#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B) -#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C) - -#define GPIO179_GPIO PIN_CFG(179, GPIO) -#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A) -#define GPIO179_U3_RXD PIN_CFG(179, ALT_B) -#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C) - -#define GPIO180_GPIO PIN_CFG(180, GPIO) -#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A) -#define GPIO180_U3_TXD PIN_CFG(180, ALT_B) -#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C) - -#define GPIO185_GPIO PIN_CFG(185, GPIO) -#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A) -#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B) - -#define GPIO186_GPIO PIN_CFG(186, GPIO) -#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A) -#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B) - -#define GPIO187_GPIO PIN_CFG(187, GPIO) -#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A) -#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B) - -#define GPIO188_GPIO PIN_CFG(188, GPIO) -#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A) -#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B) - -#define GPIO189_GPIO PIN_CFG(189, GPIO) -#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A) -#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B) - -#define GPIO190_GPIO PIN_CFG(190, GPIO) -#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A) -#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B) - -#define GPIO191_GPIO PIN_CFG(191, GPIO) -#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A) -#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B) -#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C) - -#define GPIO192_GPIO PIN_CFG(192, GPIO) -#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A) -#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B) -#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C) - -#define GPIO193_GPIO PIN_CFG(193, GPIO) -#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A) -#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B) -#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C) - -#define GPIO194_GPIO PIN_CFG(194, GPIO) -#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A) -#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B) -#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C) - -#define GPIO195_GPIO PIN_CFG(195, GPIO) -#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A) -#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B) -#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C) - -#define GPIO196_GPIO PIN_CFG(196, GPIO) -#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A) -#define GPIO196_U0_RXD PIN_CFG(196, ALT_B) -#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C) - -#define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A) -#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B) - -#define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A) - -#define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A) -#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B) - -#define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_U1_TXD PIN_CFG(200, ALT_A) -#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B) - -#define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_U1_RXD PIN_CFG(201, ALT_A) -#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B) - -#define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A) -#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B) - -#define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A) -#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B) - -#define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A) -#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B) -#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C) - -#define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A) -#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B) -#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C) - -#define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A) -#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B) -#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C) - -#define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A) -#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B) -#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C) - -#define GPIO208_GPIO PIN_CFG(208, GPIO) -#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A) -#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B) -#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C) - -#define GPIO209_GPIO PIN_CFG(209, GPIO) -#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A) -#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B) -#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C) - -#define GPIO210_GPIO PIN_CFG(210, GPIO) -#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A) -#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B) - -#define GPIO211_GPIO PIN_CFG(211, GPIO) -#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A) -#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B) - -#define GPIO212_GPIO PIN_CFG(212, GPIO) -#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A) -#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B) - -#define GPIO213_GPIO PIN_CFG(213, GPIO) -#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A) -#define GPIO213_LCD_DE PIN_CFG(213, ALT_B) -#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C) - -#define GPIO214_GPIO PIN_CFG(214, GPIO) -#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A) -#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B) -#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C) - -#define GPIO215_GPIO PIN_CFG(215, GPIO) -#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A) -#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B) -#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C) - -#define GPIO216_GPIO PIN_CFG(216, GPIO) -#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A) -#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B) - -#define GPIO217_GPIO PIN_CFG(217, GPIO) -#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A) -#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B) -#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C) - -#define GPIO218_GPIO PIN_CFG(218, GPIO) -#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A) -#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B) - -#define GPIO219_GPIO PIN_CFG(219, GPIO) -#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A) -#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B) - -#define GPIO220_GPIO PIN_CFG(220, GPIO) -#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A) -#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B) - -#define GPIO221_GPIO PIN_CFG(221, GPIO) -#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A) -#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B) - -#define GPIO222_GPIO PIN_CFG(222, GPIO) -#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A) -#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B) - -#define GPIO223_GPIO PIN_CFG(223, GPIO) -#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A) -#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B) - -#define GPIO224_GPIO PIN_CFG(224, GPIO) -#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A) -#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B) - -#define GPIO225_GPIO PIN_CFG(225, GPIO) -#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A) -#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B) - -#define GPIO226_GPIO PIN_CFG(226, GPIO) -#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A) -#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B) - -#define GPIO227_GPIO PIN_CFG(227, GPIO) -#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A) -#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B) - -#endif diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index eff5842f6232..e8cd51aa61e4 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -48,9 +48,7 @@ static void write_pen_release(int val) static void __iomem *scu_base_addr(void) { - if (cpu_is_u5500()) - return __io_address(U5500_SCU_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) return __io_address(U8500_SCU_BASE); else ux500_unknown_soc(); @@ -120,9 +118,7 @@ static void __init wakeup_secondary(void) { void __iomem *backupram; - if (cpu_is_u5500()) - backupram = __io_address(U5500_BACKUPRAM0_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) backupram = __io_address(U8500_BACKUPRAM0_BASE); else ux500_unknown_soc(); diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h deleted file mode 100644 index cb2110c32858..000000000000 --- a/arch/arm/mach-ux500/ste-dma40-db5500.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - * - * DB5500-SoC-specific configuration for DMA40 - */ - -#ifndef STE_DMA40_DB5500_H -#define STE_DMA40_DB5500_H - -#define DB5500_DMA_NR_DEV 64 - -enum dma_src_dev_type { - DB5500_DMA_DEV0_SPI0_RX = 0, - DB5500_DMA_DEV1_SPI1_RX = 1, - DB5500_DMA_DEV2_SPI2_RX = 2, - DB5500_DMA_DEV3_SPI3_RX = 3, - DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4, - DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5, - DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6, - DB5500_DMA_DEV7_IRDA_RFS = 7, - DB5500_DMA_DEV8_IRDA_FIFO_RX = 8, - DB5500_DMA_DEV9_MSP0_RX = 9, - DB5500_DMA_DEV10_MSP1_RX = 10, - DB5500_DMA_DEV11_MSP2_RX = 11, - DB5500_DMA_DEV12_UART0_RX = 12, - DB5500_DMA_DEV13_UART1_RX = 13, - DB5500_DMA_DEV14_UART2_RX = 14, - DB5500_DMA_DEV15_UART3_RX = 15, - DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16, - DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17, - DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18, - DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19, - DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20, - DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21, - DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22, - DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23, - DB5500_DMA_DEV24_SDMMC0_RX = 24, - DB5500_DMA_DEV25_SDMMC1_RX = 25, - DB5500_DMA_DEV26_SDMMC2_RX = 26, - DB5500_DMA_DEV27_SDMMC3_RX = 27, - DB5500_DMA_DEV28_SDMMC4_RX = 28, - /* 29 - 32 not used */ - DB5500_DMA_DEV33_SDMMC0_RX = 33, - DB5500_DMA_DEV34_SDMMC1_RX = 34, - DB5500_DMA_DEV35_SDMMC2_RX = 35, - DB5500_DMA_DEV36_SDMMC3_RX = 36, - DB5500_DMA_DEV37_SDMMC4_RX = 37, - DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38, - DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39, - DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40, - DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41, - DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42, - DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43, - DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44, - DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45, - /* 46 not used */ - DB5500_DMA_DEV47_MCDE_RX = 47, - DB5500_DMA_DEV48_CRYPTO1_RX = 48, - /* 49, 50 not used */ - DB5500_DMA_DEV49_I2C1_RX = 51, - DB5500_DMA_DEV50_I2C3_RX = 52, - DB5500_DMA_DEV51_I2C2_RX = 53, - /* 54 - 60 not used */ - DB5500_DMA_DEV61_CRYPTO0_RX = 61, - /* 62, 63 not used */ -}; - -enum dma_dest_dev_type { - DB5500_DMA_DEV0_SPI0_TX = 0, - DB5500_DMA_DEV1_SPI1_TX = 1, - DB5500_DMA_DEV2_SPI2_TX = 2, - DB5500_DMA_DEV3_SPI3_TX = 3, - DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4, - DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5, - DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6, - DB5500_DMA_DEV7_IRRC_TX = 7, - DB5500_DMA_DEV8_IRDA_FIFO_TX = 8, - DB5500_DMA_DEV9_MSP0_TX = 9, - DB5500_DMA_DEV10_MSP1_TX = 10, - DB5500_DMA_DEV11_MSP2_TX = 11, - DB5500_DMA_DEV12_UART0_TX = 12, - DB5500_DMA_DEV13_UART1_TX = 13, - DB5500_DMA_DEV14_UART2_TX = 14, - DB5500_DMA_DEV15_UART3_TX = 15, - DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16, - DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17, - DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18, - DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19, - DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20, - DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21, - DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22, - DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23, - DB5500_DMA_DEV24_SDMMC0_TX = 24, - DB5500_DMA_DEV25_SDMMC1_TX = 25, - DB5500_DMA_DEV26_SDMMC2_TX = 26, - DB5500_DMA_DEV27_SDMMC3_TX = 27, - DB5500_DMA_DEV28_SDMMC4_TX = 28, - /* 29 - 31 not used */ - DB5500_DMA_DEV32_FSMC_TX = 32, - DB5500_DMA_DEV33_SDMMC0_TX = 33, - DB5500_DMA_DEV34_SDMMC1_TX = 34, - DB5500_DMA_DEV35_SDMMC2_TX = 35, - DB5500_DMA_DEV36_SDMMC3_TX = 36, - DB5500_DMA_DEV37_SDMMC4_TX = 37, - DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38, - DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39, - DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40, - DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41, - DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42, - DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43, - DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44, - DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45, - /* 46 not used */ - DB5500_DMA_DEV47_STM_TX = 47, - DB5500_DMA_DEV48_CRYPTO1_TX = 48, - DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49, - DB5500_DMA_DEV50_HASH1_TX = 50, - DB5500_DMA_DEV51_I2C1_TX = 51, - DB5500_DMA_DEV52_I2C3_TX = 52, - DB5500_DMA_DEV53_I2C2_TX = 53, - /* 54, 55 not used */ - DB5500_DMA_MEMCPY_TX_1 = 56, - DB5500_DMA_MEMCPY_TX_2 = 57, - DB5500_DMA_MEMCPY_TX_3 = 58, - DB5500_DMA_MEMCPY_TX_4 = 59, - DB5500_DMA_MEMCPY_TX_5 = 60, - DB5500_DMA_DEV61_CRYPTO0_TX = 61, - DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62, - DB5500_DMA_DEV63_HASH0_TX = 63, -}; - -#endif diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index d37df98b5c32..52e55337aa9b 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -18,8 +18,6 @@ #include <mach/irqs.h> #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer, - U5500_TWD_BASE, IRQ_LOCALTIMER); static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, U8500_TWD_BASE, IRQ_LOCALTIMER); @@ -28,8 +26,8 @@ static void __init ux500_twd_init(void) struct twd_local_timer *twd_local_timer; int err; - twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer : - &u8500_twd_local_timer; + /* Use this to switch local timer base if changed in new ASICs */ + twd_local_timer = &u8500_twd_local_timer; if (of_have_populated_dt()) twd_local_timer_of_register(); @@ -48,10 +46,7 @@ static void __init ux500_timer_init(void) void __iomem *mtu_timer_base; void __iomem *prcmu_timer_base; - if (cpu_is_u5500()) { - mtu_timer_base = __io_address(U5500_MTU0_BASE); - prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); - } else if (cpu_is_u8500()) { + if (cpu_is_u8500()) { mtu_timer_base = __io_address(U8500_MTU0_BASE); prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); } else { @@ -70,7 +65,7 @@ static void __init ux500_timer_init(void) * depending on delay which is not yet calibrated. RTC-RTT is in the * always-on powerdomain and is used as clockevent instead of twd when * sleeping. - * The PRCMU timer 4(3 for DB5500) register a clocksource and + * The PRCMU timer 4 register a clocksource and * sched_clock with higher rating then MTU since is always-on. * */ diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 6bbd74e950ab..cf4687ee2a7b 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -66,12 +66,6 @@ #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) -static struct fpga_irq_data sic_irq = { - .base = VA_SIC_BASE, - .irq_start = IRQ_SIC_START, - .chip.name = "SIC", -}; - #if 1 #define IRQ_MMCI0A IRQ_VICSOURCE22 #define IRQ_AACI IRQ_VICSOURCE24 @@ -105,8 +99,11 @@ void __init versatile_init_irq(void) writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); - fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq); - irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START); + np = of_find_matching_node_by_address(NULL, sic_of_match, + VERSATILE_SIC_BASE); + + fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START, + IRQ_VICSOURCE31, ~PIC_MASK, np); /* * Interrupts on secondary controller from 0 to 8 are routed to @@ -666,17 +663,18 @@ static struct amba_device *amba_devs[] __initdata = { * having a specific name. */ struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL), + OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data), OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL), + /* FIXME: this is buggy, the platform data is needed for this MMC instance too */ OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL), OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL), - OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL), + OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data), #if 0 /* diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index d2268be8c34c..15c6a00000ec 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -303,12 +303,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) } -struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys, - &sys->resources); -} - void __init pci_versatile_preinit(void) { pcibios_min_io = 0x44000000; @@ -339,19 +333,16 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) * 26 1 29 * 27 1 30 */ - irq = 27 + ((slot + pin - 1) & 3); - - printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq); + irq = 27 + ((slot - 24 + pin - 1) & 3); return irq; } static struct hw_pci versatile_pci __initdata = { - .swizzle = NULL, .map_irq = versatile_map_irq, .nr_controllers = 1, + .ops = &pci_versatile_ops, .setup = pci_versatile_setup, - .scan = pci_versatile_scan_bus, .preinit = pci_versatile_preinit, }; diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 47cdcca5a7e7..04dd092211b8 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -19,8 +19,10 @@ #include <linux/clkdev.h> #include <linux/mtd/physmap.h> +#include <asm/arch_timer.h> #include <asm/mach-types.h> #include <asm/sizes.h> +#include <asm/smp_twd.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -616,7 +618,6 @@ void __init v2m_dt_init_early(void) } clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups)); - versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); } static struct of_device_id vexpress_irq_match[] __initdata = { @@ -643,6 +644,11 @@ static void __init v2m_dt_timer_init(void) return; node = of_find_node_by_path(path); v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0)); + if (arch_timer_of_register() != 0) + twd_local_timer_of_register(); + + if (arch_timer_sched_clock_init() != 0) + versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); } static struct sys_timer v2m_dt_timer = { diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7c8a7d8467bf..101b9681c08c 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -4,23 +4,6 @@ comment "Processor Type" # which CPUs we support in the kernel image, and the compiler instruction # optimiser behaviour. -# ARM610 -config CPU_ARM610 - bool "Support ARM610 processor" if ARCH_RPC - select CPU_32v3 - select CPU_CACHE_V3 - select CPU_CACHE_VIVT - select CPU_CP15_MMU - select CPU_COPY_V3 if MMU - select CPU_TLB_V3 if MMU - select CPU_PABRT_LEGACY - help - The ARM610 is the successor to the ARM3 processor - and was produced by VLSI Technology Inc. - - Say Y if you want support for the ARM610 processor. - Otherwise, say N. - # ARM7TDMI config CPU_ARM7TDMI bool "Support ARM7TDMI processor" @@ -36,25 +19,6 @@ config CPU_ARM7TDMI Say Y if you want support for the ARM7TDMI processor. Otherwise, say N. -# ARM710 -config CPU_ARM710 - bool "Support ARM710 processor" if ARCH_RPC - select CPU_32v3 - select CPU_CACHE_V3 - select CPU_CACHE_VIVT - select CPU_CP15_MMU - select CPU_COPY_V3 if MMU - select CPU_TLB_V3 if MMU - select CPU_PABRT_LEGACY - help - A 32-bit RISC microprocessor based on the ARM7 processor core - designed by Advanced RISC Machines Ltd. The ARM710 is the - successor to the ARM610 processor. It was released in - July 1994 by VLSI Technology Inc. - - Say Y if you want support for the ARM710 processor. - Otherwise, say N. - # ARM720T config CPU_ARM720T bool "Support ARM720T processor" if ARCH_INTEGRATOR @@ -530,9 +494,6 @@ config CPU_CACHE_FA if MMU # The copy-page model -config CPU_COPY_V3 - bool - config CPU_COPY_V4WT bool @@ -549,11 +510,6 @@ config CPU_COPY_V6 bool # This selects the TLB model -config CPU_TLB_V3 - bool - help - ARM Architecture Version 3 TLB. - config CPU_TLB_V4WT bool help @@ -731,7 +687,7 @@ config CPU_HIGH_VECTOR config CPU_ICACHE_DISABLE bool "Disable I-Cache (I-bit)" - depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) + depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N. diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index bca7e61928c7..8a9c4cb50a93 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -44,7 +44,6 @@ obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o AFLAGS_cache-v6.o :=-Wa,-march=armv6 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a -obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o @@ -54,7 +53,6 @@ obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o -obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o @@ -66,8 +64,6 @@ obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o AFLAGS_tlb-v6.o :=-Wa,-march=armv6 AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a -obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o -obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S index c2301f226100..52e35f32eefb 100644 --- a/arch/arm/mm/cache-v3.S +++ b/arch/arm/mm/cache-v3.S @@ -78,6 +78,7 @@ ENTRY(v3_coherent_kern_range) * - end - virtual end address */ ENTRY(v3_coherent_user_range) + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index fd9bb7addc8d..022135d2b7e4 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -88,6 +88,7 @@ ENTRY(v4_coherent_kern_range) * - end - virtual end address */ ENTRY(v4_coherent_user_range) + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 4f2c14151ccb..8f1eeae340c8 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -167,9 +167,9 @@ ENTRY(v4wb_coherent_user_range) add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b - mov ip, #0 - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache - mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index 4d7b467631ce..b34a5f908a82 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -125,6 +125,7 @@ ENTRY(v4wt_coherent_user_range) add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 74c2e5a33a4d..4b10760c56d6 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -12,6 +12,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/errno.h> #include <asm/unwind.h> #include "proc-macros.S" @@ -135,7 +136,6 @@ ENTRY(v6_coherent_user_range) 1: USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line add r0, r0, #CACHE_LINE_SIZE -2: cmp r0, r1 blo 1b #endif @@ -154,13 +154,11 @@ ENTRY(v6_coherent_user_range) /* * Fault handling for the cache operation above. If the virtual address in r0 - * isn't mapped, just try the next page. + * isn't mapped, fail with -EFAULT. */ 9001: - mov r0, r0, lsr #12 - mov r0, r0, lsl #12 - add r0, r0, #4096 - b 2b + mov r0, #-EFAULT + mov pc, lr UNWIND(.fnend ) ENDPROC(v6_coherent_user_range) ENDPROC(v6_coherent_kern_range) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index a655d3da386d..39e3fb3db801 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -13,6 +13,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/errno.h> #include <asm/unwind.h> #include "proc-macros.S" @@ -198,7 +199,6 @@ ENTRY(v7_coherent_user_range) add r12, r12, r2 cmp r12, r1 blo 2b -3: mov r0, #0 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB @@ -208,13 +208,11 @@ ENTRY(v7_coherent_user_range) /* * Fault handling for the cache operation above. If the virtual address in r0 - * isn't mapped, just try the next page. + * isn't mapped, fail with -EFAULT. */ 9001: - mov r12, r12, lsr #12 - mov r12, r12, lsl #12 - add r12, r12, #4096 - b 3b + mov r0, #-EFAULT + mov pc, lr UNWIND(.fnend ) ENDPROC(v7_coherent_kern_range) ENDPROC(v7_coherent_user_range) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index ee9bb363d606..806cc4f63516 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -18,30 +18,39 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock); unsigned int cpu_last_asid = ASID_FIRST_VERSION; -#ifdef CONFIG_SMP -DEFINE_PER_CPU(struct mm_struct *, current_mm); -#endif #ifdef CONFIG_ARM_LPAE -#define cpu_set_asid(asid) { \ - unsigned long ttbl, ttbh; \ - asm volatile( \ - " mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ - " mov %1, %2, lsl #(48 - 32) @ set ASID\n" \ - " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ - : "=&r" (ttbl), "=&r" (ttbh) \ - : "r" (asid & ~ASID_MASK)); \ +void cpu_set_reserved_ttbr0(void) +{ + unsigned long ttbl = __pa(swapper_pg_dir); + unsigned long ttbh = 0; + + /* + * Set TTBR0 to swapper_pg_dir which contains only global entries. The + * ASID is set to 0. + */ + asm volatile( + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" + : + : "r" (ttbl), "r" (ttbh)); + isb(); } #else -#define cpu_set_asid(asid) \ - asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +void cpu_set_reserved_ttbr0(void) +{ + u32 ttb; + /* Copy TTBR1 into TTBR0 */ + asm volatile( + " mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n" + " mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n" + : "=r" (ttb)); + isb(); +} #endif /* * We fork()ed a process, and we need a new context for the child - * to run in. We reserve version 0 for initial tasks so we will - * always allocate an ASID. The ASID 0 is reserved for the TTBR - * register changing sequence. + * to run in. */ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) { @@ -51,9 +60,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { - /* set the reserved ASID before flushing the TLB */ - cpu_set_asid(0); - isb(); + cpu_set_reserved_ttbr0(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { __flush_icache_all(); @@ -98,14 +105,7 @@ static void reset_context(void *info) { unsigned int asid; unsigned int cpu = smp_processor_id(); - struct mm_struct *mm = per_cpu(current_mm, cpu); - - /* - * Check if a current_mm was set on this CPU as it might still - * be in the early booting stages and using the reserved ASID. - */ - if (!mm) - return; + struct mm_struct *mm = current->active_mm; smp_rmb(); asid = cpu_last_asid + cpu + 1; @@ -114,8 +114,7 @@ static void reset_context(void *info) set_mm_context(mm, asid); /* set the new ASID */ - cpu_set_asid(mm->context.id); - isb(); + cpu_switch_mm(mm->pgd, mm); } #else diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c deleted file mode 100644 index 3935bddd4769..000000000000 --- a/arch/arm/mm/copypage-v3.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * linux/arch/arm/mm/copypage-v3.c - * - * Copyright (C) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/init.h> -#include <linux/highmem.h> - -/* - * ARMv3 optimised copy_user_highpage - * - * FIXME: do we need to handle cache stuff... - */ -static void __naked -v3_copy_user_page(void *kto, const void *kfrom) -{ - asm("\n\ - stmfd sp!, {r4, lr} @ 2\n\ - mov r2, %2 @ 1\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ -1: stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ - stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ - stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmia %0!, {r3, r4, ip, lr} @ 4\n\ - subs r2, r2, #1 @ 1\n\ - stmia %1!, {r3, r4, ip, lr} @ 4\n\ - ldmneia %0!, {r3, r4, ip, lr} @ 4\n\ - bne 1b @ 1\n\ - ldmfd sp!, {r4, pc} @ 3" - : - : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64)); -} - -void v3_copy_user_highpage(struct page *to, struct page *from, - unsigned long vaddr, struct vm_area_struct *vma) -{ - void *kto, *kfrom; - - kto = kmap_atomic(to); - kfrom = kmap_atomic(from); - v3_copy_user_page(kto, kfrom); - kunmap_atomic(kfrom); - kunmap_atomic(kto); -} - -/* - * ARMv3 optimised clear_user_page - * - * FIXME: do we need to handle cache stuff... - */ -void v3_clear_user_highpage(struct page *page, unsigned long vaddr) -{ - void *ptr, *kaddr = kmap_atomic(page); - asm volatile("\n\ - mov r1, %2 @ 1\n\ - mov r2, #0 @ 1\n\ - mov r3, #0 @ 1\n\ - mov ip, #0 @ 1\n\ - mov lr, #0 @ 1\n\ -1: stmia %0!, {r2, r3, ip, lr} @ 4\n\ - stmia %0!, {r2, r3, ip, lr} @ 4\n\ - stmia %0!, {r2, r3, ip, lr} @ 4\n\ - stmia %0!, {r2, r3, ip, lr} @ 4\n\ - subs r1, r1, #1 @ 1\n\ - bne 1b @ 1" - : "=r" (ptr) - : "0" (kaddr), "I" (PAGE_SIZE / 64) - : "r1", "r2", "r3", "ip", "lr"); - kunmap_atomic(kaddr); -} - -struct cpu_user_fns v3_user_fns __initdata = { - .cpu_clear_user_highpage = v3_clear_user_highpage, - .cpu_copy_user_highpage = v3_copy_user_highpage, -}; diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index f07467533365..c3bd83450227 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -247,7 +247,9 @@ good_area: return handle_mm_fault(mm, vma, addr & PAGE_MASK, flags); check_stack: - if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) + /* Don't allow expansion below FIRST_USER_ADDRESS */ + if (vma->vm_flags & VM_GROWSDOWN && + addr >= FIRST_USER_ADDRESS && !expand_stack(vma, addr)) goto good_area; out: return fault; @@ -430,9 +432,6 @@ do_translation_fault(unsigned long addr, unsigned int fsr, index = pgd_index(addr); - /* - * FIXME: CP15 C1 is write only on ARMv3 architectures. - */ pgd = cpu_get_pgd() + index; pgd_k = init_mm.pgd + index; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 2c7cf2f9c837..aa78de8bfdd3 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -489,7 +489,8 @@ static void __init build_mem_type_table(void) */ for (i = 0; i < ARRAY_SIZE(mem_types); i++) { mem_types[i].prot_pte |= PTE_EXT_AF; - mem_types[i].prot_sect |= PMD_SECT_AF; + if (mem_types[i].prot_sect) + mem_types[i].prot_sect |= PMD_SECT_AF; } kern_pgprot |= PTE_EXT_AF; vecs_pgprot |= PTE_EXT_AF; diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 234951345eb3..0650bb87c1e3 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -241,6 +241,7 @@ ENTRY(arm1020_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index c244b06caac9..4188478325a6 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -235,6 +235,7 @@ ENTRY(arm1020e_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 38fe22efd18f..33c68824bff0 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -224,6 +224,7 @@ ENTRY(arm1022_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 3eb9c3c26c75..fbc1d5fc24dc 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -218,6 +218,7 @@ ENTRY(arm1026_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S deleted file mode 100644 index 4fbeb5b8e6c2..000000000000 --- a/arch/arm/mm/proc-arm6_7.S +++ /dev/null @@ -1,327 +0,0 @@ -/* - * linux/arch/arm/mm/proc-arm6,7.S - * - * Copyright (C) 1997-2000 Russell King - * hacked for non-paged-MM by Hyok S. Choi, 2003. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * These are the low level assembler for performing cache and TLB - * functions on the ARM610 & ARM710. - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/assembler.h> -#include <asm/asm-offsets.h> -#include <asm/hwcap.h> -#include <asm/pgtable-hwdef.h> -#include <asm/pgtable.h> -#include <asm/ptrace.h> - -#include "proc-macros.S" - -ENTRY(cpu_arm6_dcache_clean_area) -ENTRY(cpu_arm7_dcache_clean_area) - mov pc, lr - -/* - * Function: arm6_7_data_abort () - * - * Params : r2 = pt_regs - * : r4 = aborted context pc - * : r5 = aborted context psr - * - * Purpose : obtain information about current aborted instruction - * - * Returns : r4-r5, r10-r11, r13 preserved - */ - -ENTRY(cpu_arm7_data_abort) - mrc p15, 0, r1, c5, c0, 0 @ get FSR - mrc p15, 0, r0, c6, c0, 0 @ get FAR - ldr r8, [r4] @ read arm instruction - tst r8, #1 << 20 @ L = 0 -> write? - orreq r1, r1, #1 << 11 @ yes. - and r7, r8, #15 << 24 - add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine - nop - -/* 0 */ b .data_unknown -/* 1 */ b do_DataAbort @ swp -/* 2 */ b .data_unknown -/* 3 */ b .data_unknown -/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m -/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m] -/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm -/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm] -/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist> -/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> -/* a */ b .data_unknown -/* b */ b .data_unknown -/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m -/* d */ b do_DataAbort @ ldc rd, [rn, #m] -/* e */ b .data_unknown -/* f */ -.data_unknown: @ Part of jumptable - mov r0, r4 - mov r1, r8 - b baddataabort - -ENTRY(cpu_arm6_data_abort) - mrc p15, 0, r1, c5, c0, 0 @ get FSR - mrc p15, 0, r0, c6, c0, 0 @ get FAR - ldr r8, [r4] @ read arm instruction - tst r8, #1 << 20 @ L = 0 -> write? - orreq r1, r1, #1 << 11 @ yes. - and r7, r8, #14 << 24 - teq r7, #8 << 24 @ was it ldm/stm - bne do_DataAbort - -.data_arm_ldmstm: - tst r8, #1 << 21 @ check writeback bit - beq do_DataAbort @ no writeback -> no fixup - mov r7, #0x11 - orr r7, r7, #0x1100 - and r6, r8, r7 - and r9, r8, r7, lsl #1 - add r6, r6, r9, lsr #1 - and r9, r8, r7, lsl #2 - add r6, r6, r9, lsr #2 - and r9, r8, r7, lsl #3 - add r6, r6, r9, lsr #3 - add r6, r6, r6, lsr #8 - add r6, r6, r6, lsr #4 - and r6, r6, #15 @ r6 = no. of registers to transfer. - and r9, r8, #15 << 16 @ Extract 'n' from instruction - ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' - tst r8, #1 << 23 @ Check U bit - subne r7, r7, r6, lsl #2 @ Undo increment - addeq r7, r7, r6, lsl #2 @ Undo decrement - str r7, [r2, r9, lsr #14] @ Put register 'Rn' - b do_DataAbort - -.data_arm_apply_r6_and_rn: - and r9, r8, #15 << 16 @ Extract 'n' from instruction - ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' - tst r8, #1 << 23 @ Check U bit - subne r7, r7, r6 @ Undo incrmenet - addeq r7, r7, r6 @ Undo decrement - str r7, [r2, r9, lsr #14] @ Put register 'Rn' - b do_DataAbort - -.data_arm_lateldrpreconst: - tst r8, #1 << 21 @ check writeback bit - beq do_DataAbort @ no writeback -> no fixup -.data_arm_lateldrpostconst: - movs r6, r8, lsl #20 @ Get offset - beq do_DataAbort @ zero -> no fixup - and r9, r8, #15 << 16 @ Extract 'n' from instruction - ldr r7, [r2, r9, lsr #14] @ Get register 'Rn' - tst r8, #1 << 23 @ Check U bit - subne r7, r7, r6, lsr #20 @ Undo increment - addeq r7, r7, r6, lsr #20 @ Undo decrement - str r7, [r2, r9, lsr #14] @ Put register 'Rn' - b do_DataAbort - -.data_arm_lateldrprereg: - tst r8, #1 << 21 @ check writeback bit - beq do_DataAbort @ no writeback -> no fixup -.data_arm_lateldrpostreg: - and r7, r8, #15 @ Extract 'm' from instruction - ldr r6, [r2, r7, lsl #2] @ Get register 'Rm' - mov r9, r8, lsr #7 @ get shift count - ands r9, r9, #31 - and r7, r8, #0x70 @ get shift type - orreq r7, r7, #8 @ shift count = 0 - add pc, pc, r7 - nop - - mov r6, r6, lsl r9 @ 0: LSL #!0 - b .data_arm_apply_r6_and_rn - b .data_arm_apply_r6_and_rn @ 1: LSL #0 - nop - b .data_unknown @ 2: MUL? - nop - b .data_unknown @ 3: MUL? - nop - mov r6, r6, lsr r9 @ 4: LSR #!0 - b .data_arm_apply_r6_and_rn - mov r6, r6, lsr #32 @ 5: LSR #32 - b .data_arm_apply_r6_and_rn - b .data_unknown @ 6: MUL? - nop - b .data_unknown @ 7: MUL? - nop - mov r6, r6, asr r9 @ 8: ASR #!0 - b .data_arm_apply_r6_and_rn - mov r6, r6, asr #32 @ 9: ASR #32 - b .data_arm_apply_r6_and_rn - b .data_unknown @ A: MUL? - nop - b .data_unknown @ B: MUL? - nop - mov r6, r6, ror r9 @ C: ROR #!0 - b .data_arm_apply_r6_and_rn - mov r6, r6, rrx @ D: RRX - b .data_arm_apply_r6_and_rn - b .data_unknown @ E: MUL? - nop - b .data_unknown @ F: MUL? - -/* - * Function: arm6_7_proc_init (void) - * : arm6_7_proc_fin (void) - * - * Notes : This processor does not require these - */ -ENTRY(cpu_arm6_proc_init) -ENTRY(cpu_arm7_proc_init) - mov pc, lr - -ENTRY(cpu_arm6_proc_fin) -ENTRY(cpu_arm7_proc_fin) - mov r0, #0x31 @ ....S..DP...M - mcr p15, 0, r0, c1, c0, 0 @ disable caches - mov pc, lr - -ENTRY(cpu_arm6_do_idle) -ENTRY(cpu_arm7_do_idle) - mov pc, lr - -/* - * Function: arm6_7_switch_mm(unsigned long pgd_phys) - * Params : pgd_phys Physical address of page table - * Purpose : Perform a task switch, saving the old processes state, and restoring - * the new. - */ -ENTRY(cpu_arm6_switch_mm) -ENTRY(cpu_arm7_switch_mm) -#ifdef CONFIG_MMU - mov r1, #0 - mcr p15, 0, r1, c7, c0, 0 @ flush cache - mcr p15, 0, r0, c2, c0, 0 @ update page table ptr - mcr p15, 0, r1, c5, c0, 0 @ flush TLBs -#endif - mov pc, lr - -/* - * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) - * Params : r0 = Address to set - * : r1 = value to set - * Purpose : Set a PTE and flush it out of any WB cache - */ - .align 5 -ENTRY(cpu_arm6_set_pte_ext) -ENTRY(cpu_arm7_set_pte_ext) -#ifdef CONFIG_MMU - armv3_set_pte_ext wc_disable=0 -#endif /* CONFIG_MMU */ - mov pc, lr - -/* - * Function: _arm6_7_reset - * Params : r0 = address to jump to - * Notes : This sets up everything for a reset - */ - .pushsection .idmap.text, "ax" -ENTRY(cpu_arm6_reset) -ENTRY(cpu_arm7_reset) - mov r1, #0 - mcr p15, 0, r1, c7, c0, 0 @ flush cache -#ifdef CONFIG_MMU - mcr p15, 0, r1, c5, c0, 0 @ flush TLB -#endif - mov r1, #0x30 - mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc - mov pc, r0 -ENDPROC(cpu_arm6_reset) -ENDPROC(cpu_arm7_reset) - .popsection - - __CPUINIT - - .type __arm6_setup, #function -__arm6_setup: mov r0, #0 - mcr p15, 0, r0, c7, c0 @ flush caches on v3 -#ifdef CONFIG_MMU - mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 - mov r0, #0x3d @ . ..RS BLDP WCAM - orr r0, r0, #0x100 @ . ..01 0011 1101 -#else - mov r0, #0x3c @ . ..RS BLDP WCA. -#endif - mov pc, lr - .size __arm6_setup, . - __arm6_setup - - .type __arm7_setup, #function -__arm7_setup: mov r0, #0 - mcr p15, 0, r0, c7, c0 @ flush caches on v3 -#ifdef CONFIG_MMU - mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 - mcr p15, 0, r0, c3, c0 @ load domain access register - mov r0, #0x7d @ . ..RS BLDP WCAM - orr r0, r0, #0x100 @ . ..01 0111 1101 -#else - mov r0, #0x7c @ . ..RS BLDP WCA. -#endif - mov pc, lr - .size __arm7_setup, . - __arm7_setup - - __INITDATA - - @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) - define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort - define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort - - .section ".rodata" - - string cpu_arch_name, "armv3" - string cpu_elf_name, "v3" - string cpu_arm6_name, "ARM6" - string cpu_arm610_name, "ARM610" - string cpu_arm7_name, "ARM7" - string cpu_arm710_name, "ARM710" - - .align - - .section ".proc.info.init", #alloc, #execinstr - -.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \ - cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req - .type __\name\()_proc_info, #object -__\name\()_proc_info: - .long \cpu_val - .long \cpu_mask - .long \cpu_mm_mmu_flags - .long PMD_TYPE_SECT | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ - b \cpu_flush - .long cpu_arch_name - .long cpu_elf_name - .long HWCAP_SWP | HWCAP_26BIT - .long \cpu_name - .long \cpu_proc_funcs - .long v3_tlb_fns - .long v3_user_fns - .long v3_cache_fns - .size __\name\()_proc_info, . - __\name\()_proc_info -.endm - - arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \ - 0x00000c1e, __arm6_setup, arm6_processor_functions - arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \ - 0x00000c1e, __arm6_setup, arm6_processor_functions - arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \ - 0x00000c1e, __arm7_setup, arm7_processor_functions - arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \ - PMD_TYPE_SECT | \ - PMD_SECT_BUFFERABLE | \ - PMD_SECT_CACHEABLE | \ - PMD_BIT4 | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ, \ - __arm7_setup, arm7_processor_functions diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index cb941ae95f66..1a8c138eb897 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -210,6 +210,7 @@ ENTRY(arm920_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 4ec0e074dd55..4c44d7e1c3ca 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -212,6 +212,7 @@ ENTRY(arm922_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 9dccd9a365b3..ec5b1180994f 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -258,6 +258,7 @@ ENTRY(arm925_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 820259b81a1f..c31e62c606c0 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -221,6 +221,7 @@ ENTRY(arm926_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 9fdc0a170974..a613a7dd7146 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -160,7 +160,7 @@ ENTRY(arm940_coherent_user_range) * - size - region size */ ENTRY(arm940_flush_kern_dcache_area) - mov ip, #0 + mov r0, #0 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index @@ -168,8 +168,8 @@ ENTRY(arm940_flush_kern_dcache_area) bcs 2b @ entries 63 to 0 subs r1, r1, #1 << 4 bcs 1b @ segments 7 to 0 - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache - mcr p15, 0, ip, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr /* diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index f684cfedcca9..9f4f2999fdd0 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -190,6 +190,7 @@ ENTRY(arm946_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index ba3c500584ac..23a8e4c7f2bd 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -232,6 +232,7 @@ ENTRY(feroceon_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index cdfedc5b8ad8..b0475468c711 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -193,6 +193,7 @@ ENTRY(mohawk_coherent_user_range) cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov r0, #0 mov pc, lr /* diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 3a4b3e7b888c..42ac069c8012 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -49,15 +49,10 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_ARM_ERRATA_754322 dsb #endif - mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID - isb -1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 - isb -#ifdef CONFIG_ARM_ERRATA_754322 - dsb -#endif mcr p15, 0, r1, c13, c0, 1 @ set context ID isb + mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + isb #endif mov pc, lr ENDPROC(cpu_v7_switch_mm) diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S deleted file mode 100644 index d253995ec4ca..000000000000 --- a/arch/arm/mm/tlb-v3.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/arm/mm/tlbv3.S - * - * Copyright (C) 1997-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * ARM architecture version 3 TLB handling functions. - * - * Processors: ARM610, ARM710. - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> -#include <asm/tlbflush.h> -#include "proc-macros.S" - - .align 5 -/* - * v3_flush_user_tlb_range(start, end, mm) - * - * Invalidate a range of TLB entries in the specified address space. - * - * - start - range start address - * - end - range end address - * - mm - mm_struct describing address space - */ - .align 5 -ENTRY(v3_flush_user_tlb_range) - vma_vm_mm r2, r2 - act_mm r3 @ get current->active_mm - teq r2, r3 @ == mm ? - movne pc, lr @ no, we dont do anything -ENTRY(v3_flush_kern_tlb_range) - bic r0, r0, #0x0ff - bic r0, r0, #0xf00 -1: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry - add r0, r0, #PAGE_SZ - cmp r0, r1 - blo 1b - mov pc, lr - - __INITDATA - - /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ - define_tlb_functions v3, v3_tlb_flags diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 0da42058a20f..8daae9b230ea 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -160,7 +160,7 @@ iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -static struct pci_ops iop3xx_ops = { +struct pci_ops iop3xx_ops = { .read = iop3xx_read_config, .write = iop3xx_write_config, }; @@ -220,12 +220,6 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) return 1; } -struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys, - &sys->resources); -} - void __init iop3xx_atu_setup(void) { /* BAR 0 ( Disabled ) */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index c7f5169a6a54..36c8989d9de6 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -256,13 +256,13 @@ #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) @@ -270,7 +270,7 @@ #define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) @@ -283,13 +283,13 @@ #define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) @@ -316,7 +316,7 @@ #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) @@ -672,23 +672,23 @@ #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) @@ -698,7 +698,7 @@ #define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) @@ -746,16 +746,16 @@ #define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) #define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) @@ -766,19 +766,19 @@ #define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) #define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) @@ -786,27 +786,27 @@ #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 527f8fe3e31b..9761e003bde2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -573,7 +573,7 @@ #define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) #define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C) +#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL) #define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) @@ -1187,7 +1187,7 @@ #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) #define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index c0fe2757b695..ed8605f01155 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -9,9 +9,6 @@ obj-m := obj-n := obj- := -# OCPI interconnect support for 1710, 1610 and 5912 -obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o - # omap_device support (OMAP2+ only at the moment) obj-$(CONFIG_ARCH_OMAP2) += omap_device.o obj-$(CONFIG_ARCH_OMAP3) += omap_device.o diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index f1e46ea6b81d..0a9b9a970113 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -20,6 +20,7 @@ #include <plat/board.h> #include <plat/vram.h> #include <plat/dsp.h> +#include <plat/dma.h> #include <plat/omap-secure.h> diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 5068fe5a6910..44ae077dbc28 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -19,6 +19,7 @@ #include <linux/io.h> #include <linux/clocksource.h> +#include <asm/mach/time.h> #include <asm/sched_clock.h> #include <plat/hardware.h> @@ -43,7 +44,7 @@ static u32 notrace omap_32k_read_sched_clock(void) } /** - * read_persistent_clock - Return time from a persistent clock. + * omap_read_persistent_clock - Return time from a persistent clock. * * Reads the time from a source which isn't disabled during PM, the * 32k sync timer. Convert the cycles elapsed since last read into @@ -52,7 +53,7 @@ static u32 notrace omap_32k_read_sched_clock(void) static struct timespec persistent_ts; static cycles_t cycles, last_cycles; static unsigned int persistent_mult, persistent_shift; -void read_persistent_clock(struct timespec *ts) +static void omap_read_persistent_clock(struct timespec *ts) { unsigned long long nsecs; cycles_t delta; @@ -116,6 +117,7 @@ int __init omap_init_clocksource_32k(void) printk(err, "32k_counter"); setup_sched_clock(omap_32k_read_sched_clock, 32, 32768); + register_persistent_clock(NULL, omap_read_persistent_clock); } return 0; } diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index c58d896cd5c3..987e6101267d 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -41,6 +41,15 @@ #include <plat/tc.h> +/* + * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA + * channels that an instance of the SDMA IP block can support. Used + * to size arrays. (The actual maximum on a particular SoC may be less + * than this -- for example, OMAP1 SDMA instances only support 17 logical + * DMA channels.) + */ +#define MAX_LOGICAL_DMA_CH_COUNT 32 + #undef DEBUG #ifndef CONFIG_ARCH_OMAP1 @@ -883,7 +892,7 @@ void omap_start_dma(int lch) if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; - char dma_chan_link_map[dma_lch_count]; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ @@ -981,7 +990,7 @@ void omap_stop_dma(int lch) if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; - char dma_chan_link_map[dma_lch_count]; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); do { diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 652139c0339e..c4ed35e89fbd 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -349,11 +349,12 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start); int omap_dm_timer_stop(struct omap_dm_timer *timer) { unsigned long rate = 0; - struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; + struct dmtimer_platform_data *pdata; if (unlikely(!timer)) return -EINVAL; + pdata = timer->pdev->dev.platform_data; if (!pdata->needs_manual_reset) rate = clk_get_rate(timer->fclk); diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index d5eb4c87db9d..4814c5b65306 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h @@ -91,6 +91,8 @@ struct omap_usb_config { u32 (*usb0_init)(unsigned nwires, unsigned is_device); u32 (*usb1_init)(unsigned nwires); u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); + + int (*ocpi_enable)(void); }; struct omap_lcd_config { diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index b4d7ec3fbfbe..a557b8484e6c 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -32,6 +32,8 @@ extern int __init omap_init_clocksource_32k(void); +extern void __init omap_check_revision(void); + extern void omap_reserve(void); extern int omap_dss_reset(struct omap_hwmod *); diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index dc562a5c0a8a..42afb4c45517 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -442,6 +442,7 @@ struct omap_system_dma_plat_info { u32 (*dma_read)(int reg, int lch); }; +extern void __init omap_init_consistent_dma_size(void); extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 9418f00b6c38..230ff91be491 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -316,12 +316,12 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) OMAP_TIMER_V1_SYS_STAT_OFFSET; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; - timer->irq_dis = 0; + timer->irq_dis = NULL; timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; timer->func_base = timer->io_base; } else { timer->revision = 2; - timer->sys_stat = 0; + timer->sys_stat = NULL; timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 3f26db4ee8e6..14dde32cd406 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -213,11 +213,16 @@ struct omap_hwmod_addr_space { */ #define OCP_USER_MPU (1 << 0) #define OCP_USER_SDMA (1 << 1) +#define OCP_USER_DSP (1 << 2) /* omap_hwmod_ocp_if.flags bits */ #define OCPIF_SWSUP_IDLE (1 << 0) #define OCPIF_CAN_BURST (1 << 1) +/* omap_hwmod_ocp_if._int_flags possibilities */ +#define _OCPIF_INT_FLAGS_REGISTERED (1 << 0) + + /** * struct omap_hwmod_ocp_if - OCP interface data * @master: struct omap_hwmod that initiates OCP transactions on this link @@ -229,6 +234,7 @@ struct omap_hwmod_addr_space { * @width: OCP data width * @user: initiators using this interface (see OCP_USER_* macros above) * @flags: OCP interface flags (see OCPIF_* macros above) + * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above) * * It may also be useful to add a tag_cnt field for OCP2.x devices. * @@ -247,6 +253,7 @@ struct omap_hwmod_ocp_if { u8 width; u8 user; u8 flags; + u8 _int_flags; }; @@ -327,9 +334,9 @@ struct omap_hwmod_sysc_fields { * then this field has to be populated with the correct offset structure. */ struct omap_hwmod_class_sysconfig { - u16 rev_offs; - u16 sysc_offs; - u16 syss_offs; + u32 rev_offs; + u32 sysc_offs; + u32 syss_offs; u16 sysc_flags; struct omap_hwmod_sysc_fields *sysc_fields; u8 srst_udelay; @@ -476,6 +483,16 @@ struct omap_hwmod_class { }; /** + * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs + * @ocp_if: OCP interface structure record pointer + * @node: list_head pointing to next struct omap_hwmod_link in a list + */ +struct omap_hwmod_link { + struct omap_hwmod_ocp_if *ocp_if; + struct list_head node; +}; + +/** * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) * @name: name of the hwmod * @class: struct omap_hwmod_class * to the class of this hwmod @@ -487,12 +504,10 @@ struct omap_hwmod_class { * @_clk: pointer to the main struct clk (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @voltdm: pointer to voltage domain (filled in at runtime) - * @masters: ptr to array of OCP ifs that this hwmod can initiate on - * @slaves: ptr to array of OCP ifs that this hwmod can respond on * @dev_attr: arbitrary device attributes that can be passed to the driver * @_sysc_cache: internal-use hwmod flags * @_mpu_rt_va: cached register target start address (internal use) - * @_mpu_port_index: cached MPU register target slave ID (internal use) + * @_mpu_port: cached MPU register target slave (internal use) * @opt_clks_cnt: number of @opt_clks * @master_cnt: number of @master entries * @slaves_cnt: number of @slave entries @@ -511,6 +526,8 @@ struct omap_hwmod_class { * * Parameter names beginning with an underscore are managed internally by * the omap_hwmod code and should not be set during initialization. + * + * @masters and @slaves are now deprecated. */ struct omap_hwmod { const char *name; @@ -529,15 +546,15 @@ struct omap_hwmod { struct omap_hwmod_opt_clk *opt_clks; char *clkdm_name; struct clockdomain *clkdm; - struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ - struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ + struct list_head master_ports; /* connect to *_IA */ + struct list_head slave_ports; /* connect to *_TA */ void *dev_attr; u32 _sysc_cache; void __iomem *_mpu_rt_va; spinlock_t _lock; struct list_head node; + struct omap_hwmod_ocp_if *_mpu_port; u16 flags; - u8 _mpu_port_index; u8 response_lat; u8 rst_lines_cnt; u8 opt_clks_cnt; @@ -549,7 +566,6 @@ struct omap_hwmod { u8 _postsetup_state; }; -int omap_hwmod_register(struct omap_hwmod **ohs); struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); @@ -581,6 +597,8 @@ int omap_hwmod_softreset(struct omap_hwmod *oh); int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); +int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, + const char *name, struct resource *res); struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); @@ -619,4 +637,6 @@ extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); +extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); + #endif diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index d50cbc6385bd..c490240bb82c 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -475,13 +475,11 @@ static int omap_device_count_resources(struct omap_device *od) static int omap_device_fill_resources(struct omap_device *od, struct resource *res) { - int c = 0; int i, r; for (i = 0; i < od->hwmods_cnt; i++) { r = omap_hwmod_fill_resources(od->hwmods[i], res); res += r; - c += r; } return 0; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index f9a8c5341ee9..477363c163ec 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -196,8 +196,8 @@ static void __init omap_map_sram(void) * Looks like we need to preserve some bootloader code at the * beginning of SRAM for jumping to flash for reboot to work... */ - memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0, - omap_sram_size - SRAM_BOOTLOADER_SZ); + memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0, + omap_sram_size - SRAM_BOOTLOADER_SZ); } /* diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index d2bbfd1cb0b5..daa0327381b5 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -31,15 +31,12 @@ #include <mach/hardware.h> -#include "../mach-omap2/common.h" - #ifdef CONFIG_ARCH_OMAP_OTG void __init omap_otg_init(struct omap_usb_config *config) { u32 syscon; - int status; int alt_pingroup = 0; /* NOTE: no bus or clock setup (yet?) */ @@ -104,6 +101,7 @@ omap_otg_init(struct omap_usb_config *config) #ifdef CONFIG_USB_GADGET_OMAP if (config->otg || config->register_dev) { struct platform_device *udc_device = config->udc_device; + int status; syscon &= ~DEV_IDLE_EN; udc_device->dev.platform_data = config; @@ -116,6 +114,7 @@ omap_otg_init(struct omap_usb_config *config) #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) if (config->otg || config->register_host) { struct platform_device *ohci_device = config->ohci_device; + int status; syscon &= ~HST_IDLE_EN; ohci_device->dev.platform_data = config; @@ -128,6 +127,7 @@ omap_otg_init(struct omap_usb_config *config) #ifdef CONFIG_USB_OTG if (config->otg) { struct platform_device *otg_device = config->otg_device; + int status; syscon &= ~OTG_IDLE_EN; otg_device->dev.platform_data = config; @@ -138,8 +138,6 @@ omap_otg_init(struct omap_usb_config *config) #endif pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); omap_writel(syscon, OTG_SYSCON_1); - - status = 0; } #else diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 8b928f9bc1c3..1013a341b0fd 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -272,16 +272,8 @@ struct platform_device s5p_device_fimc3 = { #ifdef CONFIG_S5P_DEV_G2D static struct resource s5p_g2d_resource[] = { - [0] = { - .start = S5P_PA_G2D, - .end = S5P_PA_G2D + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_2D, - .end = IRQ_2D, - .flags = IORESOURCE_IRQ, - }, + [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_2D), }; struct platform_device s5p_device_g2d = { @@ -370,7 +362,6 @@ struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, }; struct platform_device s3c_device_hsmmc0 = { @@ -401,7 +392,6 @@ struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, }; struct platform_device s3c_device_hsmmc1 = { @@ -434,7 +424,6 @@ struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, }; struct platform_device s3c_device_hsmmc2 = { @@ -465,7 +454,6 @@ struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = { .max_width = 4, .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, }; struct platform_device s3c_device_hsmmc3 = { diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index e834c5ef437c..151cc9195cf6 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -33,18 +33,12 @@ enum cd_types { S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */ }; -enum clk_types { - S3C_SDHCI_CLK_DIV_INTERNAL, /* use mmc internal clock divider */ - S3C_SDHCI_CLK_DIV_EXTERNAL, /* use external clock divider */ -}; - /** * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI * @max_width: The maximum number of data bits supported. * @host_caps: Standard MMC host capabilities bit field. * @host_caps2: The second standard MMC host capabilities bit field. * @cd_type: Type of Card Detection method (see cd_types enum above) - * @clk_type: Type of clock divider method (see clk_types enum above) * @ext_cd_init: Initialize external card detect subsystem. Called on * sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL. * notify_func argument is a callback to the sdhci-s3c driver @@ -69,7 +63,6 @@ struct s3c_sdhci_platdata { unsigned int host_caps2; unsigned int pm_caps; enum cd_types cd_type; - enum clk_types clk_type; int ext_cd_gpio; bool ext_cd_gpio_invert; diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c index fa78aa710ed1..b430e9946287 100644 --- a/arch/arm/plat-samsung/platformdata.c +++ b/arch/arm/plat-samsung/platformdata.c @@ -57,6 +57,4 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd, set->host_caps2 |= pd->host_caps2; if (pd->pm_caps) set->pm_caps |= pd->pm_caps; - if (pd->clk_type) - set->clk_type = pd->clk_type; } diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig index 043f7b02a9e7..81ee7cc34457 100644 --- a/arch/arm/plat-versatile/Kconfig +++ b/arch/arm/plat-versatile/Kconfig @@ -5,6 +5,12 @@ config PLAT_VERSATILE_CLCD config PLAT_VERSATILE_FPGA_IRQ bool + select IRQ_DOMAIN + +config PLAT_VERSATILE_FPGA_IRQ_NR + int + default 4 + depends on PLAT_VERSATILE_FPGA_IRQ config PLAT_VERSATILE_LEDS def_bool y if LEDS_CLASS diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c index f0cc8e19b094..6e70d03824a1 100644 --- a/arch/arm/plat-versatile/fpga-irq.c +++ b/arch/arm/plat-versatile/fpga-irq.c @@ -3,7 +3,10 @@ */ #include <linux/irq.h> #include <linux/io.h> +#include <linux/irqdomain.h> +#include <linux/module.h> +#include <asm/exception.h> #include <asm/mach/irq.h> #include <plat/fpga-irq.h> @@ -12,10 +15,32 @@ #define IRQ_ENABLE_SET 0x08 #define IRQ_ENABLE_CLEAR 0x0c +/** + * struct fpga_irq_data - irq data container for the FPGA IRQ controller + * @base: memory offset in virtual memory + * @irq_start: first IRQ number handled by this instance + * @chip: chip container for this instance + * @domain: IRQ domain for this instance + * @valid: mask for valid IRQs on this controller + * @used_irqs: number of active IRQs on this controller + */ +struct fpga_irq_data { + void __iomem *base; + unsigned int irq_start; + struct irq_chip chip; + u32 valid; + struct irq_domain *domain; + u8 used_irqs; +}; + +/* we cannot allocate memory when the controllers are initially registered */ +static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR]; +static int fpga_irq_id; + static void fpga_irq_mask(struct irq_data *d) { struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - f->irq_start); + u32 mask = 1 << d->hwirq; writel(mask, f->base + IRQ_ENABLE_CLEAR); } @@ -23,7 +48,7 @@ static void fpga_irq_mask(struct irq_data *d) static void fpga_irq_unmask(struct irq_data *d) { struct fpga_irq_data *f = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - f->irq_start); + u32 mask = 1 << d->hwirq; writel(mask, f->base + IRQ_ENABLE_SET); } @@ -41,32 +66,93 @@ static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) do { irq = ffs(status) - 1; status &= ~(1 << irq); - - generic_handle_irq(irq + f->irq_start); + generic_handle_irq(irq_find_mapping(f->domain, irq)); } while (status); } -void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f) +/* + * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero + * if we've handled at least one interrupt. This does a single read of the + * status register and handles all interrupts in order from LSB first. + */ +static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs) +{ + int handled = 0; + int irq; + u32 status; + + while ((status = readl(f->base + IRQ_STATUS))) { + irq = ffs(status) - 1; + handle_IRQ(irq_find_mapping(f->domain, irq), regs); + handled = 1; + } + + return handled; +} + +/* + * Keep iterating over all registered FPGA IRQ controllers until there are + * no pending interrupts. + */ +asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs) { - unsigned int i; + int i, handled; + do { + for (i = 0, handled = 0; i < fpga_irq_id; ++i) + handled |= handle_one_fpga(&fpga_irq_devices[i], regs); + } while (handled); +} + +static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct fpga_irq_data *f = d->host_data; + + /* Skip invalid IRQs, only register handlers for the real ones */ + if (!(f->valid & (1 << hwirq))) + return -ENOTSUPP; + irq_set_chip_data(irq, f); + irq_set_chip_and_handler(irq, &f->chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + f->used_irqs++; + return 0; +} + +static struct irq_domain_ops fpga_irqdomain_ops = { + .map = fpga_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, +}; + +void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, + int parent_irq, u32 valid, struct device_node *node) +{ + struct fpga_irq_data *f; + + if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) { + printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__); + return; + } + + f = &fpga_irq_devices[fpga_irq_id]; + f->base = base; + f->irq_start = irq_start; + f->chip.name = name; f->chip.irq_ack = fpga_irq_mask; f->chip.irq_mask = fpga_irq_mask; f->chip.irq_unmask = fpga_irq_unmask; + f->valid = valid; if (parent_irq != -1) { irq_set_handler_data(parent_irq, f); irq_set_chained_handler(parent_irq, fpga_irq_handle); } - for (i = 0; i < 32; i++) { - if (valid & (1 << i)) { - unsigned int irq = f->irq_start + i; + f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0, + &fpga_irqdomain_ops, f); + pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", + fpga_irq_id, name, base, f->used_irqs); - irq_set_chip_data(irq, f); - irq_set_chip_and_handler(irq, &f->chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } + fpga_irq_id++; } diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h index 627fafd1e595..91bcfb67551d 100644 --- a/arch/arm/plat-versatile/include/plat/fpga-irq.h +++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h @@ -1,12 +1,11 @@ #ifndef PLAT_FPGA_IRQ_H #define PLAT_FPGA_IRQ_H -struct fpga_irq_data { - void __iomem *base; - unsigned int irq_start; - struct irq_chip chip; -}; +struct device_node; +struct pt_regs; -void fpga_irq_init(int, u32, struct fpga_irq_data *); +void fpga_handle_irq(struct pt_regs *regs); +void fpga_irq_init(void __iomem *, const char *, int, int, u32, + struct device_node *node); #endif diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index f9c9f33f8cbe..2997e56ce0dd 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -16,7 +16,7 @@ # are merged into mainline or have been edited in the machine database # within the last 12 months. References to machine_is_NAME() do not count! # -# Last update: Tue Dec 6 11:07:38 2011 +# Last update: Thu Apr 26 08:44:23 2012 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -205,6 +205,7 @@ omap_fsample MACH_OMAP_FSAMPLE OMAP_FSAMPLE 970 snapper_cl15 MACH_SNAPPER_CL15 SNAPPER_CL15 986 omap_palmz71 MACH_OMAP_PALMZ71 OMAP_PALMZ71 993 smdk2412 MACH_SMDK2412 SMDK2412 1009 +bkde303 MACH_BKDE303 BKDE303 1021 smdk2413 MACH_SMDK2413 SMDK2413 1022 aml_m5900 MACH_AML_M5900 AML_M5900 1024 balloon3 MACH_BALLOON3 BALLOON3 1029 @@ -381,8 +382,6 @@ davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157 at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 -btmavb101 MACH_BTMAVB101 BTMAVB101 2172 -btmawb101 MACH_BTMAWB101 BTMAWB101 2173 tx25 MACH_TX25 TX25 2177 omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 anw6410 MACH_ANW6410 ANW6410 2183 @@ -397,7 +396,6 @@ net2big_v2 MACH_NET2BIG_V2 NET2BIG_V2 2204 net5big_v2 MACH_NET5BIG_V2 NET5BIG_V2 2206 inetspace_v2 MACH_INETSPACE_V2 INETSPACE_V2 2208 at91sam9g45ekes MACH_AT91SAM9G45EKES AT91SAM9G45EKES 2212 -pc7302 MACH_PC7302 PC7302 2220 spear600 MACH_SPEAR600 SPEAR600 2236 spear300 MACH_SPEAR300 SPEAR300 2237 lilly1131 MACH_LILLY1131 LILLY1131 2239 @@ -407,7 +405,6 @@ d2net MACH_D2NET D2NET 2282 bigdisk MACH_BIGDISK BIGDISK 2283 at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 bcmring MACH_BCMRING BCMRING 2289 -dp6xx MACH_DP6XX DP6XX 2302 mahimahi MACH_MAHIMAHI MAHIMAHI 2304 smdk6442 MACH_SMDK6442 SMDK6442 2324 openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 @@ -444,8 +441,6 @@ mx28evk MACH_MX28EVK MX28EVK 2531 smartq5 MACH_SMARTQ5 SMARTQ5 2534 davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 -riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 -riot_x37 MACH_RIOT_X37 RIOT_X37 2578 pca101 MACH_PCA101 PCA101 2595 capc7117 MACH_CAPC7117 CAPC7117 2612 icontrol MACH_ICONTROL ICONTROL 2624 @@ -460,7 +455,6 @@ spear320 MACH_SPEAR320 SPEAR320 2661 aquila MACH_AQUILA AQUILA 2676 esata_sheevaplug MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678 msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679 -ea2478devkit MACH_EA2478DEVKIT EA2478DEVKIT 2683 terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697 msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703 msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704 @@ -479,8 +473,6 @@ wbd222 MACH_WBD222 WBD222 2753 msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755 msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756 tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758 -nanos MACH_NANOS NANOS 2759 -stamp9g45 MACH_STAMP9G45 STAMP9G45 2761 cns3420vb MACH_CNS3420VB CNS3420VB 2776 omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791 ti8168evm MACH_TI8168EVM TI8168EVM 2800 @@ -490,12 +482,9 @@ eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35SD EUKREA_CPUIMX35SD 2821 eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822 eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823 smdkc210 MACH_SMDKC210 SMDKC210 2838 -pca102 MACH_PCA102 PCA102 2843 +pcaal1 MACH_PCAAL1 PCAAL1 2843 t5325 MACH_T5325 T5325 2846 income MACH_INCOME INCOME 2849 -vvbox_sdorig2 MACH_VVBOX_SDORIG2 VVBOX_SDORIG2 2857 -vvbox_sdlite2 MACH_VVBOX_SDLITE2 VVBOX_SDLITE2 2858 -vvbox_sdpro4 MACH_VVBOX_SDPRO4 VVBOX_SDPRO4 2859 mx257sx MACH_MX257SX MX257SX 2861 goni MACH_GONI GONI 2862 bv07 MACH_BV07 BV07 2882 @@ -504,6 +493,7 @@ devixp MACH_DEVIXP DEVIXP 2885 miccpt MACH_MICCPT MICCPT 2886 mic256 MACH_MIC256 MIC256 2887 u5500 MACH_U5500 U5500 2890 +pov15hd MACH_POV15HD POV15HD 2910 linkstation_lschl MACH_LINKSTATION_LSCHL LINKSTATION_LSCHL 2913 smdkv310 MACH_SMDKV310 SMDKV310 2925 wm8505_7in_netbook MACH_WM8505_7IN_NETBOOK WM8505_7IN_NETBOOK 2928 @@ -537,243 +527,24 @@ trimslice MACH_TRIMSLICE TRIMSLICE 3209 mackerel MACH_MACKEREL MACKEREL 3211 kaen MACH_KAEN KAEN 3217 nokia_rm680 MACH_NOKIA_RM680 NOKIA_RM680 3220 -dm6446_adbox MACH_DM6446_ADBOX DM6446_ADBOX 3226 -quad_salsa MACH_QUAD_SALSA QUAD_SALSA 3227 -abb_gma_1_1 MACH_ABB_GMA_1_1 ABB_GMA_1_1 3228 -svcid MACH_SVCID SVCID 3229 msm8960_sim MACH_MSM8960_SIM MSM8960_SIM 3230 msm8960_rumi3 MACH_MSM8960_RUMI3 MSM8960_RUMI3 3231 -icon_g MACH_ICON_G ICON_G 3232 -mb3 MACH_MB3 MB3 3233 gsia18s MACH_GSIA18S GSIA18S 3234 -pivicc MACH_PIVICC PIVICC 3235 -pcm048 MACH_PCM048 PCM048 3236 -dds MACH_DDS DDS 3237 -chalten_xa1 MACH_CHALTEN_XA1 CHALTEN_XA1 3238 -ts48xx MACH_TS48XX TS48XX 3239 -tonga2_tfttimer MACH_TONGA2_TFTTIMER TONGA2_TFTTIMER 3240 -whistler MACH_WHISTLER WHISTLER 3241 -asl_phoenix MACH_ASL_PHOENIX ASL_PHOENIX 3242 -at91sam9263otlite MACH_AT91SAM9263OTLITE AT91SAM9263OTLITE 3243 -ddplug MACH_DDPLUG DDPLUG 3244 -d2plug MACH_D2PLUG D2PLUG 3245 -kzm9d MACH_KZM9D KZM9D 3246 -verdi_lte MACH_VERDI_LTE VERDI_LTE 3247 -nanozoom MACH_NANOZOOM NANOZOOM 3248 -dm3730_som_lv MACH_DM3730_SOM_LV DM3730_SOM_LV 3249 -dm3730_torpedo MACH_DM3730_TORPEDO DM3730_TORPEDO 3250 -anchovy MACH_ANCHOVY ANCHOVY 3251 -re2rev20 MACH_RE2REV20 RE2REV20 3253 -re2rev21 MACH_RE2REV21 RE2REV21 3254 -cns21xx MACH_CNS21XX CNS21XX 3255 -rider MACH_RIDER RIDER 3257 -nsk330 MACH_NSK330 NSK330 3258 -cns2133evb MACH_CNS2133EVB CNS2133EVB 3259 -z3_816x_mod MACH_Z3_816X_MOD Z3_816X_MOD 3260 -z3_814x_mod MACH_Z3_814X_MOD Z3_814X_MOD 3261 -beect MACH_BEECT BEECT 3262 -dma_thunderbug MACH_DMA_THUNDERBUG DMA_THUNDERBUG 3263 -omn_at91sam9g20 MACH_OMN_AT91SAM9G20 OMN_AT91SAM9G20 3264 -mx25_e2s_uc MACH_MX25_E2S_UC MX25_E2S_UC 3265 -mione MACH_MIONE MIONE 3266 -top9000_tcu MACH_TOP9000_TCU TOP9000_TCU 3267 -top9000_bsl MACH_TOP9000_BSL TOP9000_BSL 3268 -kingdom MACH_KINGDOM KINGDOM 3269 -armadillo460 MACH_ARMADILLO460 ARMADILLO460 3270 -lq2 MACH_LQ2 LQ2 3271 -sweda_tms2 MACH_SWEDA_TMS2 SWEDA_TMS2 3272 mx53_loco MACH_MX53_LOCO MX53_LOCO 3273 -acer_a8 MACH_ACER_A8 ACER_A8 3275 -acer_gauguin MACH_ACER_GAUGUIN ACER_GAUGUIN 3276 -guppy MACH_GUPPY GUPPY 3277 -mx61_ard MACH_MX61_ARD MX61_ARD 3278 tx53 MACH_TX53 TX53 3279 -omapl138_case_a3 MACH_OMAPL138_CASE_A3 OMAPL138_CASE_A3 3280 -uemd MACH_UEMD UEMD 3281 -ccwmx51mut MACH_CCWMX51MUT CCWMX51MUT 3282 -rockhopper MACH_ROCKHOPPER ROCKHOPPER 3283 encore MACH_ENCORE ENCORE 3284 -hkdkc100 MACH_HKDKC100 HKDKC100 3285 -ts42xx MACH_TS42XX TS42XX 3286 -aebl MACH_AEBL AEBL 3287 wario MACH_WARIO WARIO 3288 -gfs_spm MACH_GFS_SPM GFS_SPM 3289 cm_t3730 MACH_CM_T3730 CM_T3730 3290 -isc3 MACH_ISC3 ISC3 3291 -rascal MACH_RASCAL RASCAL 3292 hrefv60 MACH_HREFV60 HREFV60 3293 -tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294 -splendor MACH_SPLENDOR SPLENDOR 3296 -msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298 -htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299 -athene MACH_ATHENE ATHENE 3300 -deep_r_ek_1 MACH_DEEP_R_EK_1 DEEP_R_EK_1 3301 -vivow_ct MACH_VIVOW_CT VIVOW_CT 3302 -nery_1000 MACH_NERY_1000 NERY_1000 3303 -rfl109145_ssrv MACH_RFL109145_SSRV RFL109145_SSRV 3304 -nmh MACH_NMH NMH 3305 -wn802t MACH_WN802T WN802T 3306 -dragonet MACH_DRAGONET DRAGONET 3307 -at91sam9263desk16l MACH_AT91SAM9263DESK16L AT91SAM9263DESK16L 3309 -bcmhana_sv MACH_BCMHANA_SV BCMHANA_SV 3310 -bcmhana_tablet MACH_BCMHANA_TABLET BCMHANA_TABLET 3311 -koi MACH_KOI KOI 3312 -ts4800 MACH_TS4800 TS4800 3313 -tqma9263 MACH_TQMA9263 TQMA9263 3314 -holiday MACH_HOLIDAY HOLIDAY 3315 -pcats_overlay MACH_PCATS_OVERLAY PCATS_OVERLAY 3317 -hwgw6410 MACH_HWGW6410 HWGW6410 3318 -shenzhou MACH_SHENZHOU SHENZHOU 3319 -cwme9210 MACH_CWME9210 CWME9210 3320 -cwme9210js MACH_CWME9210JS CWME9210JS 3321 -colibri_tegra2 MACH_COLIBRI_TEGRA2 COLIBRI_TEGRA2 3323 -w21 MACH_W21 W21 3324 -polysat1 MACH_POLYSAT1 POLYSAT1 3325 -dataway MACH_DATAWAY DATAWAY 3326 -cobral138 MACH_COBRAL138 COBRAL138 3327 -roverpcs8 MACH_ROVERPCS8 ROVERPCS8 3328 -marvelc MACH_MARVELC MARVELC 3329 -navefihid MACH_NAVEFIHID NAVEFIHID 3330 -dm365_cv100 MACH_DM365_CV100 DM365_CV100 3331 -able MACH_ABLE ABLE 3332 -legacy MACH_LEGACY LEGACY 3333 -icong MACH_ICONG ICONG 3334 -rover_g8 MACH_ROVER_G8 ROVER_G8 3335 -t5388p MACH_T5388P T5388P 3336 -dingo MACH_DINGO DINGO 3337 -goflexhome MACH_GOFLEXHOME GOFLEXHOME 3338 -lanreadyfn511 MACH_LANREADYFN511 LANREADYFN511 3340 -omap3_baia MACH_OMAP3_BAIA OMAP3_BAIA 3341 -omap3smartdisplay MACH_OMAP3SMARTDISPLAY OMAP3SMARTDISPLAY 3342 -xilinx MACH_XILINX XILINX 3343 -a2f MACH_A2F A2F 3344 -sky25 MACH_SKY25 SKY25 3345 -ccmx53 MACH_CCMX53 CCMX53 3346 -ccmx53js MACH_CCMX53JS CCMX53JS 3347 -ccwmx53 MACH_CCWMX53 CCWMX53 3348 -ccwmx53js MACH_CCWMX53JS CCWMX53JS 3349 -frisms MACH_FRISMS FRISMS 3350 -msm7x27a_ffa MACH_MSM7X27A_FFA MSM7X27A_FFA 3351 -msm7x27a_surf MACH_MSM7X27A_SURF MSM7X27A_SURF 3352 -msm7x27a_rumi3 MACH_MSM7X27A_RUMI3 MSM7X27A_RUMI3 3353 -dimmsam9g20 MACH_DIMMSAM9G20 DIMMSAM9G20 3354 -dimm_imx28 MACH_DIMM_IMX28 DIMM_IMX28 3355 -amk_a4 MACH_AMK_A4 AMK_A4 3356 -gnet_sgme MACH_GNET_SGME GNET_SGME 3357 -shooter_u MACH_SHOOTER_U SHOOTER_U 3358 -vmx53 MACH_VMX53 VMX53 3359 -rhino MACH_RHINO RHINO 3360 armlex4210 MACH_ARMLEX4210 ARMLEX4210 3361 -swarcoextmodem MACH_SWARCOEXTMODEM SWARCOEXTMODEM 3362 snowball MACH_SNOWBALL SNOWBALL 3363 -pcm049 MACH_PCM049 PCM049 3364 -vigor MACH_VIGOR VIGOR 3365 -oslo_amundsen MACH_OSLO_AMUNDSEN OSLO_AMUNDSEN 3366 -gsl_diamond MACH_GSL_DIAMOND GSL_DIAMOND 3367 -cv2201 MACH_CV2201 CV2201 3368 -cv2202 MACH_CV2202 CV2202 3369 -cv2203 MACH_CV2203 CV2203 3370 -vit_ibox MACH_VIT_IBOX VIT_IBOX 3371 -dm6441_esp MACH_DM6441_ESP DM6441_ESP 3372 -at91sam9x5ek MACH_AT91SAM9X5EK AT91SAM9X5EK 3373 -libra MACH_LIBRA LIBRA 3374 -easycrrh MACH_EASYCRRH EASYCRRH 3375 -tripel MACH_TRIPEL TRIPEL 3376 -endian_mini MACH_ENDIAN_MINI ENDIAN_MINI 3377 xilinx_ep107 MACH_XILINX_EP107 XILINX_EP107 3378 nuri MACH_NURI NURI 3379 -janus MACH_JANUS JANUS 3380 -ddnas MACH_DDNAS DDNAS 3381 -tag MACH_TAG TAG 3382 -tagw MACH_TAGW TAGW 3383 -nitrogen_vm_imx51 MACH_NITROGEN_VM_IMX51 NITROGEN_VM_IMX51 3384 -viprinet MACH_VIPRINET VIPRINET 3385 -bockw MACH_BOCKW BOCKW 3386 -eva2000 MACH_EVA2000 EVA2000 3387 -steelyard MACH_STEELYARD STEELYARD 3388 -nsslsboard MACH_NSSLSBOARD NSSLSBOARD 3392 -geneva_b5 MACH_GENEVA_B5 GENEVA_B5 3393 -spear1340 MACH_SPEAR1340 SPEAR1340 3394 -rexmas MACH_REXMAS REXMAS 3395 -msm8960_cdp MACH_MSM8960_CDP MSM8960_CDP 3396 -msm8960_fluid MACH_MSM8960_FLUID MSM8960_FLUID 3398 -msm8960_apq MACH_MSM8960_APQ MSM8960_APQ 3399 -helios_v2 MACH_HELIOS_V2 HELIOS_V2 3400 -mif10p MACH_MIF10P MIF10P 3401 -iam28 MACH_IAM28 IAM28 3402 -picasso MACH_PICASSO PICASSO 3403 -mr301a MACH_MR301A MR301A 3404 -notle MACH_NOTLE NOTLE 3405 -eelx2 MACH_EELX2 EELX2 3406 -moon MACH_MOON MOON 3407 -ruby MACH_RUBY RUBY 3408 -goldengate MACH_GOLDENGATE GOLDENGATE 3409 -ctbu_gen2 MACH_CTBU_GEN2 CTBU_GEN2 3410 -kmp_am17_01 MACH_KMP_AM17_01 KMP_AM17_01 3411 wtplug MACH_WTPLUG WTPLUG 3412 -mx27su2 MACH_MX27SU2 MX27SU2 3413 -nb31 MACH_NB31 NB31 3414 -hjsdu MACH_HJSDU HJSDU 3415 -td3_rev1 MACH_TD3_REV1 TD3_REV1 3416 -eag_ci4000 MACH_EAG_CI4000 EAG_CI4000 3417 -net5big_nand_v2 MACH_NET5BIG_NAND_V2 NET5BIG_NAND_V2 3418 -cpx2 MACH_CPX2 CPX2 3419 -net2big_nand_v2 MACH_NET2BIG_NAND_V2 NET2BIG_NAND_V2 3420 -ecuv5 MACH_ECUV5 ECUV5 3421 -hsgx6d MACH_HSGX6D HSGX6D 3422 -dawad7 MACH_DAWAD7 DAWAD7 3423 -sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424 -gt_i5700 MACH_GT_I5700 GT_I5700 3425 -ctera_plug_c2 MACH_CTERA_PLUG_C2 CTERA_PLUG_C2 3426 -marvelct MACH_MARVELCT MARVELCT 3427 -ag11005 MACH_AG11005 AG11005 3428 -vangogh MACH_VANGOGH VANGOGH 3430 -matrix505 MACH_MATRIX505 MATRIX505 3431 -oce_nigma MACH_OCE_NIGMA OCE_NIGMA 3432 -t55 MACH_T55 T55 3433 -bio3k MACH_BIO3K BIO3K 3434 -expressct MACH_EXPRESSCT EXPRESSCT 3435 -cardhu MACH_CARDHU CARDHU 3436 -aruba MACH_ARUBA ARUBA 3437 -bonaire MACH_BONAIRE BONAIRE 3438 -nuc700evb MACH_NUC700EVB NUC700EVB 3439 -nuc710evb MACH_NUC710EVB NUC710EVB 3440 -nuc740evb MACH_NUC740EVB NUC740EVB 3441 -nuc745evb MACH_NUC745EVB NUC745EVB 3442 -transcede MACH_TRANSCEDE TRANSCEDE 3443 -mora MACH_MORA MORA 3444 -nda_evm MACH_NDA_EVM NDA_EVM 3445 -timu MACH_TIMU TIMU 3446 -expressh MACH_EXPRESSH EXPRESSH 3447 veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448 -dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449 -omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450 -tritip MACH_TRITIP TRITIP 3451 -sm1k MACH_SM1K SM1K 3452 -monch MACH_MONCH MONCH 3453 -curacao MACH_CURACAO CURACAO 3454 origen MACH_ORIGEN ORIGEN 3455 -epc10 MACH_EPC10 EPC10 3456 -sgh_i740 MACH_SGH_I740 SGH_I740 3457 -tuna MACH_TUNA TUNA 3458 -mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459 -mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460 -acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461 -elke MACH_ELKE ELKE 3462 -sbc6000x MACH_SBC6000X SBC6000X 3463 -r1801e MACH_R1801E R1801E 3464 -h1600 MACH_H1600 H1600 3465 -mini210 MACH_MINI210 MINI210 3466 -mini8168 MACH_MINI8168 MINI8168 3467 -pc7308 MACH_PC7308 PC7308 3468 -kmm2m01 MACH_KMM2M01 KMM2M01 3470 -mx51erebus MACH_MX51EREBUS MX51EREBUS 3471 wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472 -tuxrail MACH_TUXRAIL TUXRAIL 3473 -arthur MACH_ARTHUR ARTHUR 3474 -doorboy MACH_DOORBOY DOORBOY 3475 xarina MACH_XARINA XARINA 3476 -roverx7 MACH_ROVERX7 ROVERX7 3477 sdvr MACH_SDVR SDVR 3478 acer_maya MACH_ACER_MAYA ACER_MAYA 3479 pico MACH_PICO PICO 3480 @@ -999,6 +770,7 @@ promwad_jade MACH_PROMWAD_JADE PROMWAD_JADE 3708 amp MACH_AMP AMP 3709 gnet_amp MACH_GNET_AMP GNET_AMP 3710 toques MACH_TOQUES TOQUES 3711 +apx4devkit MACH_APX4DEVKIT APX4DEVKIT 3712 dct_storm MACH_DCT_STORM DCT_STORM 3713 owl MACH_OWL OWL 3715 cogent_csb1741 MACH_COGENT_CSB1741 COGENT_CSB1741 3716 @@ -1063,7 +835,6 @@ shelter MACH_SHELTER SHELTER 3778 omap3_devkit8500 MACH_OMAP3_DEVKIT8500 OMAP3_DEVKIT8500 3779 edgetd MACH_EDGETD EDGETD 3780 copperyard MACH_COPPERYARD COPPERYARD 3781 -edge MACH_EDGE EDGE 3782 edge_u MACH_EDGE_U EDGE_U 3783 edge_td MACH_EDGE_TD EDGE_TD 3784 wdss MACH_WDSS WDSS 3785 @@ -1169,3 +940,269 @@ elite_ulk MACH_ELITE_ULK ELITE_ULK 3888 pov2 MACH_POV2 POV2 3889 ipod_touch_2g MACH_IPOD_TOUCH_2G IPOD_TOUCH_2G 3890 da850_pqab MACH_DA850_PQAB DA850_PQAB 3891 +fermi MACH_FERMI FERMI 3892 +ccardwmx28 MACH_CCARDWMX28 CCARDWMX28 3893 +ccardmx28 MACH_CCARDMX28 CCARDMX28 3894 +fs20_fcm2050 MACH_FS20_FCM2050 FS20_FCM2050 3895 +kinetis MACH_KINETIS KINETIS 3896 +kai MACH_KAI KAI 3897 +bcthb2 MACH_BCTHB2 BCTHB2 3898 +inels3_cu MACH_INELS3_CU INELS3_CU 3899 +da850_apollo MACH_DA850_APOLLO DA850_APOLLO 3901 +tracnas MACH_TRACNAS TRACNAS 3902 +mityarm335x MACH_MITYARM335X MITYARM335X 3903 +xcgz7x MACH_XCGZ7X XCGZ7X 3904 +cubox MACH_CUBOX CUBOX 3905 +terminator MACH_TERMINATOR TERMINATOR 3906 +eye03 MACH_EYE03 EYE03 3907 +kota3 MACH_KOTA3 KOTA3 3908 +pscpe MACH_PSCPE PSCPE 3910 +akt1100 MACH_AKT1100 AKT1100 3911 +pcaaxl2 MACH_PCAAXL2 PCAAXL2 3912 +primodd_ct MACH_PRIMODD_CT PRIMODD_CT 3913 +nsbc MACH_NSBC NSBC 3914 +meson2_skt MACH_MESON2_SKT MESON2_SKT 3915 +meson2_ref MACH_MESON2_REF MESON2_REF 3916 +ccardwmx28js MACH_CCARDWMX28JS CCARDWMX28JS 3917 +ccardmx28js MACH_CCARDMX28JS CCARDMX28JS 3918 +indico MACH_INDICO INDICO 3919 +msm8960dt MACH_MSM8960DT MSM8960DT 3920 +primods MACH_PRIMODS PRIMODS 3921 +beluga_m1388 MACH_BELUGA_M1388 BELUGA_M1388 3922 +primotd MACH_PRIMOTD PRIMOTD 3923 +varan_master MACH_VARAN_MASTER VARAN_MASTER 3924 +primodd MACH_PRIMODD PRIMODD 3925 +jetduo MACH_JETDUO JETDUO 3926 +mx53_umobo MACH_MX53_UMOBO MX53_UMOBO 3927 +trats MACH_TRATS TRATS 3928 +starcraft MACH_STARCRAFT STARCRAFT 3929 +qseven_tegra2 MACH_QSEVEN_TEGRA2 QSEVEN_TEGRA2 3930 +lichee_sun4i_devbd MACH_LICHEE_SUN4I_DEVBD LICHEE_SUN4I_DEVBD 3931 +movenow MACH_MOVENOW MOVENOW 3932 +golf_u MACH_GOLF_U GOLF_U 3933 +msm7627a_evb MACH_MSM7627A_EVB MSM7627A_EVB 3934 +rambo MACH_RAMBO RAMBO 3935 +golfu MACH_GOLFU GOLFU 3936 +mango310 MACH_MANGO310 MANGO310 3937 +dns343 MACH_DNS343 DNS343 3938 +var_som_om44 MACH_VAR_SOM_OM44 VAR_SOM_OM44 3939 +naon MACH_NAON NAON 3940 +vp4000 MACH_VP4000 VP4000 3941 +impcard MACH_IMPCARD IMPCARD 3942 +smoovcam MACH_SMOOVCAM SMOOVCAM 3943 +cobham3725 MACH_COBHAM3725 COBHAM3725 3944 +cobham3730 MACH_COBHAM3730 COBHAM3730 3945 +cobham3703 MACH_COBHAM3703 COBHAM3703 3946 +quetzal MACH_QUETZAL QUETZAL 3947 +apq8064_cdp MACH_APQ8064_CDP APQ8064_CDP 3948 +apq8064_mtp MACH_APQ8064_MTP APQ8064_MTP 3949 +apq8064_fluid MACH_APQ8064_FLUID APQ8064_FLUID 3950 +apq8064_liquid MACH_APQ8064_LIQUID APQ8064_LIQUID 3951 +mango210 MACH_MANGO210 MANGO210 3952 +mango100 MACH_MANGO100 MANGO100 3953 +mango24 MACH_MANGO24 MANGO24 3954 +mango64 MACH_MANGO64 MANGO64 3955 +nsa320 MACH_NSA320 NSA320 3956 +elv_ccu2 MACH_ELV_CCU2 ELV_CCU2 3957 +triton_x00 MACH_TRITON_X00 TRITON_X00 3958 +triton_1500_2000 MACH_TRITON_1500_2000 TRITON_1500_2000 3959 +pogoplugv4 MACH_POGOPLUGV4 POGOPLUGV4 3960 +venus_cl MACH_VENUS_CL VENUS_CL 3961 +vulcano_g20 MACH_VULCANO_G20 VULCANO_G20 3962 +sgs_i9100 MACH_SGS_I9100 SGS_I9100 3963 +stsv2 MACH_STSV2 STSV2 3964 +csb1724 MACH_CSB1724 CSB1724 3965 +omapl138_lcdk MACH_OMAPL138_LCDK OMAPL138_LCDK 3966 +pvd_mx25 MACH_PVD_MX25 PVD_MX25 3968 +meson6_skt MACH_MESON6_SKT MESON6_SKT 3969 +meson6_ref MACH_MESON6_REF MESON6_REF 3970 +pxm MACH_PXM PXM 3971 +pogoplugv3 MACH_POGOPLUGV3 POGOPLUGV3 3973 +mlp89626 MACH_MLP89626 MLP89626 3974 +iomegahmndce MACH_IOMEGAHMNDCE IOMEGAHMNDCE 3975 +pogoplugv3pci MACH_POGOPLUGV3PCI POGOPLUGV3PCI 3976 +bntv250 MACH_BNTV250 BNTV250 3977 +mx53_qseven MACH_MX53_QSEVEN MX53_QSEVEN 3978 +gtl_it1100 MACH_GTL_IT1100 GTL_IT1100 3979 +mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980 +mt4 MACH_MT4 MT4 3981 +jumbo_d MACH_JUMBO_D JUMBO_D 3982 +jumbo_i MACH_JUMBO_I JUMBO_I 3983 +fs20_dmp MACH_FS20_DMP FS20_DMP 3984 +dns320 MACH_DNS320 DNS320 3985 +mx28bacos MACH_MX28BACOS MX28BACOS 3986 +tl80 MACH_TL80 TL80 3987 +polatis_nic_1001 MACH_POLATIS_NIC_1001 POLATIS_NIC_1001 3988 +tely MACH_TELY TELY 3989 +u8520 MACH_U8520 U8520 3990 +manta MACH_MANTA MANTA 3991 +mpq8064_cdp MACH_MPQ8064_CDP MPQ8064_CDP 3993 +mpq8064_dtv MACH_MPQ8064_DTV MPQ8064_DTV 3995 +dm368som MACH_DM368SOM DM368SOM 3996 +gprisb2 MACH_GPRISB2 GPRISB2 3997 +chammid MACH_CHAMMID CHAMMID 3998 +seoul2 MACH_SEOUL2 SEOUL2 3999 +omap4_nooktablet MACH_OMAP4_NOOKTABLET OMAP4_NOOKTABLET 4000 +aalto MACH_AALTO AALTO 4001 +metro MACH_METRO METRO 4002 +cydm3730 MACH_CYDM3730 CYDM3730 4003 +tqma53 MACH_TQMA53 TQMA53 4004 +msm7627a_qrd3 MACH_MSM7627A_QRD3 MSM7627A_QRD3 4005 +mx28_canby MACH_MX28_CANBY MX28_CANBY 4006 +tiger MACH_TIGER TIGER 4007 +pcats_9307_type_a MACH_PCATS_9307_TYPE_A PCATS_9307_TYPE_A 4008 +pcats_9307_type_o MACH_PCATS_9307_TYPE_O PCATS_9307_TYPE_O 4009 +pcats_9307_type_r MACH_PCATS_9307_TYPE_R PCATS_9307_TYPE_R 4010 +streamplug MACH_STREAMPLUG STREAMPLUG 4011 +icechicken_dev MACH_ICECHICKEN_DEV ICECHICKEN_DEV 4012 +hedgehog MACH_HEDGEHOG HEDGEHOG 4013 +yusend_obc MACH_YUSEND_OBC YUSEND_OBC 4014 +imxninja MACH_IMXNINJA IMXNINJA 4015 +omap4_jarod MACH_OMAP4_JAROD OMAP4_JAROD 4016 +eco5_pk MACH_ECO5_PK ECO5_PK 4017 +qj2440 MACH_QJ2440 QJ2440 4018 +mx6q_mercury MACH_MX6Q_MERCURY MX6Q_MERCURY 4019 +cm6810 MACH_CM6810 CM6810 4020 +omap4_torpedo MACH_OMAP4_TORPEDO OMAP4_TORPEDO 4021 +nsa310 MACH_NSA310 NSA310 4022 +tmx536 MACH_TMX536 TMX536 4023 +ktt20 MACH_KTT20 KTT20 4024 +dragonix MACH_DRAGONIX DRAGONIX 4025 +lungching MACH_LUNGCHING LUNGCHING 4026 +bulogics MACH_BULOGICS BULOGICS 4027 +mx535_sx MACH_MX535_SX MX535_SX 4028 +ngui3250 MACH_NGUI3250 NGUI3250 4029 +salutec_dac MACH_SALUTEC_DAC SALUTEC_DAC 4030 +loco MACH_LOCO LOCO 4031 +ctera_plug_usi MACH_CTERA_PLUG_USI CTERA_PLUG_USI 4032 +scepter MACH_SCEPTER SCEPTER 4033 +sga MACH_SGA SGA 4034 +p_81_j5 MACH_P_81_J5 P_81_J5 4035 +p_81_o4 MACH_P_81_O4 P_81_O4 4036 +msm8625_surf MACH_MSM8625_SURF MSM8625_SURF 4037 +carallon_shark MACH_CARALLON_SHARK CARALLON_SHARK 4038 +ordog MACH_ORDOG ORDOG 4040 +puente_io MACH_PUENTE_IO PUENTE_IO 4041 +msm8625_evb MACH_MSM8625_EVB MSM8625_EVB 4042 +ev_am1707 MACH_EV_AM1707 EV_AM1707 4043 +ev_am1707e2 MACH_EV_AM1707E2 EV_AM1707E2 4044 +ev_am3517e2 MACH_EV_AM3517E2 EV_AM3517E2 4045 +calabria MACH_CALABRIA CALABRIA 4046 +ev_imx287 MACH_EV_IMX287 EV_IMX287 4047 +erau MACH_ERAU ERAU 4048 +sichuan MACH_SICHUAN SICHUAN 4049 +davinci_da850 MACH_DAVINCI_DA850 DAVINCI_DA850 4051 +omap138_trunarc MACH_OMAP138_TRUNARC OMAP138_TRUNARC 4052 +bcm4761 MACH_BCM4761 BCM4761 4053 +picasso_e2 MACH_PICASSO_E2 PICASSO_E2 4054 +picasso_mf MACH_PICASSO_MF PICASSO_MF 4055 +miro MACH_MIRO MIRO 4056 +at91sam9g20ewon3 MACH_AT91SAM9G20EWON3 AT91SAM9G20EWON3 4057 +yoyo MACH_YOYO YOYO 4058 +windjkl MACH_WINDJKL WINDJKL 4059 +monarudo MACH_MONARUDO MONARUDO 4060 +batan MACH_BATAN BATAN 4061 +tadao MACH_TADAO TADAO 4062 +baso MACH_BASO BASO 4063 +mahon MACH_MAHON MAHON 4064 +villec2 MACH_VILLEC2 VILLEC2 4065 +asi1230 MACH_ASI1230 ASI1230 4066 +alaska MACH_ALASKA ALASKA 4067 +swarco_shdsl2 MACH_SWARCO_SHDSL2 SWARCO_SHDSL2 4068 +oxrtu MACH_OXRTU OXRTU 4069 +omap5_panda MACH_OMAP5_PANDA OMAP5_PANDA 4070 +c8000 MACH_C8000 C8000 4072 +bje_display3_5 MACH_BJE_DISPLAY3_5 BJE_DISPLAY3_5 4073 +picomod7 MACH_PICOMOD7 PICOMOD7 4074 +picocom5 MACH_PICOCOM5 PICOCOM5 4075 +qblissa8 MACH_QBLISSA8 QBLISSA8 4076 +armstonea8 MACH_ARMSTONEA8 ARMSTONEA8 4077 +netdcu14 MACH_NETDCU14 NETDCU14 4078 +at91sam9x5_epiphan MACH_AT91SAM9X5_EPIPHAN AT91SAM9X5_EPIPHAN 4079 +p2u MACH_P2U P2U 4080 +doris MACH_DORIS DORIS 4081 +j49 MACH_J49 J49 4082 +vdss2e MACH_VDSS2E VDSS2E 4083 +vc300 MACH_VC300 VC300 4084 +ns115_pad_test MACH_NS115_PAD_TEST NS115_PAD_TEST 4085 +ns115_pad_ref MACH_NS115_PAD_REF NS115_PAD_REF 4086 +ns115_phone_test MACH_NS115_PHONE_TEST NS115_PHONE_TEST 4087 +ns115_phone_ref MACH_NS115_PHONE_REF NS115_PHONE_REF 4088 +golfc MACH_GOLFC GOLFC 4089 +xerox_olympus MACH_XEROX_OLYMPUS XEROX_OLYMPUS 4090 +mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091 +csb1701_csb1726 MACH_CSB1701_CSB1726 CSB1701_CSB1726 4092 +at91sam9xeek MACH_AT91SAM9XEEK AT91SAM9XEEK 4093 +ebv210 MACH_EBV210 EBV210 4094 +msm7627a_qrd7 MACH_MSM7627A_QRD7 MSM7627A_QRD7 4095 +svthin MACH_SVTHIN SVTHIN 4096 +duovero MACH_DUOVERO DUOVERO 4097 +chupacabra MACH_CHUPACABRA CHUPACABRA 4098 +scorpion MACH_SCORPION SCORPION 4099 +davinci_he_hmi10 MACH_DAVINCI_HE_HMI10 DAVINCI_HE_HMI10 4100 +topkick MACH_TOPKICK TOPKICK 4101 +m3_auguestrush MACH_M3_AUGUESTRUSH M3_AUGUESTRUSH 4102 +ipc335x MACH_IPC335X IPC335X 4103 +sun4i MACH_SUN4I SUN4I 4104 +imx233_olinuxino MACH_IMX233_OLINUXINO IMX233_OLINUXINO 4105 +k2_wl MACH_K2_WL K2_WL 4106 +k2_ul MACH_K2_UL K2_UL 4107 +k2_cl MACH_K2_CL K2_CL 4108 +minbari_w MACH_MINBARI_W MINBARI_W 4109 +minbari_m MACH_MINBARI_M MINBARI_M 4110 +k035 MACH_K035 K035 4111 +ariel MACH_ARIEL ARIEL 4112 +arielsaarc MACH_ARIELSAARC ARIELSAARC 4113 +arieldkb MACH_ARIELDKB ARIELDKB 4114 +armadillo810 MACH_ARMADILLO810 ARMADILLO810 4115 +tam335x MACH_TAM335X TAM335X 4116 +grouper MACH_GROUPER GROUPER 4117 +mpcsa21_9g20 MACH_MPCSA21_9G20 MPCSA21_9G20 4118 +m6u_cpu MACH_M6U_CPU M6U_CPU 4119 +davinci_dp10 MACH_DAVINCI_DP10 DAVINCI_DP10 4120 +ginkgo MACH_GINKGO GINKGO 4121 +cgt_qmx6 MACH_CGT_QMX6 CGT_QMX6 4122 +profpga MACH_PROFPGA PROFPGA 4123 +acfx100oc MACH_ACFX100OC ACFX100OC 4124 +acfx100nb MACH_ACFX100NB ACFX100NB 4125 +capricorn MACH_CAPRICORN CAPRICORN 4126 +pisces MACH_PISCES PISCES 4127 +aries MACH_ARIES ARIES 4128 +cancer MACH_CANCER CANCER 4129 +leo MACH_LEO LEO 4130 +virgo MACH_VIRGO VIRGO 4131 +sagittarius MACH_SAGITTARIUS SAGITTARIUS 4132 +devil MACH_DEVIL DEVIL 4133 +ballantines MACH_BALLANTINES BALLANTINES 4134 +omap3_procerusvpu MACH_OMAP3_PROCERUSVPU OMAP3_PROCERUSVPU 4135 +my27 MACH_MY27 MY27 4136 +sun6i MACH_SUN6I SUN6I 4137 +sun5i MACH_SUN5I SUN5I 4138 +mx512_mx MACH_MX512_MX MX512_MX 4139 +kzm9g MACH_KZM9G KZM9G 4140 +vdstbn MACH_VDSTBN VDSTBN 4141 +cfa10036 MACH_CFA10036 CFA10036 4142 +cfa10049 MACH_CFA10049 CFA10049 4143 +pcm051 MACH_PCM051 PCM051 4144 +vybrid_vf7xx MACH_VYBRID_VF7XX VYBRID_VF7XX 4145 +vybrid_vf6xx MACH_VYBRID_VF6XX VYBRID_VF6XX 4146 +vybrid_vf5xx MACH_VYBRID_VF5XX VYBRID_VF5XX 4147 +vybrid_vf4xx MACH_VYBRID_VF4XX VYBRID_VF4XX 4148 +aria_g25 MACH_ARIA_G25 ARIA_G25 4149 +bcm21553 MACH_BCM21553 BCM21553 4150 +smdk5410 MACH_SMDK5410 SMDK5410 4151 +lpc18xx MACH_LPC18XX LPC18XX 4152 +oratisparty MACH_ORATISPARTY ORATISPARTY 4153 +qseven MACH_QSEVEN QSEVEN 4154 +gmv_generic MACH_GMV_GENERIC GMV_GENERIC 4155 +th_link_eth MACH_TH_LINK_ETH TH_LINK_ETH 4156 +tn_muninn MACH_TN_MUNINN TN_MUNINN 4157 +rampage MACH_RAMPAGE RAMPAGE 4158 +visstrim_mv10 MACH_VISSTRIM_MV10 VISSTRIM_MV10 4159 +mx28_wilma MACH_MX28_WILMA MX28_WILMA 4164 +msm8625_ffa MACH_MSM8625_FFA MSM8625_FFA 4166 +vpu101 MACH_VPU101 VPU101 4167 +baileys MACH_BAILEYS BAILEYS 4169 +familybox MACH_FAMILYBOX FAMILYBOX 4170 +ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171 +sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172 diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index bc683b8219b5..586961929e96 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -11,6 +11,7 @@ #include <linux/types.h> #include <linux/cpu.h> #include <linux/cpu_pm.h> +#include <linux/hardirq.h> #include <linux/kernel.h> #include <linux/notifier.h> #include <linux/signal.h> @@ -240,11 +241,11 @@ static void vfp_panic(char *reason, u32 inst) { int i; - printk(KERN_ERR "VFP: Error: %s\n", reason); - printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", + pr_err("VFP: Error: %s\n", reason); + pr_err("VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", fmrx(FPEXC), fmrx(FPSCR), inst); for (i = 0; i < 32; i += 2) - printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n", + pr_err("VFP: s%2u: 0x%08x s%2u: 0x%08x\n", i, vfp_get_float(i), i+1, vfp_get_float(i+1)); } @@ -432,7 +433,10 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) static void vfp_enable(void *unused) { - u32 access = get_copro_access(); + u32 access; + + BUG_ON(preemptible()); + access = get_copro_access(); /* * Enable full access to VFP (cp10 and cp11) @@ -448,7 +452,7 @@ static int vfp_pm_suspend(void) /* if vfp is on, then save state for resumption */ if (fpexc & FPEXC_EN) { - printk(KERN_DEBUG "%s: saving vfp state\n", __func__); + pr_debug("%s: saving vfp state\n", __func__); vfp_save_state(&ti->vfpstate, fpexc); /* disable, just in case */ @@ -573,12 +577,6 @@ int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, * entry. */ hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK); - - /* - * Disable VFP in the hwstate so that we can detect if it gets - * used. - */ - hwstate->fpexc &= ~FPEXC_EN; return 0; } @@ -591,12 +589,8 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp, unsigned long fpexc; int err = 0; - /* - * If VFP has been used, then disable it to avoid corrupting - * the new thread state. - */ - if (hwstate->fpexc & FPEXC_EN) - vfp_flush_hwstate(thread); + /* Disable VFP to avoid corrupting the new thread state. */ + vfp_flush_hwstate(thread); /* * Copy the floating point registers. There can be unused @@ -657,7 +651,7 @@ static int __init vfp_init(void) unsigned int cpu_arch = cpu_architecture(); if (cpu_arch >= CPU_ARCH_ARMv6) - vfp_enable(NULL); + on_each_cpu(vfp_enable, NULL, 1); /* * First check that there is a VFP that we can use. @@ -670,18 +664,16 @@ static int __init vfp_init(void) barrier(); vfp_vector = vfp_null_entry; - printk(KERN_INFO "VFP support v0.3: "); + pr_info("VFP support v0.3: "); if (VFP_arch) - printk("not present\n"); + pr_cont("not present\n"); else if (vfpsid & FPSID_NODOUBLE) { - printk("no double precision support\n"); + pr_cont("no double precision support\n"); } else { hotcpu_notifier(vfp_hotplug, 0); - smp_call_function(vfp_enable, NULL, 1); - VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */ - printk("implementor %02x architecture %d part %02x variant %x rev %x\n", + pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n", (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT, (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT, (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, |
