diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2006-01-04 19:55:53 +0000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-01-09 15:44:32 +1100 |
| commit | c902be71dc6d5e8473bd021feafc8c3608e2b82a (patch) | |
| tree | 527b15800ed84edd16a5d53d165275a48cea1915 /include/asm-powerpc/cputable.h | |
| parent | 017e0fad3e40ece983527ec88a92b3da8fcdecea (diff) | |
| download | talos-obmc-linux-c902be71dc6d5e8473bd021feafc8c3608e2b82a.tar.gz talos-obmc-linux-c902be71dc6d5e8473bd021feafc8c3608e2b82a.zip | |
[PATCH] cell: enable pause(0) in cpu_idle
This patch enables support for pause(0) power management state
for the Cell Broadband Processor, which is import for power efficient
operation. The pervasive infrastructure will in the future enable
us to introduce more functionality specific to the Cell's
pervasive unit.
From: Maximino Aguilar <maguilar@us.ibm.com>
Signed-off-by: Arnd Bergmann <arndb@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/cputable.h')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index f4d508932467..d8798f31b360 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -105,6 +105,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000) +#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000) #else /* ensure on 32b processors the flags are available for compiling but * don't do anything */ @@ -304,7 +305,8 @@ enum { CPU_FTR_MMCRA_SIHV, CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | - CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT, + CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | + CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO, CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2, #endif |
