diff options
| author | Marek Vasut <marek.vasut@gmail.com> | 2010-10-19 16:19:32 +0200 |
|---|---|---|
| committer | Eric Miao <eric.y.miao@gmail.com> | 2010-12-20 23:14:02 +0800 |
| commit | 1b9169d8a0fe2b41fbbb8d152c8108190865f3cf (patch) | |
| tree | b7aa4266dab7ac291823acdd9ef7f2a1638f10cd /drivers/pcmcia | |
| parent | e60f137b715b0a19b84502c23a09c5af9107399d (diff) | |
| download | talos-obmc-linux-1b9169d8a0fe2b41fbbb8d152c8108190865f3cf.tar.gz talos-obmc-linux-1b9169d8a0fe2b41fbbb8d152c8108190865f3cf.zip | |
ARM: pxa: Update Balloon3 for new FPGA firmware
The new FPGA firmware in Balloon3 uses different methods to control it's bus
control lines. In the new version, there are separate registers to set/clear
bus control lines. This patch updates affected places.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'drivers/pcmcia')
| -rw-r--r-- | drivers/pcmcia/pxa2xx_balloon3.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/pcmcia/pxa2xx_balloon3.c b/drivers/pcmcia/pxa2xx_balloon3.c index dbbdd0063202..453c54c97612 100644 --- a/drivers/pcmcia/pxa2xx_balloon3.c +++ b/drivers/pcmcia/pxa2xx_balloon3.c @@ -39,12 +39,10 @@ static struct pcmcia_irqs irqs[] = { static int balloon3_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { uint16_t ver; - int ret; - static void __iomem *fpga_ver; ver = __raw_readw(BALLOON3_FPGA_VER); - if (ver > 0x0201) - pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. " + if (ver < 0x4f08) + pr_warn("The FPGA code, version 0x%04x, is too old. " "PCMCIA/CF support might be broken in this version!", ver); @@ -97,8 +95,9 @@ static void balloon3_pcmcia_socket_state(struct soc_pcmcia_socket *skt, static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) { - __raw_writew((state->flags & SS_RESET) ? BALLOON3_CF_RESET : 0, - BALLOON3_CF_CONTROL_REG); + __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG | + ((state->flags & SS_RESET) ? + BALLOON3_FPGA_SETnCLR : 0)); return 0; } |
