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| author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-12 11:14:58 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-12 11:14:58 -0500 |
| commit | 22c7e1d4b48f61138a9e81270beaf73e98099adf (patch) | |
| tree | fc570fe0b5031dee9b315903c44afb890f92c617 /drivers/pci/host/pci-exynos.c | |
| parent | dd5bba52d3efe13ea43ca95d72f2ed2cd3f1e612 (diff) | |
| parent | 4c9441d1e64c0ce224771d0985fabd75690a6d53 (diff) | |
| download | talos-obmc-linux-22c7e1d4b48f61138a9e81270beaf73e98099adf.tar.gz talos-obmc-linux-22c7e1d4b48f61138a9e81270beaf73e98099adf.zip | |
Merge branch 'pci/host-designware' into next
* pci/host-designware:
PCI: designware-plat: Remove unused platform data
PCI: designware-plat: Add local struct device pointers
PCI: designware-plat: Remove redundant dw_plat_pcie.mem_base
PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments
PCI: designware: Uninline register accessors
PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()
PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments
PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces
PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll()
PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device()
Diffstat (limited to 'drivers/pci/host/pci-exynos.c')
| -rw-r--r-- | drivers/pci/host/pci-exynos.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 2e2d7f00b9e8..f559b494f300 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -425,22 +425,20 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp) exynos_pcie_msi_init(pp); } -static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, - void __iomem *dbi_base) +static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) { u32 val; exynos_pcie_sideband_dbi_r_mode(pp, true); - val = readl(dbi_base); + val = readl(pp->dbi_base + reg); exynos_pcie_sideband_dbi_r_mode(pp, false); return val; } -static inline void exynos_pcie_writel_rc(struct pcie_port *pp, - u32 val, void __iomem *dbi_base) +static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) { exynos_pcie_sideband_dbi_w_mode(pp, true); - writel(val, dbi_base); + writel(val, pp->dbi_base + reg); exynos_pcie_sideband_dbi_w_mode(pp, false); } |
