diff options
author | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2018-01-04 13:08:56 -0500 |
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committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2018-01-04 13:15:05 -0500 |
commit | 6e6a8b5a38cb04d5ef35d4eb57836126b954e7c8 (patch) | |
tree | 1ea9d8dbba617094c1f8ae2ff4806eeb868ee2c3 /drivers/media/platform/davinci | |
parent | 4a3fad709bbc74c85fffff8903d17b5e35723365 (diff) | |
download | talos-obmc-linux-6e6a8b5a38cb04d5ef35d4eb57836126b954e7c8.tar.gz talos-obmc-linux-6e6a8b5a38cb04d5ef35d4eb57836126b954e7c8.zip |
media: replace all <spaces><tab> occurrences
There are a lot of places where sequences of space/tabs are
found. Get rid of all spaces before tabs.
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'drivers/media/platform/davinci')
-rw-r--r-- | drivers/media/platform/davinci/dm355_ccdc_regs.h | 6 | ||||
-rw-r--r-- | drivers/media/platform/davinci/dm644x_ccdc_regs.h | 4 | ||||
-rw-r--r-- | drivers/media/platform/davinci/isif_regs.h | 6 | ||||
-rw-r--r-- | drivers/media/platform/davinci/vpfe_capture.c | 2 | ||||
-rw-r--r-- | drivers/media/platform/davinci/vpif.h | 4 | ||||
-rw-r--r-- | drivers/media/platform/davinci/vpss.c | 10 |
6 files changed, 16 insertions, 16 deletions
diff --git a/drivers/media/platform/davinci/dm355_ccdc_regs.h b/drivers/media/platform/davinci/dm355_ccdc_regs.h index a753ce262583..20ba390763b5 100644 --- a/drivers/media/platform/davinci/dm355_ccdc_regs.h +++ b/drivers/media/platform/davinci/dm355_ccdc_regs.h @@ -107,7 +107,7 @@ #define CCDC_RAW_IP_MODE 0 #define CCDC_VDHDOUT_INPUT 0 #define CCDC_YCINSWP_RAW (0 << 4) -#define CCDC_EXWEN_DISABLE 0 +#define CCDC_EXWEN_DISABLE 0 #define CCDC_DATAPOL_NORMAL 0 #define CCDC_CCDCFG_FIDMD_LATCH_VSYNC 0 #define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC (1 << 6) @@ -152,7 +152,7 @@ #define CCDC_ALAW_GAMMA_WD_MASK 7 #define CCDC_REC656IF_BT656_EN 3 -#define CCDC_FMTCFG_FMTMODE_MASK 3 +#define CCDC_FMTCFG_FMTMODE_MASK 3 #define CCDC_FMTCFG_FMTMODE_SHIFT 1 #define CCDC_FMTCFG_LNUM_MASK 3 #define CCDC_FMTCFG_LNUM_SHIFT 4 @@ -196,7 +196,7 @@ #define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15) #define CCDC_LATCH_ON_VSYNC_ENABLE (0 << 15) #define CCDC_FPC_ENABLE (1 << 15) -#define CCDC_FPC_FPC_NUM_MASK 0x7FFF +#define CCDC_FPC_FPC_NUM_MASK 0x7FFF #define CCDC_DATA_PACK_ENABLE (1 << 11) #define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF #define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF diff --git a/drivers/media/platform/davinci/dm644x_ccdc_regs.h b/drivers/media/platform/davinci/dm644x_ccdc_regs.h index bece0bd9c9de..ffd89c7ea2b6 100644 --- a/drivers/media/platform/davinci/dm644x_ccdc_regs.h +++ b/drivers/media/platform/davinci/dm644x_ccdc_regs.h @@ -97,7 +97,7 @@ #define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15) #define CCDC_FPC_ENABLE (1 << 15) #define CCDC_FPC_DISABLE 0 -#define CCDC_FPC_FPC_NUM_MASK 0x7FFF +#define CCDC_FPC_FPC_NUM_MASK 0x7FFF #define CCDC_DATA_PACK_ENABLE (1 << 11) #define CCDC_FMTCFG_VPIN_MASK 7 #define CCDC_FMTCFG_VPIN_SHIFT 12 @@ -143,7 +143,7 @@ #define CCDC_REC656IF_BT656_EN 3 #define CCDC_SYN_MODE_VD_POL_NEGATIVE (1 << 2) #define CCDC_CCDCFG_Y8POS_SHIFT 11 -#define CCDC_CCDCFG_BW656_10BIT (1 << 5) +#define CCDC_CCDCFG_BW656_10BIT (1 << 5) #define CCDC_SDOFST_FIELD_INTERLEAVED 0x249 #define CCDC_NO_CULLING 0xffff00ff #endif diff --git a/drivers/media/platform/davinci/isif_regs.h b/drivers/media/platform/davinci/isif_regs.h index a3564abe08ae..97d3ba1614d6 100644 --- a/drivers/media/platform/davinci/isif_regs.h +++ b/drivers/media/platform/davinci/isif_regs.h @@ -35,7 +35,7 @@ #define LINCFG0 0x44 #define LINCFG1 0x48 #define CCOLP 0x4c -#define CRGAIN 0x50 +#define CRGAIN 0x50 #define CGRGAIN 0x54 #define CGBGAIN 0x58 #define CBGAIN 0x5c @@ -46,7 +46,7 @@ #define VDINT0 0x70 #define VDINT1 0x74 #define VDINT2 0x78 -#define MISC 0x7c +#define MISC 0x7c #define CGAMMAWD 0x80 #define REC656IF 0x84 #define CCDCFG 0x88 @@ -191,7 +191,7 @@ #define ISIF_VD_POL_SHIFT 2 #define ISIF_DATAPOL_NORMAL 0 #define ISIF_DATAPOL_SHIFT 6 -#define ISIF_EXWEN_DISABLE 0 +#define ISIF_EXWEN_DISABLE 0 #define ISIF_EXWEN_SHIFT 5 #define ISIF_FRM_FMT_SHIFT 7 #define ISIF_DATASFT_SHIFT 8 diff --git a/drivers/media/platform/davinci/vpfe_capture.c b/drivers/media/platform/davinci/vpfe_capture.c index 498f69b53de3..7d08f0f283a5 100644 --- a/drivers/media/platform/davinci/vpfe_capture.c +++ b/drivers/media/platform/davinci/vpfe_capture.c @@ -1794,7 +1794,7 @@ static int vpfe_probe(struct platform_device *pdev) vfd->fops = &vpfe_fops; vfd->ioctl_ops = &vpfe_ioctl_ops; vfd->tvnorms = 0; - vfd->v4l2_dev = &vpfe_dev->v4l2_dev; + vfd->v4l2_dev = &vpfe_dev->v4l2_dev; snprintf(vfd->name, sizeof(vfd->name), "%s_V%d.%d.%d", CAPTURE_DRV_NAME, diff --git a/drivers/media/platform/davinci/vpif.h b/drivers/media/platform/davinci/vpif.h index 9956e6788693..2466c7c77deb 100644 --- a/drivers/media/platform/davinci/vpif.h +++ b/drivers/media/platform/davinci/vpif.h @@ -226,11 +226,11 @@ static inline void vpif_clr_bit(u32 reg, u32 bit) (VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL)) /* enabled interrupt on both the fields on vpid_ch0_ctrl register */ -#define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\ +#define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\ (VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL)) /* enabled interrupt on both the fields on vpid_ch1_ctrl register */ -#define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\ +#define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\ (VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL)) #define VPIF_CH_FID_MASK (0x20) diff --git a/drivers/media/platform/davinci/vpss.c b/drivers/media/platform/davinci/vpss.c index f2d27b932999..b73886519f4f 100644 --- a/drivers/media/platform/davinci/vpss.c +++ b/drivers/media/platform/davinci/vpss.c @@ -59,9 +59,9 @@ MODULE_AUTHOR("Texas Instruments"); #define DM365_ISP5_INTSEL1 0x10 #define DM365_ISP5_INTSEL2 0x14 #define DM365_ISP5_INTSEL3 0x18 -#define DM365_ISP5_CCDCMUX 0x20 -#define DM365_ISP5_PG_FRAME_SIZE 0x28 -#define DM365_VPBE_CLK_CTRL 0x00 +#define DM365_ISP5_CCDCMUX 0x20 +#define DM365_ISP5_PG_FRAME_SIZE 0x28 +#define DM365_VPBE_CLK_CTRL 0x00 #define VPSS_CLK_CTRL 0x01c40044 #define VPSS_CLK_CTRL_VENCCLKEN BIT(3) @@ -78,8 +78,8 @@ MODULE_AUTHOR("Texas Instruments"); #define DM365_ISP5_INTSEL3_DEFAULT 0x00000015 /* masks and shifts for DM365*/ -#define DM365_CCDC_PG_VD_POL_SHIFT 0 -#define DM365_CCDC_PG_HD_POL_SHIFT 1 +#define DM365_CCDC_PG_VD_POL_SHIFT 0 +#define DM365_CCDC_PG_HD_POL_SHIFT 1 #define CCD_SRC_SEL_MASK (BIT_MASK(5) | BIT_MASK(4)) #define CCD_SRC_SEL_SHIFT 4 |