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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-07-27 13:29:41 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-08-13 16:06:41 +0200 |
| commit | b8fe03827b192a23d04e99c40d72e6b938fa6576 (patch) | |
| tree | 82d621f9a666c191596d7190290004c13c8ce3bf /drivers/iommu/tegra-smmu.c | |
| parent | 4b3c7d10765403ab19628fb7d530b8ce1c50b81d (diff) | |
| download | talos-obmc-linux-b8fe03827b192a23d04e99c40d72e6b938fa6576.tar.gz talos-obmc-linux-b8fe03827b192a23d04e99c40d72e6b938fa6576.zip | |
iommu/tegra-smmu: Split smmu_flush_ptc()
smmu_flush_ptc() is used in two modes: one is to flush an individual
entry, the other is to flush all entries. We know at the call site
which we require. Split the function into smmu_flush_ptc_all() and
smmu_flush_ptc().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/iommu/tegra-smmu.c')
| -rw-r--r-- | drivers/iommu/tegra-smmu.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 42b13c07aeef..5c775b70ef8c 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -165,29 +165,29 @@ static void smmu_flush_dcache(struct page *page, unsigned long offset, #endif } +static void smmu_flush_ptc_all(struct tegra_smmu *smmu) +{ + smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); +} + static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page, unsigned long offset) { - phys_addr_t phys = page ? page_to_phys(page) : 0; + phys_addr_t phys = page_to_phys(page); u32 value; - if (page) { - offset &= ~(smmu->mc->soc->atom_size - 1); + offset &= ~(smmu->mc->soc->atom_size - 1); - if (smmu->mc->soc->num_address_bits > 32) { + if (smmu->mc->soc->num_address_bits > 32) { #ifdef CONFIG_PHYS_ADDR_T_64BIT - value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK; + value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK; #else - value = 0; + value = 0; #endif - smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); - } - - value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR; - } else { - value = SMMU_PTC_FLUSH_TYPE_ALL; + smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); } + value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR; smmu_writel(smmu, value, SMMU_PTC_FLUSH); } @@ -894,7 +894,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev, smmu_writel(smmu, value, SMMU_TLB_CONFIG); - smmu_flush_ptc(smmu, NULL, 0); + smmu_flush_ptc_all(smmu); smmu_flush_tlb(smmu); smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); smmu_flush(smmu); |
