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authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>2016-04-15 02:47:49 +0200
committerAlex Deucher <alexander.deucher@amd.com>2016-05-04 20:23:15 -0400
commit3d02b7fee9c3ece1746f5b06c4143b511383fc6b (patch)
tree8a15635277e2b10b6bd5c282107d975a39b74e76 /drivers/gpu/drm/radeon/si.c
parentb76af4a41927994e130500659866efbd992deb9d (diff)
downloadtalos-obmc-linux-3d02b7fee9c3ece1746f5b06c4143b511383fc6b.tar.gz
talos-obmc-linux-3d02b7fee9c3ece1746f5b06c4143b511383fc6b.zip
drm/radeon: Allow setting shader registers using DMA/COPY packet3 on SI.
Mesa uses a COPY_DATA packet to copy the grid size for indirect dispatches into COMPUTE_USER_DATA_*. Setting those registers with a SET_SH_REG packet is allowed, not allowing them with other packets seems like an oversight. v2: Clarify commit message. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 7afe825ee561..b30e719dd56d 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4364,6 +4364,10 @@ static bool si_vm_reg_valid(u32 reg)
if (reg >= 0x28000)
return true;
+ /* shader regs are also fine */
+ if (reg >= 0xB000 && reg < 0xC000)
+ return true;
+
/* check config regs */
switch (reg) {
case GRBM_GFX_INDEX:
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