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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-06 13:30:40 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-07 07:30:45 -0700 |
| commit | bf9a496a1fa434670285bd592c75d009cbb99720 (patch) | |
| tree | 65a8f98fc68f9b0b8d17fae27e904bb0b9871a85 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | 8bcd3dd417660dce8cf38a731a888f09e8028190 (diff) | |
| download | talos-obmc-linux-bf9a496a1fa434670285bd592c75d009cbb99720.tar.gz talos-obmc-linux-bf9a496a1fa434670285bd592c75d009cbb99720.zip | |
drm/i915/cnl: Also need power well sanitize.
The workaround added in
commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
equests left on by DMC/KVMR")
needs to be applied on Cannonlake as well.
So let's assume any platform using this power well setup
will also need and let's just go ahead and remove if condition.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-11-git-send-email-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 0b3cacd29bac..8a6f287d225b 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -853,8 +853,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, DRM_DEBUG_KMS("Disabling %s\n", power_well->name); } - if (IS_GEN9(dev_priv)) - gen9_sanitize_power_well_requests(dev_priv, power_well); + gen9_sanitize_power_well_requests(dev_priv, power_well); } if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable, |
