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author | Olof Johansson <olof@lixom.net> | 2014-07-19 15:03:08 -0700 |
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committer | Olof Johansson <olof@lixom.net> | 2014-07-19 15:03:08 -0700 |
commit | f37ac9e5a47d72eab5185b0ddc14dfc943cc9589 (patch) | |
tree | 53577aa529e3bbe718459d0626fc6d45ada3dcdd /drivers/gpu/drm/i915/i915_reg.h | |
parent | 4338925434e4bf5ff714055713f3fb9b5fae9037 (diff) | |
parent | fc2cac41ebbfb16da8b036cba6ec6714ab780a6d (diff) | |
download | talos-obmc-linux-f37ac9e5a47d72eab5185b0ddc14dfc943cc9589.tar.gz talos-obmc-linux-f37ac9e5a47d72eab5185b0ddc14dfc943cc9589.zip |
Merge tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung exynos cpuidle update for v3.17" from Kukjin Kim:
- add callbacks exynos_suspend() and exynos_powered_up()
for support cpuidle through mcpm
- skip exynos_cpuidle for exynos5420 because is uses
cpuidle-big-liggle generic cpuidle driver
- add generic functions to calculate cpu number is used
for pmu and this is required for exynos5420 multi-cluster
- add of_device_id structure for big.LITTLE cpuidle and
add "samsung,exynos5420" compatible string for exynos5420
* tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: populate suspend and powered_up callbacks for mcpm
ARM: EXYNOS: do not allow cpuidle registration for exynos5420
cpuidle: big.LITTLE: init driver for exynos5420
cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config
ARM: EXYNOS: add generic function to calculate cpu number
cpuidle: big.LITTLE: add of_device_id structure
+ Linux 3.16-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e691b30b2817..a5bab61bfc00 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -942,6 +942,9 @@ enum punit_power_well { /* * Instruction and interrupt control regs */ +#define PGTBL_CTL 0x02020 +#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ +#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ #define PGTBL_ER 0x02024 #define RENDER_RING_BASE 0x02000 #define BSD_RING_BASE 0x04000 |