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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2016-01-21 15:20:45 +0000 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2016-07-05 16:26:36 +0200 |
| commit | 7d0c6e711549cb623dc98a68bf89e66208263636 (patch) | |
| tree | 6aa1f6e0c234458d903386cd8d1615b5793cc35f /drivers/gpu/drm/etnaviv/state_hi.xml.h | |
| parent | 33688abb2802ff3a230bd2441f765477b94cc89e (diff) | |
| download | talos-obmc-linux-7d0c6e711549cb623dc98a68bf89e66208263636.tar.gz talos-obmc-linux-7d0c6e711549cb623dc98a68bf89e66208263636.zip | |
drm/etnaviv: enable GPU module level clock gating support
Enable GPU module level hardware clock gating, using the conditions
found in the galcore v5 driver.
v2 lst: Split out clock gating enable into separate function, as
there might be more conditions needed for new hardware.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'drivers/gpu/drm/etnaviv/state_hi.xml.h')
| -rw-r--r-- | drivers/gpu/drm/etnaviv/state_hi.xml.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h index 6a7de5f1454a..807a3d9e0dd5 100644 --- a/drivers/gpu/drm/etnaviv/state_hi.xml.h +++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h @@ -218,6 +218,13 @@ Copyright (C) 2015 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000 #define VIVS_PM_MODULE_STATUS 0x00000108 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001 |
