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| author | Markus Elfring <elfring@users.sourceforge.net> | 2017-04-18 11:15:56 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-19 11:29:49 -0700 |
| commit | 34675d67032ae568331a2a230973c7b58ddcaf9d (patch) | |
| tree | 6d0005527c3f58ef618e9bd3208efea7b6f70dc6 /drivers/clk | |
| parent | 3cda284b77cba833baea9a0f5e256a34d249761f (diff) | |
| download | talos-obmc-linux-34675d67032ae568331a2a230973c7b58ddcaf9d.tar.gz talos-obmc-linux-34675d67032ae568331a2a230973c7b58ddcaf9d.zip | |
clk: hi3620: Fix a typo in one variable name
The script "checkpatch.pl" pointed information out like the following.
CHECK: 'seperated' may be misspelled - perhaps 'separated'?
Thus rename the affected variable.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3620.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 33a713ac8fe6..fa0fba653898 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -144,7 +144,7 @@ static struct hisi_divider_clock hi3620_div_clks[] __initdata = { { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, }; -static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = { +static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = { { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, }, { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, }, { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, }, @@ -224,8 +224,8 @@ static void __init hi3620_clk_init(struct device_node *np) clk_data); hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), clk_data); - hisi_clk_register_gate_sep(hi3620_seperated_gate_clks, - ARRAY_SIZE(hi3620_seperated_gate_clks), + hisi_clk_register_gate_sep(hi3620_separated_gate_clks, + ARRAY_SIZE(hi3620_separated_gate_clks), clk_data); } CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init); |
