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| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2017-04-20 02:46:25 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-05-15 09:46:31 +0200 |
| commit | f5ca01141c8c7df5c492b8d9f2e4b784b0822388 (patch) | |
| tree | 3fe417212a0e493ecf3ac2d5277aee761e515670 /drivers/clk/renesas | |
| parent | 0a12c4400c0680131b42080d5a89ef9ec967e144 (diff) | |
| download | talos-obmc-linux-f5ca01141c8c7df5c492b8d9f2e4b784b0822388.tar.gz talos-obmc-linux-f5ca01141c8c7df5c492b8d9f2e4b784b0822388.zip | |
clk: renesas: r8a7795: Add HS-USB ch3 clock
This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 58dd5b6bef0d..5808803cec48 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -196,6 +196,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), + DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), |
