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| author | David S. Miller <davem@sunset.davemloft.net> | 2006-02-01 15:55:21 -0800 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 01:11:32 -0800 |
| commit | 517af33237ecfc3c8a93b335365fa61e741ceca4 (patch) | |
| tree | 58eff40eb4c517c4fd49fd347d38273ee1e1ee4b /arch/sparc64/kernel/vmlinux.lds.S | |
| parent | b0fd4e49aea8a460afab7bc67cd618e2d19291d4 (diff) | |
| download | talos-obmc-linux-517af33237ecfc3c8a93b335365fa61e741ceca4.tar.gz talos-obmc-linux-517af33237ecfc3c8a93b335365fa61e741ceca4.zip | |
[SPARC64]: Access TSB with physical addresses when possible.
This way we don't need to lock the TSB into the TLB.
The trick is that every TSB load/store is registered into
a special instruction patch section. The default uses
virtual addresses, and the patch instructions use physical
address load/stores.
We can't do this on all chips because only cheetah+ and later
have the physical variant of the atomic quad load.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/vmlinux.lds.S')
| -rw-r--r-- | arch/sparc64/kernel/vmlinux.lds.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/vmlinux.lds.S b/arch/sparc64/kernel/vmlinux.lds.S index 467d13a0d5c1..71b943f1c9b1 100644 --- a/arch/sparc64/kernel/vmlinux.lds.S +++ b/arch/sparc64/kernel/vmlinux.lds.S @@ -70,6 +70,10 @@ SECTIONS .con_initcall.init : { *(.con_initcall.init) } __con_initcall_end = .; SECURITY_INIT + . = ALIGN(4); + __tsb_phys_patch = .; + .tsb_phys_patch : { *(.tsb_phys_patch) } + __tsb_phys_patch_end = .; . = ALIGN(8192); __initramfs_start = .; .init.ramfs : { *(.init.ramfs) } |
