diff options
| author | Minghuan Lian <Minghuan.Lian@freescale.com> | 2013-06-21 18:59:14 +0800 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2013-08-07 18:38:05 -0500 |
| commit | f31dd9443afd35696a833c2a32d584a9257abd40 (patch) | |
| tree | 8ff21712b02cbd063c6bb88fe4359e036a0534dd /arch/powerpc/sysdev/fsl_msi.h | |
| parent | 6d854acd24e152254bff798d90b1592cc5956521 (diff) | |
| download | talos-obmc-linux-f31dd9443afd35696a833c2a32d584a9257abd40.tar.gz talos-obmc-linux-f31dd9443afd35696a833c2a32d584a9257abd40.zip | |
powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3
The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank
contains 16 registers, and this patch adds NR_MSI_REG_MAX and
NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank.
MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1
uses different bits definition than MSIIR. This patch adds
ibs_shift and srs_shift to indicate the bits definition of the
MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1
simultaneously.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
[scottwood@freescale.com: reinstated static on all_avail]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_msi.h')
| -rw-r--r-- | arch/powerpc/sysdev/fsl_msi.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h index 8225f8653f78..df9aa9fe0933 100644 --- a/arch/powerpc/sysdev/fsl_msi.h +++ b/arch/powerpc/sysdev/fsl_msi.h @@ -16,9 +16,11 @@ #include <linux/of.h> #include <asm/msi_bitmap.h> -#define NR_MSI_REG 8 +#define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */ +#define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */ +#define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1 #define IRQS_PER_MSI_REG 32 -#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG) +#define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG) #define FSL_PIC_IP_MASK 0x0000000F #define FSL_PIC_IP_MPIC 0x00000001 @@ -31,9 +33,11 @@ struct fsl_msi { unsigned long cascade_irq; u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */ + u32 ibs_shift; /* Shift of interrupt bit select */ + u32 srs_shift; /* Shift of the shared interrupt register select */ void __iomem *msi_regs; u32 feature; - int msi_virqs[NR_MSI_REG]; + int msi_virqs[NR_MSI_REG_MAX]; struct msi_bitmap bitmap; |
