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| author | Kumar Gala <galak@kernel.crashing.org> | 2007-05-15 13:20:05 -0500 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2007-05-17 21:10:17 +1000 |
| commit | 4da421d620fc104adf0b8b3841650c78f0e87b0a (patch) | |
| tree | 2cc051d13240ba595c9f60c2e4b3cbecf2184368 /arch/powerpc/boot | |
| parent | 50cf67075ba071e0532ccc657ad64cfbb2da3c7a (diff) | |
| download | talos-obmc-linux-4da421d620fc104adf0b8b3841650c78f0e87b0a.tar.gz talos-obmc-linux-4da421d620fc104adf0b8b3841650c78f0e87b0a.zip | |
[POWERPC] 85xx: Add device nodes for error reporting devices used by EDAC
Adding memory-controller and l2-cache-controller entries to be used by EDAC
as of_devices for MPC8541 CDS, MPC8544 DS, MPC8555 CDS, and MPC8568 MDS.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8541cds.dts | 16 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8544ds.dts | 16 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8555cds.dts | 16 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8568mds.dts | 16 |
4 files changed, 64 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 5fdcb69554f2..4f2c3af2e052 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -48,6 +48,22 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>; + memory-controller@2000 { + compatible = "fsl,8541-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <2 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,8541-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <40000>; // L2, 256K + interrupt-parent = <&mpic>; + interrupts = <0 2>; + }; + i2c@3000 { device_type = "i2c"; compatible = "fsl-i2c"; diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 6b084605bb4b..3033599e74e8 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -48,6 +48,22 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>; // Filled out by uboot. + memory-controller@2000 { + compatible = "fsl,8544-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <2 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,8544-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <40000>; // L2, 256K + interrupt-parent = <&mpic>; + interrupts = <0 2>; + }; + i2c@3000 { device_type = "i2c"; compatible = "fsl-i2c"; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 68a4795720dc..951ed92f1154 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -48,6 +48,22 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>; + memory-controller@2000 { + compatible = "fsl,8555-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <2 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,8555-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <40000>; // L2, 256K + interrupt-parent = <&mpic>; + interrupts = <0 2>; + }; + i2c@3000 { device_type = "i2c"; compatible = "fsl-i2c"; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 948a3b61bd4a..a123ec9456bc 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -57,6 +57,22 @@ reg = <e0000000 00100000>; bus-frequency = <0>; + memory-controller@2000 { + compatible = "fsl,8568-memory-controller"; + reg = <2000 1000>; + interrupt-parent = <&mpic>; + interrupts = <2 2>; + }; + + l2-cache-controller@20000 { + compatible = "fsl,8568-l2-cache-controller"; + reg = <20000 1000>; + cache-line-size = <20>; // 32 bytes + cache-size = <80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <0 2>; + }; + i2c@3000 { device_type = "i2c"; compatible = "fsl-i2c"; |
