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authorSteven J. Hill <Steven.Hill@imgtec.com>2013-03-25 13:47:29 -0500
committerSteven J. Hill <Steven.Hill@imgtec.com>2013-05-01 16:32:49 -0500
commitb6d92b4a6bdb880b39789c677b952c53a437028d (patch)
treef14d30f02314d75860aa1ed12449410e6659513b /arch/mips/mti-sead3/sead3-setup.c
parentc34c09c81d659e13e15947580198fa652af3ca1a (diff)
downloadtalos-obmc-linux-b6d92b4a6bdb880b39789c677b952c53a437028d.tar.gz
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MIPS: Add option to disable software I/O coherency.
Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Diffstat (limited to 'arch/mips/mti-sead3/sead3-setup.c')
-rw-r--r--arch/mips/mti-sead3/sead3-setup.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c
index f012fd164cee..14633bc80049 100644
--- a/arch/mips/mti-sead3/sead3-setup.c
+++ b/arch/mips/mti-sead3/sead3-setup.c
@@ -13,9 +13,6 @@
#include <asm/mips-boards/generic.h>
#include <asm/prom.h>
-int coherentio; /* 0 => no DMA cache coherency (may be set by user) */
-int hw_coherentio; /* 0 => no HW DMA cache coherency (reflects real HW) */
-
const char *get_system_type(void)
{
return "MIPS SEAD3";
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