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author | Paul Burton <paul.burton@imgtec.com> | 2016-10-05 18:18:21 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2016-10-06 18:04:20 +0200 |
commit | 3f5f0a4475e13345326061f00c68f428232ba2bc (patch) | |
tree | 0ad2657c668b23aafab4692d83c7156e55ca138f /arch/mips/mti-sead3/sead3-int.c | |
parent | eed0eabd12ef061821cbfa20d903476e07645320 (diff) | |
download | talos-obmc-linux-3f5f0a4475e13345326061f00c68f428232ba2bc.tar.gz talos-obmc-linux-3f5f0a4475e13345326061f00c68f428232ba2bc.zip |
MIPS: generic: Convert SEAD-3 to a generic board
Convert the MIPS SEAD-3 board support to be a generic board, supported
by generic kernels.
Because the SEAD-3 boot protocol was defined long ago and we don't want
to force a switch to the UHI protocol, SEAD-3 is added as a legacy board
which is detected by reading the REVISION register. This may technically
not be a valid memory read & future work will include attempting to
handle that gracefully. In practice since SEAD-3 is the only legacy
board supported by the generic kernel so far the read will only happen
on SEAD-3 boards, and even once Malta is converted the same REVISION
register exists there too. Other boards such as Boston, Ci20 & Ci40 will
use the UHI boot protocol & thus not run any of the legacy board detect
functions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14354/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mti-sead3/sead3-int.c')
-rw-r--r-- | arch/mips/mti-sead3/sead3-int.c | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c deleted file mode 100644 index 2e6b73244ecd..000000000000 --- a/arch/mips/mti-sead3/sead3-int.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. - */ -#include <linux/init.h> -#include <linux/irqchip.h> -#include <linux/irqchip/mips-gic.h> - -#include <asm/cpu-info.h> -#include <asm/irq.h> - -void __init arch_init_irq(void) -{ - irqchip_init(); - - pr_info("GIC: %spresent\n", (gic_present) ? "" : "not "); - pr_info("EIC: %s\n", - (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off"); -} - |