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authorChris Dearman <chris@mips.com>2006-06-20 17:15:20 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-06-29 21:10:52 +0100
commit9318c51acd9689505850152cc98277a6d6f2d752 (patch)
tree7a8d49a377bed11ba2a45643c08af47f1222c51b /arch/mips/mm/c-r4k.c
parentf7a849153be3b66326b52dce0d07896b56cb4cd7 (diff)
downloadtalos-obmc-linux-9318c51acd9689505850152cc98277a6d6f2d752.tar.gz
talos-obmc-linux-9318c51acd9689505850152cc98277a6d6f2d752.zip
[MIPS] MIPS32/MIPS64 secondary cache management
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c23
1 files changed, 18 insertions, 5 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 4a43924cd4fc..01450938db8b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1092,6 +1092,7 @@ static int __init probe_scache(void)
extern int r5k_sc_init(void);
extern int rm7k_sc_init(void);
+extern int mips_sc_init(void);
static void __init setup_scache(void)
{
@@ -1139,17 +1140,29 @@ static void __init setup_scache(void)
return;
default:
+ if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+ c->isa_level == MIPS_CPU_ISA_M32R2 ||
+ c->isa_level == MIPS_CPU_ISA_M64R1 ||
+ c->isa_level == MIPS_CPU_ISA_M64R2) {
+#ifdef CONFIG_MIPS_CPU_SCACHE
+ if (mips_sc_init ()) {
+ scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+ printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+ scache_size >> 10,
+ way_string[c->scache.ways], c->scache.linesz);
+ }
+#else
+ if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+#endif
+ return;
+ }
sc_present = 0;
}
if (!sc_present)
return;
- if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
- c->isa_level == MIPS_CPU_ISA_M64R1) &&
- !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
-
/* compute a couple of other cache variables */
c->scache.waysize = scache_size / c->scache.ways;
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