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| author | Huacai Chen <chenhc@lemote.com> | 2018-04-28 11:21:26 +0800 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-07-23 17:56:52 -0700 |
| commit | 97ab1bb4901cb5e1e43f6f7effd44e03d0e7427d (patch) | |
| tree | c456abc666506b5ca0d7be15b64759c7c6afc0c3 /arch/mips/include/asm/mipsregs.h | |
| parent | 7cff3f168999fd1de4a41c5971363f42d49e961f (diff) | |
| download | talos-obmc-linux-97ab1bb4901cb5e1e43f6f7effd44e03d0e7427d.tar.gz talos-obmc-linux-97ab1bb4901cb5e1e43f6f7effd44e03d0e7427d.zip | |
MIPS: Loongson64: Define and use some CP0 registers
Defines CP0_CONFIG3, CP0_CONFIG6, CP0_PAGEGRAIN and use them in
kernel-entry-init.h for Loongson64.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19264/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@mips.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0bc270806ec5..b6237ffbacf5 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -51,6 +51,7 @@ #define CP0_GLOBALNUMBER $3, 1 #define CP0_CONTEXT $4 #define CP0_PAGEMASK $5 +#define CP0_PAGEGRAIN $5, 1 #define CP0_SEGCTL0 $5, 2 #define CP0_SEGCTL1 $5, 3 #define CP0_SEGCTL2 $5, 4 @@ -77,6 +78,7 @@ #define CP0_CONFIG $16 #define CP0_CONFIG3 $16, 3 #define CP0_CONFIG5 $16, 5 +#define CP0_CONFIG6 $16, 6 #define CP0_LLADDR $17 #define CP0_WATCHLO $18 #define CP0_WATCHHI $19 |
