arch: remove blackfin port

The Analog Devices Blackfin port was added in 2007 and was rather
active for a while, but all work on it has come to a standstill
over time, as Analog have changed their product line-up.

Aaron Wu confirmed that the architecture port is no longer relevant,
and multiple people suggested removing blackfin independently because
of some of its oddities like a non-working SMP port, and the amount of
duplication between the chip variants, which cause extra work when
doing cross-architecture changes.

Link: https://docs.blackfin.uclinux.org/
Acked-by: Aaron Wu <Aaron.Wu@analog.com>
Acked-by: Bryan Wu <cooloney@gmail.com>
Cc: Steven Miao <realmz6@gmail.com>
Cc: Mike Frysinger <vapier@chromium.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 0 insertions, 73 deletions

diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c
deleted file mode 100644
index 1fa793ced347..000000000000
--- a/arch/blackfin/mach-bf538/ints-priority.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
-
-	/* Program the IAR0 Register with the configured priority */
-	bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
-			((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
-			((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
-			((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
-			((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
-			((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
-			((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
-			((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
-	bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
-			((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
-			((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
-			((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
-			((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
-			((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
-			((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
-			((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
-	bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
-			((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
-			((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
-			((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
-			((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
-			((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
-			((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
-			((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
-	bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
-			((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
-			((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
-			((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
-			((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
-			((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
-			((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
-
-	bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
-			((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
-			((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
-			((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
-			((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
-			((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
-	bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
-			((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
-			((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
-			((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
-			((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
-			((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
-			((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
-			((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
-	bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
-			((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
-			((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
-
-	SSYNC();
-}