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| author | Jeff Garzik <jgarzik@pretzel.yyz.us> | 2005-06-22 13:10:49 -0400 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-06-22 13:10:49 -0400 |
| commit | 80bd6d7f5e0d872a0f5a151473d2a39d95d210a8 (patch) | |
| tree | b3a36048d6b7de88f7e906624ecb4b98816bb736 /arch/arm/mm/Kconfig | |
| parent | 949d33e70f2c3e93bfe5265a50e40175b1ab1ec1 (diff) | |
| parent | 2a5a68b840cbab31baab2d9b2e1e6de3b289ae1e (diff) | |
| download | talos-obmc-linux-80bd6d7f5e0d872a0f5a151473d2a39d95d210a8.tar.gz talos-obmc-linux-80bd6d7f5e0d872a0f5a151473d2a39d95d210a8.zip | |
Merge /spare/repo/linux-2.6/
Diffstat (limited to 'arch/arm/mm/Kconfig')
| -rw-r--r-- | arch/arm/mm/Kconfig | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 48bac7da8c70..95606b4a3ba6 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -62,7 +62,7 @@ config CPU_ARM720T # ARM920T config CPU_ARM920T bool "Support ARM920T processor" if !ARCH_S3C2410 - depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX + depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 default y if ARCH_S3C2410 select CPU_32v4 select CPU_ABRT_EV4T @@ -228,7 +228,6 @@ config CPU_SA1100 select CPU_CACHE_V4WB select CPU_CACHE_VIVT select CPU_TLB_V4WB - select CPU_MINICACHE # XScale config CPU_XSCALE @@ -239,7 +238,6 @@ config CPU_XSCALE select CPU_ABRT_EV5T select CPU_CACHE_VIVT select CPU_TLB_V4WBI - select CPU_MINICACHE # ARMv6 config CPU_V6 @@ -345,11 +343,6 @@ config CPU_TLB_V4WBI config CPU_TLB_V6 bool -config CPU_MINICACHE - bool - help - Processor has a minicache. - comment "Processor Features" config ARM_THUMB @@ -429,3 +422,11 @@ config HAS_TLS_REG assume directly accessing that register and always obtain the expected value only on ARMv7 and above. +config NEEDS_SYSCALL_FOR_CMPXCHG + bool + default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) + help + SMP on a pre-ARMv6 processor? Well OK then. + Forget about fast user space cmpxchg support. + It is just not possible. + |
