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author | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
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committer | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
commit | 239060b93bb30a4ad55f1ecaa512464a035cc5ba (patch) | |
tree | 77f79810e57d4fc24356eca0cd6db463e8994128 /arch/arm/mach-tegra/common.c | |
parent | 1408b15b98635a13bad2e2a50b3c2ae2ccdf625b (diff) | |
parent | e9203c988234aa512bd45ca32b52e21c7bbfc414 (diff) | |
download | talos-obmc-linux-239060b93bb30a4ad55f1ecaa512464a035cc5ba.tar.gz talos-obmc-linux-239060b93bb30a4ad55f1ecaa512464a035cc5ba.zip |
Merge branch 'kbuild/rc-fixes' into kbuild/kconfig
We need to revert the temporary hack in 71ebc01, hence the merge.
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c new file mode 100644 index 000000000000..039a514b61ef --- /dev/null +++ b/arch/arm/mach-tegra/common.c @@ -0,0 +1,61 @@ +/* + * arch/arm/mach-tegra/board-harmony.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/io.h> + +#include <asm/hardware/cache-l2x0.h> + +#include <mach/iomap.h> + +#include "board.h" +#include "clock.h" + +static __initdata struct tegra_clk_init_table common_clk_init_table[] = { + /* name parent rate enabled */ + { "clk_m", NULL, 0, true }, + { "pll_p", "clk_m", 216000000, true }, + { "pll_p_out1", "pll_p", 28800000, true }, + { "pll_p_out2", "pll_p", 48000000, true }, + { "pll_p_out3", "pll_p", 72000000, true }, + { "pll_p_out4", "pll_p", 108000000, true }, + { "sys", "pll_p_out4", 108000000, true }, + { "hclk", "sys", 108000000, true }, + { "pclk", "hclk", 54000000, true }, + { NULL, NULL, 0, 0}, +}; + +void __init tegra_init_cache(void) +{ +#ifdef CONFIG_CACHE_L2X0 + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + + writel(0x331, p + L2X0_TAG_LATENCY_CTRL); + writel(0x441, p + L2X0_DATA_LATENCY_CTRL); + + l2x0_init(p, 0x6C080001, 0x8200c3fe); +#endif +} + +void __init tegra_common_init(void) +{ + tegra_init_clock(); + tegra_clk_init_from_table(common_clk_init_table); + tegra_init_cache(); +} |