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| author | Grant Likely <grant.likely@secretlab.ca> | 2010-05-25 00:38:26 -0600 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2010-05-25 00:38:26 -0600 |
| commit | b1e50ebcf24668e57f058deb48b0704b5391ed0f (patch) | |
| tree | 17e1b69b249d0738317b732186340c9dd053f1a1 /arch/arm/mach-s3c2410/include/mach/regs-dsc.h | |
| parent | 0c2a2ae32793e3500a15a449612485f5d17dd431 (diff) | |
| parent | 7e125f7b9cbfce4101191b8076d606c517a73066 (diff) | |
| download | talos-obmc-linux-b1e50ebcf24668e57f058deb48b0704b5391ed0f.tar.gz talos-obmc-linux-b1e50ebcf24668e57f058deb48b0704b5391ed0f.zip | |
Merge remote branch 'origin' into secretlab/next-spi
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-dsc.h')
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-dsc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h index 3c3853cd3cf7..98fd4a05587c 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h @@ -19,6 +19,42 @@ #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) #endif +#if defined(CONFIG_CPU_S3C2416) +#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0) +#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4) +#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8) +#define S3C2416_DSC3 S3C2410_GPIOREG(0x110) + +#define S3C2416_SELECT_DSC0 (0 << 30) +#define S3C2416_SELECT_DSC1 (1 << 30) +#define S3C2416_SELECT_DSC2 (2 << 30) +#define S3C2416_SELECT_DSC3 (3 << 30) + +#define S3C2416_DSC_GETSHIFT(x) (x & 30) + +#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28) +#define S3C2416_DSC0_CF_5mA (0 << 28) +#define S3C2416_DSC0_CF_10mA (1 << 28) +#define S3C2416_DSC0_CF_15mA (2 << 28) +#define S3C2416_DSC0_CF_21mA (3 << 28) +#define S3C2416_DSC0_CF_MASK (3 << 28) + +#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26) +#define S3C2416_DSC0_nRBE_5mA (0 << 26) +#define S3C2416_DSC0_nRBE_10mA (1 << 26) +#define S3C2416_DSC0_nRBE_15mA (2 << 26) +#define S3C2416_DSC0_nRBE_21mA (3 << 26) +#define S3C2416_DSC0_nRBE_MASK (3 << 26) + +#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24) +#define S3C2416_DSC0_nROE_5mA (0 << 24) +#define S3C2416_DSC0_nROE_10mA (1 << 24) +#define S3C2416_DSC0_nROE_15mA (2 << 24) +#define S3C2416_DSC0_nROE_21mA (3 << 24) +#define S3C2416_DSC0_nROE_MASK (3 << 24) + +#endif + #if defined(CONFIG_CPU_S3C244X) #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) |
