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authorKalle Jokiniemi <kalle.jokiniemi@digia.com>2009-03-26 15:59:00 +0200
committerKevin Hilman <khilman@deeprootsystems.com>2009-11-11 14:42:26 -0800
commitba50ea7eb9ce663511013b35608cf0753c9ab674 (patch)
treee3dc023dd370a66ece98ba3fdae2f90db871cdbf /arch/arm/mach-omap2/sleep34xx.S
parent133464dc30846282b5f852433d7b6a31f292f886 (diff)
downloadtalos-obmc-linux-ba50ea7eb9ce663511013b35608cf0753c9ab674.tar.gz
talos-obmc-linux-ba50ea7eb9ce663511013b35608cf0753c9ab674.zip
OMAP3: PM: Fix secure SRAM context save/restore
The secure sram context save uses dma channels 0 and 1. In order to avoid collision between kernel DMA transfers and ROM code dma transfers, we need to reserve DMA channels 0 1 on high security devices. A bug in ROM code leaves dma irq status bits uncleared. Hence those irq status bits need to be cleared when restoring DMA context after off mode. There was also a faulty parameter given to PPA in the secure ram context save assembly code, which caused interrupts to be enabled during secure ram context save. This caused the save to fail sometimes, which resulted the saved context to be corrupted, but also left DMA channels in secure mode. The secure mode DMA channels caused "DMA secure error with device 0" errors to be displayed. Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/sleep34xx.S')
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index db75167bc52d..b6abadccb1c6 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -68,7 +68,7 @@ save_secure_ram_debug:
mov r0, #25 @ set service ID for PPA
mov r12, r0 @ copy secure service ID in r12
mov r1, #0 @ set task id for ROM code in r1
- mov r2, #7 @ set some flags in r2, r6
+ mov r2, #4 @ set some flags in r2, r6
mov r6, #0xff
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
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