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| author | Paul Walmsley <paul@pwsan.com> | 2012-09-23 17:15:11 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-09-23 17:15:11 -0600 |
| commit | 2910f14584eddf2bc0db4baec3c6950ef357b52c (patch) | |
| tree | 7396768abc8e9dfcf45e9376ac7405c6ae36339c /arch/arm/mach-omap1/clock_data.c | |
| parent | 5698bd757d55b1bb87edd1a9744ab09c142abfc2 (diff) | |
| parent | 7852ec0536ca39cefffc6301dc77f8ae55592926 (diff) | |
| download | talos-obmc-linux-2910f14584eddf2bc0db4baec3c6950ef357b52c.tar.gz talos-obmc-linux-2910f14584eddf2bc0db4baec3c6950ef357b52c.zip | |
Merge tag 'omap-cleanup-b-for-3.7' into test_v3.6-rc6_ocb3.7_cff3.7_odaf3.7
smatch and string-wrapping cleanups for the OMAP subarch code.
These changes fix some of the more meaningful warnings that smatch
returns for the OMAP subarch code, and unwraps strings that are
wrapped at the 80-column boundary, to conform with the current
practice.
Basic build, boot, and PM logs are available here:
http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
Diffstat (limited to 'arch/arm/mach-omap1/clock_data.c')
| -rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index c007d80dfb62..243e8b2865f5 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -776,11 +776,10 @@ static struct clk_functions omap1_clk_functions = { static void __init omap1_show_rates(void) { - pr_notice("Clocking rate (xtal/DPLL1/MPU): " - "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", - ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, - arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); + pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", + ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); } u32 cpu_mask; @@ -848,8 +847,8 @@ int __init omap1_clk_init(void) if (cpu_is_omap16xx() && crystal_type == 2) ck_ref.rate = 19200000; - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " - "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), + pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", + omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); /* We want to be in syncronous scalable mode */ |
