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| author | Daniel Lezcano <daniel.lezcano@linaro.org> | 2012-01-25 00:56:05 +0100 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2012-02-03 13:42:19 +0100 |
| commit | c54b7bbbd25600007d452909e6fac39fd36bbc98 (patch) | |
| tree | 176c4807f665d5ea6bb696ebb4a252fb7d88250b /arch/arm/mach-at91/pm.h | |
| parent | 9918ceafd4a9e013572e03983f528017c29bb1cb (diff) | |
| download | talos-obmc-linux-c54b7bbbd25600007d452909e6fac39fd36bbc98.tar.gz talos-obmc-linux-c54b7bbbd25600007d452909e6fac39fd36bbc98.zip | |
ARM: at91: coding style fixes
This patch is mindless and does only fix the line length.
The purpose is to facilitate the review of the next patches.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm.h')
| -rw-r--r-- | arch/arm/mach-at91/pm.h | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 218d816427c0..caac65f39838 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -20,9 +20,12 @@ static inline u32 sdram_selfrefresh_enable(void) return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) -#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ - : : "r" (0)) +#define sdram_selfrefresh_disable(saved_lpr) \ + at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) + +#define wait_for_interrupt_enable() \ + asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ + : : "r" (0)) #elif defined(CONFIG_ARCH_AT91SAM9G45) #include <mach/at91sam9_ddrsdr.h> @@ -59,6 +62,7 @@ static inline u32 sdram_selfrefresh_enable(void) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ } while (0) + #define wait_for_interrupt_enable() cpu_do_idle() #else @@ -79,11 +83,15 @@ static inline u32 sdram_selfrefresh_enable(void) saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR); lpr = saved_lpr & ~AT91_SDRAMC_LPCB; - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | + AT91_SDRAMC_LPCB_SELF_REFRESH); return saved_lpr; } -#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) -#define wait_for_interrupt_enable() cpu_do_idle() +#define sdram_selfrefresh_disable(saved_lpr) \ + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) + +#define wait_for_interrupt_enable() \ + cpu_do_idle() #endif |
