diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-01-16 17:25:03 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2014-01-31 14:58:51 -0800 |
| commit | 3933d267835c8b0fd2892e2b851f9b2a3991f6c8 (patch) | |
| tree | f50b1a62b772e3a125cda4599dddabbfdf04456b /arch/arm/boot/dts/qcom-msm8960-cdp.dts | |
| parent | de70af494c468c107eedf90090eb74d6ccf30c4c (diff) | |
| download | talos-obmc-linux-3933d267835c8b0fd2892e2b851f9b2a3991f6c8.tar.gz talos-obmc-linux-3933d267835c8b0fd2892e2b851f9b2a3991f6c8.zip | |
ARM: dts: msm: Add clock controller nodes and hook into uart
Add the necessary DT nodes to probe the clock controllers on MSM
devices as well as hook up the uart nodes to the clock
controllers. This should allow us to boot to a serial console on
all DT enabled MSM platforms.
Cc: David Brown <davidb@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8960-cdp.dts')
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8960-cdp.dts | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 6ccbac77931e..7c30de4fa302 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -2,6 +2,8 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-msm8960.h> + / { model = "Qualcomm MSM8960 CDP"; compatible = "qcom,msm8960-cdp", "qcom,msm8960"; @@ -37,11 +39,27 @@ reg = <0x800000 0x4000>; }; + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + serial@16440000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, <0x16400000 0x1000>; interrupts = <0 154 0x0>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; }; qcom,ssbi@500000 { |
