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| author | Kevin Hilman <khilman@linaro.org> | 2013-12-17 16:23:49 -0800 |
|---|---|---|
| committer | Kevin Hilman <khilman@linaro.org> | 2013-12-17 16:43:34 -0800 |
| commit | a9434e96d9f089e778b440217f815c8e85daf317 (patch) | |
| tree | a8fbebcc67b2b6c992b249d5c29035f9d6a5b309 /arch/arm/boot/dts/hi3620.dtsi | |
| parent | 524b7df9fdebe96f13977ab880df49a3b74dc1a1 (diff) | |
| download | talos-obmc-linux-a9434e96d9f089e778b440217f815c8e85daf317.tar.gz talos-obmc-linux-a9434e96d9f089e778b440217f815c8e85daf317.zip | |
ARM: hi3xxx: add smp support
Enable SMP support on hi3xxx platform
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: Zhang Mingjun <zhang.mingjun@linaro.org>
Tested-by: Li Xin <li.xin@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
[khilman: fix checkpatch errors]
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/hi3620.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index b9d86795ed5a..e311937a1e2c 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -39,6 +39,27 @@ reg = <0x0>; next-level-cache = <&L2>; }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; }; amba { @@ -65,6 +86,17 @@ reg = <0x1000 0x1000>, <0x100 0x100>; }; + sysctrl: system-controller@802000 { + compatible = "hisilicon,sysctrl"; + reg = <0x802000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; + dual_timer0: dual_timer@800000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x800000 0x1000>; @@ -115,6 +147,12 @@ status = "disabled"; }; + timer5: timer@600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = <1 13 0xf01>; + }; + uart0: uart@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb00000 0x1000>; |
