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| author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2014-11-19 12:10:20 +0100 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2014-11-19 12:10:20 +0100 |
| commit | c080d13c1a09d3afccb594e9b2be28940d4b0ef5 (patch) | |
| tree | 7e9bde65ed9909c4b7903636e3317391ccad5e65 /arch/arm/boot/dts/at91sam9x5_can.dtsi | |
| parent | 0df1f2487d2f0d04703f142813d53615d62a1da4 (diff) | |
| parent | 2667c6adfcf686e8c5a5b56e8c7c65af001df2cb (diff) | |
| download | talos-obmc-linux-c080d13c1a09d3afccb594e9b2be28940d4b0ef5.tar.gz talos-obmc-linux-c080d13c1a09d3afccb594e9b2be28940d4b0ef5.zip | |
Merge branch 'at91-3.19-dt' into at91-3.19-dt2
Diffstat (limited to 'arch/arm/boot/dts/at91sam9x5_can.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/at91sam9x5_can.dtsi | 50 |
1 files changed, 45 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi index f44ab7702a12..8eb2f9c1b978 100644 --- a/arch/arm/boot/dts/at91sam9x5_can.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi @@ -1,5 +1,5 @@ /* - * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 * Ethernet interface. * * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> @@ -20,10 +20,50 @@ reg = <29>; }; - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <30>; - }; + can1_clk: can1_clk { + #clock-cells = <0>; + reg = <30>; + }; + }; + }; + + can0: can@f8000000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8000000 0x300>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8004000 0x300>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */ + AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */ + AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */ + }; }; }; }; |
