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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2012-08-16 16:41:08 +0300
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-08-22 20:17:18 +0100
commit11dd586421b3091007e6f084a9211f3baa66f9fc (patch)
tree5e4e33a7ed3d006065433b9d0fbe33ddb9273365 /Documentation
parente586e955aa47f9b4afe6e665798fd2cb074a90f4 (diff)
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ASoC: omap-mcbsp: Add device tree bindings
Device tree support for McBSP modules on OMAP2+ SoC. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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+* Texas Instruments OMAP2+ McBSP module
+
+Required properties:
+- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420
+ "ti,omap2430-mcbsp" for McBSP on OMAP2430
+ "ti,omap3-mcbsp" for McBSP on OMAP3
+ "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC
+- reg: Register location and size, for OMAP4+ as an array:
+ <MPU access base address, size>,
+ <L3 interconnect address, size>;
+- interrupts: Interrupt numbers for the McBSP port, as an array in case the
+ McBSP IP have more interrupt lines:
+ <OCP compliant irq>,
+ <TX irq>,
+ <RX irq>;
+- interrupt-parent: The parent interrupt controller
+- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
+- ti,hwmods: Name of the hwmod associated to the McBSP port
+
+Sidetone support for OMAP3 McBSP2 and 3 ports:
+- sidetone { }: Within this section the following parameters are required:
+- reg: Register location and size for the ST block
+- interrupts: The interrupt number for the ST block
+- interrupt-parent: The parent interrupt controller for the ST block
+
+Example:
+
+mcbsp2: mcbsp@49022000 {
+ compatible = "ti,omap3-mcbsp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x49022000 0xff>;
+ interrupts = <0 17 0x4>, /* OCP compliant interrup */
+ <0 62 0x4>, /* TX interrup */
+ <0 63 0x4>; /* RX interrup */
+ interrupt-parent = <&intc>;
+ ti,buffer-size = <1280>;
+ ti,hwmods = "mcbsp2";
+
+ sidetone {
+ reg = <0x49028000 0xff>;
+ interrupts = <0 4 0x4>;
+ interrupt-parent = <&intc>;
+ };
+};
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