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authorWolfram Sang <w.sang@pengutronix.de>2012-04-05 16:15:24 +0200
committerWolfram Sang <w.sang@pengutronix.de>2012-04-25 22:59:44 +0200
commitc95eeae9e39314273bcda057f27100603d333518 (patch)
tree52ab3eee720240c6556d803574d9bee53f47d06f
parent096407136769ec10690abe1baba092abcb763662 (diff)
downloadtalos-obmc-linux-c95eeae9e39314273bcda057f27100603d333518.tar.gz
talos-obmc-linux-c95eeae9e39314273bcda057f27100603d333518.zip
i2c: mxs: handle spurious interrupt
After an error interrupt setting cmd->err, I see another interrupt that the data engine is empty which clears cmd->err before being processed. So, clear cmd->err at the beginning of a transfer only to handle these consecutive interrupts. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
-rw-r--r--drivers/i2c/busses/i2c-mxs.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 3d471d56bf15..4c37347973e6 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -227,6 +227,7 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
return -EINVAL;
init_completion(&i2c->cmd_complete);
+ i2c->cmd_err = 0;
flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
@@ -299,8 +300,6 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
/* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
i2c->cmd_err = -EIO;
- else
- i2c->cmd_err = 0;
is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
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