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| author | Paul Mundt <lethal@linux-sh.org> | 2007-05-08 15:45:33 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@hera.kernel.org> | 2007-05-09 01:35:01 +0000 |
| commit | 074f98df0547b7d15f78db9a17e985da0c22af28 (patch) | |
| tree | e40128828e295cfabc6a18206df9a0c4ea25c654 | |
| parent | 53f983a90d7908bcece51f86180c7c9b575a1e4d (diff) | |
| download | talos-obmc-linux-074f98df0547b7d15f78db9a17e985da0c22af28.tar.gz talos-obmc-linux-074f98df0547b7d15f78db9a17e985da0c22af28.zip | |
sh: Add 32-bit opcode feature CPU flag.
Add a CPU flag for the CPUs that support 32-bit opcodes, which
gets passed down to userspace.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| -rw-r--r-- | arch/sh/kernel/cpu/sh2a/probe.c | 1 | ||||
| -rw-r--r-- | arch/sh/kernel/setup.c | 2 | ||||
| -rw-r--r-- | include/asm-sh/cpu-features.h | 1 |
3 files changed, 3 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 426f6db01fc6..f455c3509789 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -18,6 +18,7 @@ int __init detect_cpu_and_cache_system(void) { /* Just SH7206 for now .. */ current_cpu_data.type = CPU_SH7206; + current_cpu_data.flags |= CPU_HAS_OP32; current_cpu_data.dcache.ways = 4; current_cpu_data.dcache.way_incr = (1 << 11); diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 477d2a854fc4..c27729135935 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -431,7 +431,7 @@ const char *get_cpu_subtype(struct sh_cpuinfo *c) /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */ static const char *cpu_flags[] = { "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr", - "ptea", "llsc", "l2", NULL + "ptea", "llsc", "l2", "op32", NULL }; static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c) diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h index 4bccd7c032f9..86308aa39731 100644 --- a/include/asm-sh/cpu-features.h +++ b/include/asm-sh/cpu-features.h @@ -20,5 +20,6 @@ #define CPU_HAS_PTEA 0x0020 /* PTEA register */ #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ +#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ #endif /* __ASM_SH_CPU_FEATURES_H */ |
