<feed xmlns='http://www.w3.org/2005/Atom'>
<title>talos-obmc-linux/include/linux/libnvdimm.h, branch dev-4.13-fsi</title>
<subtitle>Talos™ II Linux sources for OpenBMC</subtitle>
<id>https://git.raptorcs.com/git/talos-obmc-linux/atom?h=dev-4.13-fsi</id>
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<updated>2017-07-03T23:54:58+00:00</updated>
<entry>
<title>Merge branch 'for-4.13/dax' into libnvdimm-for-next</title>
<updated>2017-07-03T23:54:58+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-07-03T23:54:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/commit/?id=9d92573fff3ec70785ef1815cc80573f70e7a921'/>
<id>urn:sha1:9d92573fff3ec70785ef1815cc80573f70e7a921</id>
<content type='text'>
</content>
</entry>
<entry>
<title>libnvdimm, acpi, nfit: Add bus level dsm mask for pass thru.</title>
<updated>2017-07-01T15:49:59+00:00</updated>
<author>
<name>Jerry Hoemann</name>
<email>jerry.hoemann@hpe.com</email>
</author>
<published>2017-07-01T03:53:24+00:00</published>
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<id>urn:sha1:7db5bb33add5afe6c64e00516b0c928bfc937466</id>
<content type='text'>
Add a bus level dsm_mask to nvdimm_bus_descriptor to allow the passthru
calling mechanism to specify a different mask from the cmd_mask.

Populate bus_dsm_mask and use it to filter dsm calls that user can
make through the pass thru interface.

Signed-off-by: Jerry Hoemann &lt;jerry.hoemann@hpe.com&gt;
[djbw: use command number constants instead of a magic mask value]
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;</content>
</entry>
<entry>
<title>libnvdimm, pmem: disable dax flushing when pmem is fronting a volatile region</title>
<updated>2017-06-29T16:29:50+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-06-09T16:46:50+00:00</published>
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<id>urn:sha1:0b277961f4484fb3f142caaa1dd1748cb0b2cbee</id>
<content type='text'>
The pmem driver attaches to both persistent and volatile memory ranges
advertised by the ACPI NFIT. When the region is volatile it is redundant
to spend cycles flushing caches at fsync(). Check if the hosting region
is volatile and do not set dax_write_cache() if it is.

Cc: Jan Kara &lt;jack@suse.cz&gt;
Cc: Jeff Moyer &lt;jmoyer@redhat.com&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Matthew Wilcox &lt;mawilcox@microsoft.com&gt;
Cc: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>x86, libnvdimm, pmem: remove global pmem api</title>
<updated>2017-06-27T23:29:54+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-01-14T04:36:58+00:00</published>
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<id>urn:sha1:ca6a4657e5420dec727256717e905ebc3c751352</id>
<content type='text'>
Now that all callers of the pmem api have been converted to dax helpers that
call back to the pmem driver, we can remove include/linux/pmem.h and
asm/pmem.h.

Cc: &lt;x86@kernel.org&gt;
Cc: Jeff Moyer &lt;jmoyer@redhat.com&gt;
Cc: Ingo Molnar &lt;mingo@redhat.com&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Toshi Kani &lt;toshi.kani@hpe.com&gt;
Cc: Oliver O'Halloran &lt;oohall@gmail.com&gt;
Cc: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Reviewed-by: Jan Kara &lt;jack@suse.cz&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, label: populate the type_guid property for v1.2 namespaces</title>
<updated>2017-06-15T21:31:40+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-06-06T18:10:51+00:00</published>
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<id>urn:sha1:faec6f8a1cd2c44e439de35ab3328c5cf7bf52d8</id>
<content type='text'>
The type_guid refers to the "Address Range Type GUID" for the region
backing a namespace as defined the ACPI NFIT (NVDIMM Firmware Interface
Table). This 'type' identifier specifies an access mechanism for the
given namespace. This capability replaces the confusing usage of the
'NSLABEL_FLAG_LOCAL' flag to indicate a block-aperture-mode namespace.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm, label: add v1.2 interleave-set-cookie algorithm</title>
<updated>2017-06-15T21:31:39+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-06-04T01:59:15+00:00</published>
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<id>urn:sha1:c12c48ce869d72029d70666f615cbd8f67fc14e9</id>
<content type='text'>
The interleave-set-cookie algorithm is extended to incorporate all the
same components that are used to generate an nvdimm unique-id. For
backwards compatibility we still maintain the old v1.1 definition.

Reported-by: Nicholas Moulin &lt;nicholas.w.moulin@intel.com&gt;
Reported-by: Kaushik Kanetkar &lt;kaushik.a.kanetkar@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: convert NDD_ flags to use bitops, introduce NDD_LOCKED</title>
<updated>2017-05-04T21:01:24+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-05-04T21:01:24+00:00</published>
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<id>urn:sha1:8f078b38dd382710884ce7abd31a1935c440e6f8</id>
<content type='text'>
This is a preparation patch for handling locked nvdimm label regions, a
new concept as introduced by the latest DSM document on pmem.io [1]. A
future patch will leverage nvdimm_set_locked() at DIMM probe time to
flag regions that can not be enabled. There should be no functional
difference resulting from this change.

[1]: http://pmem.io/documents/NVDIMM_DSM_Interface_Example-V1.3.pdf

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: rework region badblocks clearing</title>
<updated>2017-04-29T22:24:03+00:00</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2017-04-29T22:24:03+00:00</published>
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<id>urn:sha1:23f4984483623cf8621246004228f08fcabf51e4</id>
<content type='text'>
Toshi noticed that the new support for a region-level badblocks missed
the case where errors are cleared due to BTT I/O.

An initial attempt to fix this ran into a "sleeping while atomic"
warning due to taking the nvdimm_bus_lock() in the BTT I/O path to
satisfy the locking requirements of __nvdimm_bus_badblocks_clear().
However, that lock is not needed since we are not acting on any data that
is subject to change under that lock. The badblocks instance has its own
internal lock to handle mutations of the error list.

So, in order to make it clear that we are just acting on region devices,
rename __nvdimm_bus_badblocks_clear() to nvdimm_clear_badblocks_regions().
Eliminate the lock and consolidate all support routines for the new
nvdimm_account_cleared_poison() in drivers/nvdimm/bus.c. Finally, to the
opportunity to cleanup to some unnecessary casts, make the calling
convention of nvdimm_clear_badblocks_regions() clearer by replacing struct
resource with the minimal struct clear_badblocks_context, and use the
DEVICE_ATTR macro.

Cc: Dave Jiang &lt;dave.jiang@intel.com&gt;
Cc: Vishal Verma &lt;vishal.l.verma@intel.com&gt;
Reported-by: Toshi Kani &lt;toshi.kani@hpe.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: fix clear poison locking with spinlock and GFP_NOWAIT allocation</title>
<updated>2017-04-13T21:23:51+00:00</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2017-04-13T21:25:17+00:00</published>
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<id>urn:sha1:b3b454f694db663773bc22002e10909afe9c1739</id>
<content type='text'>
The following warning results from holding a lane spinlock,
preempt_disable(), or the btt map spinlock and then trying to take the
reconfig_mutex to walk the poison list and potentially add new entries.

BUG: sleeping function called from invalid context at kernel/locking/mutex.
c:747
in_atomic(): 1, irqs_disabled(): 0, pid: 17159, name: dd
[..]
Call Trace:
dump_stack+0x85/0xc8
___might_sleep+0x184/0x250
__might_sleep+0x4a/0x90
__mutex_lock+0x58/0x9b0
? nvdimm_bus_lock+0x21/0x30 [libnvdimm]
? __nvdimm_bus_badblocks_clear+0x2f/0x60 [libnvdimm]
? acpi_nfit_forget_poison+0x79/0x80 [nfit]
? _raw_spin_unlock+0x27/0x40
mutex_lock_nested+0x1b/0x20
nvdimm_bus_lock+0x21/0x30 [libnvdimm]
nvdimm_forget_poison+0x25/0x50 [libnvdimm]
nvdimm_clear_poison+0x106/0x140 [libnvdimm]
nsio_rw_bytes+0x164/0x270 [libnvdimm]
btt_write_pg+0x1de/0x3e0 [nd_btt]
? blk_queue_enter+0x30/0x290
btt_make_request+0x11a/0x310 [nd_btt]
? blk_queue_enter+0xb7/0x290
? blk_queue_enter+0x30/0x290
generic_make_request+0x118/0x3b0

A spinlock is introduced to protect the poison list. This allows us to not
having to acquire the reconfig_mutex for touching the poison list. The
add_poison() function has been broken out into two helper functions. One to
allocate the poison entry and the other to apppend the entry. This allows us
to unlock the poison_lock in non-I/O path and continue to be able to allocate
the poison entry with GFP_KERNEL. We will use GFP_NOWAIT in the I/O path in
order to satisfy being in atomic context.

Reviewed-by: Vishal Verma &lt;vishal.l.verma@intel.com&gt;
Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>libnvdimm: add support for clear poison list and badblocks for device dax</title>
<updated>2017-04-13T04:56:43+00:00</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2017-04-07T22:33:31+00:00</published>
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<id>urn:sha1:006358b35c73ab75544fb4509483a81ef1a9c0b2</id>
<content type='text'>
Providing mechanism to clear poison list via the ndctl ND_CMD_CLEAR_ERROR
call. We will update the poison list and also the badblocks at region level
if the region is in dax mode or in pmem mode and not active. In other
words we force badblocks to be cleared through write requests if the
address is currently accessed through a block device, otherwise it can
only be done via the ioctl+dsm path.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Reviewed-by: Johannes Thumshirn &lt;jthumshirn@suse.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
</feed>
