talos-obmc-linux/drivers, branch dev-4.13

ipmi: NPCM7xx KCS BMC: enable interrupt to the host

2018-05-18T08:52:10+00:00

Original kcs_bmc_npcm7xx.c was missing enabling to send interrupt to the host on writes to output buffer. This patch fixes it by setting the bits that enables the generation of IRQn events by hardware control based on the status of the OBF flag. OpenBMC-Staging-Count: 1 Signed-off-by: Avi Fishman Signed-off-by: Joel Stanley

ipmi: kcs_bmc: coding-style fixes

2018-05-18T08:52:10+00:00

OpenBMC-Staging-Count: 1 Signed-off-by: Haiyue Wang Signed-off-by: Corey Minyard [This is is not the same commit as upstream, as the changes to use new type '__poll_t' from linux-4.16-rc1 are not included. This was done because the feature is not a small self contained backport. There is no impact on functionality for dev-4.13] Signed-off-by: Joel Stanley

ipmi: add an NPCM7xx KCS BMC driver

2018-05-18T08:34:22+00:00

This driver exposes the Keyboard Controller Style (KCS) interface on Novoton NPCM7xx SoCs as a character device. Such SOCs are commonly used as a BaseBoard Management Controller (BMC) on a server board, and KCS interface is commonly used to perform the in-band IPMI communication between the server and its BMC. OpenBMC-Staging-Count: 1 Signed-off-by: Avi Fishman Signed-off-by: Haiyue Wang Signed-off-by: Corey Minyard Signed-off-by: Joel Stanley

ipmi: add an Aspeed KCS IPMI BMC driver

2018-05-18T08:34:22+00:00

The KCS (Keyboard Controller Style) interface is used to perform in-band IPMI communication between a server host and its BMC (BaseBoard Management Controllers). This driver exposes the KCS interface on ASpeed SOCs (AST2400 and AST2500) as a character device. Such SOCs are commonly used as BMCs and this driver implements the BMC side of the KCS interface. OpenBMC-Staging-Count: 1 Signed-off-by: Haiyue Wang Signed-off-by: Corey Minyard Signed-off-by: Joel Stanley

ipmi: add a KCS IPMI BMC driver

2018-05-18T08:34:22+00:00

Provides a device driver for the KCS (Keyboard Controller Style) IPMI interface which meets the requirement of the BMC (Baseboard Management Controllers) side for handling the IPMI request from host system software. Signed-off-by: Haiyue Wang [Removed the selectability of IPMI_KCS_BMC, as it doesn't do much good to have it by itself.] Signed-off-by: Corey Minyard Signed-off-by: Joel Stanley

clk: npcm7xx: fix return value check in npcm7xx_clk_init()

2018-05-18T08:34:22+00:00

In case of error, the function ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. OpenBMC-Staging-Count: 1 Fixes: fcfd14369856 ("clk: npcm7xx: add clock controller") Signed-off-by: Wei Yongjun Signed-off-by: Stephen Boyd Signed-off-by: Joel Stanley

pinctrl: npcm: add NPCM7xx pin control driver

2018-05-18T08:34:22+00:00

Add Nuvoton BMC NPCM7xx pin controller driver. The NPCM7XX Pin Controller multi-function routed through the multiplexing block, Each pin supports GPIO functionality (GPIOx) and multiple functions that directly connect the pin to different hardware blocks. OpenBMC-Staging-Count: 1 Signed-off-by: Tomer Maimon [Joel: - changed depend to select for MFD_SYSCON to fix kconfig warn - Fixed unintialised variable warning in npcm_set_drive_strength] Signed-off-by: Joel Stanley

clk: aspeed: Add 24MHz fixed clock

2018-05-18T07:51:50+00:00

Add a 24MHz fixed clock that is provided by the input oscillator. This clock will be used for certain devices, e.g. pwm. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU Signed-off-by: Joel Stanley

hwmon: (pmbus) Use 64bit math for DIRECT format values

2018-05-17T02:29:54+00:00

Power values in the 100s of watt range can easily blow past 32bit math limits when processing everything in microwatts. Use 64bit math instead to avoid these issues on common 32bit ARM BMC platforms. Fixes: 442aba78728e ("hwmon: PMBus device driver") Signed-off-by: Robert Lippert Signed-off-by: Guenter Roeck (cherry picked from commit bd467e4eababe4c04272c1e646f066db02734c79) Signed-off-by: Joel Stanley

fsi/fsi-master-gpio: Delay sampling of FSI data input

2018-05-17T02:26:51+00:00

Most SoC GPIO implementations, including the Aspeed one, have synchronizers on the GPIO inputs. This means that the value read from a GPIO is a couple of clocks old, from whatever clock source feeds those synchronizers. In practice, this means that in no-delay mode, we are using a value that can potentially be a bit too old and too close to the clock edge establishing the data on the other side of the link. The voltage converters we use on some systems make this worse and sensitive to things like voltage fluctuations etc... This is, we believe, the cause of occasional CRC errors encountered during heavy activity on the LPC bus. This is fixed by introducing a dummy GPIO read before the actual data read. It slows down SBEFIFO by about 15% (less than any delay primitive) and the end result is so far solid. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Christopher Bostic Signed-off-by: Joel Stanley