<feed xmlns='http://www.w3.org/2005/Atom'>
<title>talos-obmc-linux/drivers/nvme, branch dev-4.13</title>
<subtitle>Talos™ II Linux sources for OpenBMC</subtitle>
<id>https://git.raptorcs.com/git/talos-obmc-linux/atom?h=dev-4.13</id>
<link rel='self' href='https://git.raptorcs.com/git/talos-obmc-linux/atom?h=dev-4.13'/>
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<updated>2017-11-02T08:54:45+00:00</updated>
<entry>
<title>nvme-fc: fix iowait hang</title>
<updated>2017-11-02T08:54:45+00:00</updated>
<author>
<name>James Smart</name>
<email>jsmart2021@gmail.com</email>
</author>
<published>2017-10-09T20:39:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/commit/?id=ac307385849db68fbdb4ce9665f25c84c3623089'/>
<id>urn:sha1:ac307385849db68fbdb4ce9665f25c84c3623089</id>
<content type='text'>
commit 8a82dbf19129dde9e6fc9ab25a00dbc7569abe6a upstream.

Add missing iowait head initialization.
Fix irqsave vs irq: wait_event_lock_irq() doesn't do irq save/restore

Fixes: 36715cf4b366 ("nvme_fc: replace ioabort msleep loop with completion”)
Signed-off-by: James Smart &lt;james.smart@broadcom.com&gt;
Reviewed-by: Sagi Grimberg &lt;sagi@grimberg.me&gt;
Reviewed-by: Himanshu Madhani &lt;himanshu.madhani@cavium.com&gt;
Tested-by: Himanshu Madhani &lt;himanshu.madhani@cavium.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>nvme-pci: Use PCI bus address for data/queues in CMB</title>
<updated>2017-10-12T09:56:19+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2017-10-01T07:37:35+00:00</published>
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<id>urn:sha1:598b587120d1364d0d58097dac99f209aaadf917</id>
<content type='text'>
commit 8969f1f8291762c13147c1ba89d46238af01675b upstream.

Currently, NVMe PCI host driver is programming CMB dma address as
I/O SQs addresses. This results in failures on systems where 1:1
outbound mapping is not used (example Broadcom iProc SOCs) because
CMB BAR will be progammed with PCI bus address but NVMe PCI EP will
try to access CMB using dma address.

To have CMB working on systems without 1:1 outbound mapping, we
program PCI bus address for I/O SQs instead of dma address. This
approach will work on systems with/without 1:1 outbound mapping.

Based on a report and previous patch from Abhishek Shah.

Fixes: 8ffaadf7 ("NVMe: Use CMB for the IO SQes if available")
Reported-by: Abhishek Shah &lt;abhishek.shah@broadcom.com&gt;
Tested-by: Abhishek Shah &lt;abhishek.shah@broadcom.com&gt;
Reviewed-by: Keith Busch &lt;keith.busch@intel.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>nvme-pci: propagate (some) errors from host memory buffer setup</title>
<updated>2017-10-05T07:47:24+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2017-09-06T10:19:57+00:00</published>
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<id>urn:sha1:8ce9fe2f84576f67e6a2407ff18995c54470e990</id>
<content type='text'>
commit 9620cfba97a8b88ae91f0e275e8ff110b578bb6e upstream.

We want to catch command execution errors when resetting the device, so
propagate errors from the Set Features when setting up the host memory
buffer.  We keep ignoring memory allocation failures, as the spec
clearly says that the controller must work without a host memory buffer.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Keith Busch &lt;keith.busch@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>nvme-pci: use appropriate initial chunk size for HMB allocation</title>
<updated>2017-10-05T07:47:24+00:00</updated>
<author>
<name>Akinobu Mita</name>
<email>akinobu.mita@gmail.com</email>
</author>
<published>2017-09-06T10:15:31+00:00</published>
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<id>urn:sha1:2e81e134465ed6fb4287d25d4e274ea436bf6936</id>
<content type='text'>
commit 30f92d62e5b41a94de2d0bbd677a6ea2fcfed74f upstream.

The initial chunk size for host memory buffer allocation is currently
PAGE_SIZE &lt;&lt; MAX_ORDER.  MAX_ORDER order allocation is usually failed
without CONFIG_DMA_CMA.  So the HMB allocation is retried with chunk size
PAGE_SIZE &lt;&lt; (MAX_ORDER - 1) in general, but there is no problem if the
retry allocation works correctly.

Signed-off-by: Akinobu Mita &lt;akinobu.mita@gmail.com&gt;
[hch: rebased]
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Keith Busch &lt;keith.busch@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>nvme-pci: fix host memory buffer allocation fallback</title>
<updated>2017-10-05T07:47:24+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2017-09-11T16:08:43+00:00</published>
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<id>urn:sha1:4230ffe5eeb424ad2e2ae7ca598770791af069dc</id>
<content type='text'>
commit 92dc689563170b90ba844b8a2eb95e8a5eda2e83 upstream.

nvme_alloc_host_mem currently contains two loops that are interwinded,
and the outer retry loop turns out to be broken.  Fix this by untangling
the two.

Based on a report an initial patch from Akinobu Mita.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reported-by: Akinobu Mita &lt;akinobu.mita@gmail.com&gt;
Tested-by: Akinobu Mita &lt;akinobu.mita@gmail.com&gt;
Reviewed-by: Keith Busch &lt;keith.busch@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>nvme-fabrics: generate spec-compliant UUID NQNs</title>
<updated>2017-09-13T21:20:52+00:00</updated>
<author>
<name>Daniel Verkamp</name>
<email>daniel.verkamp@intel.com</email>
</author>
<published>2017-08-30T22:18:19+00:00</published>
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<id>urn:sha1:b1bd28c3000115550253578e0fd6c60c3630e438</id>
<content type='text'>
commit 40a5fce495715c48c2e02668144e68a507ac5a30 upstream.

The default host NQN, which is generated based on the host's UUID,
does not follow the UUID-based NQN format laid out in the NVMe 1.3
specification.  Remove the "NVMf:" portion of the NQN to match the spec.

Signed-off-by: Daniel Verkamp &lt;daniel.verkamp@intel.com&gt;
Reviewed-by: Max Gurtovoy &lt;maxg@mellanox.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>nvme-pci: use dma memory for the host memory buffer descriptors</title>
<updated>2017-08-30T12:46:16+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2017-08-28T08:47:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/commit/?id=4033f35d174af4804a79fd5731d9e6be976f9f28'/>
<id>urn:sha1:4033f35d174af4804a79fd5731d9e6be976f9f28</id>
<content type='text'>
The NVMe 1.3 specification says in section 5.21.1.13:

"After a successful completion of a Set Features enabling the host memory
 buffer, the host shall not write to the associated host memory region,
 buffer size, or descriptor list until the host memory buffer has been
 disabled."

While this doesn't state that the descriptor list must remain accessible
to the device it certainly implies it must remaing readable by the device.

So switch to a dma coherent allocation for the descriptor list just to be
safe - it's not like the cost for it matters compared to the actual
memory buffers.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Keith Busch &lt;keith.busch@intel.com&gt;
Reviewed-by: Sagi Grimberg &lt;sagi@grimberg.me&gt;
Reviewed-by: Johannes Thumshirn &lt;jthumshirn@suse.de&gt;
Fixes: 87ad72a59a38 ("nvme-pci: implement host memory buffer support")
</content>
</entry>
<entry>
<title>nvme-rdma: default MR page size to 4k</title>
<updated>2017-08-30T12:46:10+00:00</updated>
<author>
<name>Max Gurtovoy</name>
<email>maxg@mellanox.com</email>
</author>
<published>2017-08-28T09:52:27+00:00</published>
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<id>urn:sha1:b925a2dc165e5ec2330ca1256704faef8ed96913</id>
<content type='text'>
Due to various page sizes in the system (IOMMU/device/kernel), we
set the fabrics controller page size to 4k and block layer boundaries
accordinglly. In architectures that uses different kernel page size
we'll have a mismatch to the MR page size that may cause a mapping error.
Update the MR page size to correspond to the core ctrl settings.

Signed-off-by: Max Gurtovoy &lt;maxg@mellanox.com&gt;
Reviewed-by: Sagi Grimberg &lt;sagi@grimberg.me&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>nvme-pci: set cqe_seen on polled completions</title>
<updated>2017-08-18T07:19:39+00:00</updated>
<author>
<name>Keith Busch</name>
<email>keith.busch@intel.com</email>
</author>
<published>2017-08-17T20:45:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/commit/?id=e9d8a0fdeacd843c85dcef480cdb2ab76bcdb6e4'/>
<id>urn:sha1:e9d8a0fdeacd843c85dcef480cdb2ab76bcdb6e4</id>
<content type='text'>
Fixes: 920d13a884 ("nvme-pci: factor out the cqe reading mechanics from __nvme_process_cq")
Reported-by: Jens Axboe &lt;axboe@kernel.dk&gt;
Signed-off-by: Keith Busch &lt;keith.busch@intel.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>nvme-fabrics: fix reporting of unrecognized options</title>
<updated>2017-08-17T16:48:54+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2017-08-17T11:57:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/commit/?id=81a0b8d74edd5841be29d223ce44bc8db2b00d09'/>
<id>urn:sha1:81a0b8d74edd5841be29d223ce44bc8db2b00d09</id>
<content type='text'>
Only print the specified options that are not recognized, instead
of the whole list of options.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Max Gurtovoy &lt;maxg@mellanox.com&gt;
</content>
</entry>
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