talos-obmc-linux/drivers/mtd, branch dev-5.0

Revert "mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization buffer"

2019-04-19T00:56:52+00:00

This reverts commit cb8980080ccb7879c5a8ef0e3efa783c9288d907. From Milton: > NACK > > [The] justifcation is false. The routine reads the whole buffer > because it calls the _rep routine and takes the size. > > In addition, the comment just before aspeed_smc_read_from_ahb > tells why memcpy_fromio and memcpy_toio are broken on 32 bit > arm, and this is still the case judging from the recent bug > reportfrom a Nuvoton user [1]. > > [1] https://github.com/openbmc/openbmc/issues/3521 OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: add support for the 4B opcodes

2019-04-18T01:41:23+00:00

Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization buffer

2019-04-18T01:41:20+00:00

aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: clarify 4BYTE address mode mask

2019-04-18T01:41:15+00:00

OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helper

2019-04-18T01:41:12+00:00

OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery

mtd: spi-nor: add NPCM FIU controller driver

2019-03-20T04:43:34+00:00

Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR controller driver The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. OpenBMC-Staging-Count: 2 Signed-off-by: Tomer Maimon [v5.0: Remove asm/size.h include to fix build] Signed-off-by: Joel Stanley

mtd: spi-nor: fix options for mx66l51235f

2019-03-20T04:43:33+00:00

Currently in driver spi-nor there is a line for mx66l51235l. According to Macronix site there is no such part number. The chip detected as such is actually mx66l51235f. According to the datasheet for mx66l51235f, "The device default is in 24-bit address mode" (section 9-10). Hence we removed SPI_NOR_4B_OPCODES option with this commit. OpenBMC-Staging-Count: 4 Fixes: d342b6a973af ("mtd: spi-nor: enable 4B opcodes for mx66l51235l") Signed-off-by: Alexander Soldatov Reviewed-by: Cédric Le Goater Reviewed-by: Lei YU Signed-off-by: Joel Stanley

mtd: spi-nor: aspeed: limit the maximum SPI frequency

2019-03-20T04:43:32+00:00

The optimize read algo can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the optimize read algorithm and we run the algo on the FMC controller chips as well. By default, the frequency setting is 50MHz. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley

mtd: spi-nor: aspeed: optimize read mode

2019-03-20T04:43:32+00:00

This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 5 Signed-off-by: Cédric Le Goater Signed-off-by: Alexander Soldatov Signed-off-by: Joel Stanley

mtd: spi-nor: aspeed: link controller with the ahb clock

2019-03-20T04:43:32+00:00

We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 5 Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley