talos-obmc-linux/drivers/mtd, branch dev-4.13

mtd: spi-nor: aspeed: optimize read mode

2017-11-28T04:02:32+00:00

This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley

mtd: spi-nor: aspeed: link controller with the ahb clock

2017-11-28T04:02:28+00:00

We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley

mtd: spi-nor: aspeed: add support for SPI dual IO read mode

2017-11-28T04:02:20+00:00

Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Still to be done SNOR_PROTO_1_2_2 Based on work from Robert Lippert OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley

mtd: spi-nor: aspeed: use command mode for reads

2017-11-28T04:02:16+00:00

When reading flash contents, try to use the "command mode" if the AHB window configured for the flash module is big enough. Else, just fall back to the "user mode" to perform the read. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley

mtd: spi-nor: aspeed: set 4B setting for all chips

2017-10-09T07:00:38+00:00

The driver made the wrong assumption that the 4B setting was autodetected for all chips of the AST2500 FMC flash controller. This is only the case for the CS0. Signed-off-by: Cédric Le Goater Signed-off-by: Cyrille Pitchen (cherry picked from commit 811cb897564625f196258f15bab485b9bbdd7a36) Signed-off-by: Joel Stanley

mtd: nand: atmel: fix buffer overflow in atmel_pmecc_user

2017-10-05T07:47:34+00:00

commit 36de80740008e6a4a55115b4a92e2059e47c1cba upstream. When calculating the size needed by struct atmel_pmecc_user *user, the dmu and delta buffer sizes were forgotten. This lead to a memory corruption (especially with a large ecc_strength). Link: http://lkml.kernel.org/r/1506503157.3016.5.camel@gmail.com Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Reported-by: Richard Genoud Pointed-at-by: Boris Brezillon Signed-off-by: Richard Genoud Reviewed-by: Nicolas Ferre Signed-off-by: Boris Brezillon Signed-off-by: Greg Kroah-Hartman

mtd: Fix partition alignment check on multi-erasesize devices

2017-10-05T07:47:34+00:00

commit 7e439681af82984045efc215437ebb2ca8d33a4c upstream. Commit 1eeef2d7483a ("mtd: handle partitioning on devices with 0 erasesize") introduced a regression on heterogeneous erase region devices. Alignment of the partition was tested against the master eraseblock size which can be bigger than the slave one, thus leading to some partitions being marked as read-only. Update wr_alignment to match this slave erasesize after this erasesize has been determined by picking the biggest erasesize of all the regions embedded in the MTD partition. Reported-by: Mathias Thore Fixes: 1eeef2d7483a ("mtd: handle partitioning on devices with 0 erasesize") Signed-off-by: Boris Brezillon Tested-by: Mathias Thore Reviewed-by: Mathias Thore Signed-off-by: Greg Kroah-Hartman

mtd: nand: qcom: fix config error for BCH

2017-09-13T21:20:52+00:00

commit 10777de570016471fd929869c7830a7772893e39 upstream. The configuration for BCH is not correct in the current driver. The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the BCH ECC in which 0x1 : BCH_DISABLED 0x0 : BCH_ENABLED But currently host->bch_enabled is being assigned to BCH_DISABLED. Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver") Signed-off-by: Abhishek Sahu Reviewed-by: Archit Taneja Signed-off-by: Boris Brezillon Signed-off-by: Greg Kroah-Hartman

mtd: nand: qcom: fix read failure without complete bootchain

2017-09-13T21:20:52+00:00

commit d8a9b320a26c1ea28e51e4f3ecfb593d5aac2910 upstream. The NAND page read fails without complete boot chain since NAND_DEV_CMD_VLD value is not proper. The default power on reset value for this register is 0xe - ERASE_START_VALID | WRITE_START_VALID | READ_STOP_VALID The READ_START_VALID should be enabled for sending PAGE_READ command. READ_STOP_VALID should be cleared since normal NAND page read does not require READ_STOP command. Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver") Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu Signed-off-by: Boris Brezillon Signed-off-by: Greg Kroah-Hartman

mtd: nand: mxc: Fix mxc_v1 ooblayout

2017-09-13T21:20:52+00:00

commit 3bff08dffe3115a25ce04b95ea75f6d868572c60 upstream. Commit a894cf6c5a82 ("mtd: nand: mxc: switch to mtd_ooblayout_ops") introduced a bug in the OOB layout description. Even if the driver claims that 3 ECC bytes are reserved to protect 512 bytes of data, it's actually 5 ECC bytes to protect 512+6 bytes of data (some OOB bytes are also protected using extra ECC bytes). Fix the mxc_v1_ooblayout_{free,ecc}() functions to reflect this behavior. Signed-off-by: Boris Brezillon Fixes: a894cf6c5a82 ("mtd: nand: mxc: switch to mtd_ooblayout_ops") Signed-off-by: Boris Brezillon Signed-off-by: Greg Kroah-Hartman