talos-obmc-linux/drivers/i2c, branch dev-4.13

i2c: aspeed: Deassert reset in probe

2018-02-07T02:06:24+00:00

In order to use i2c from a cold boot, the i2c peripheral must be taken out of reset. We request a shared reset controller each time a bus driver is loaded, as the reset is shared between the 14 i2c buses. On remove the reset is asserted, which only touches the hardware once the last i2c bus is removed. The reset is required as the I2C buses will not work without releasing the reset. Previously the driver only worked with out of tree hacks that released this reset before the driver was loaded. Update the device tree bindings to reflect this. Signed-off-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Wolfram Sang (cherry picked from commit edd20e95bca4a5434f264d8ab40d729761479825) Signed-off-by: Joel Stanley

i2c: fsi: Add bus recovery for FSI algorithm

2018-01-18T17:17:10+00:00

Bus recovery should reset the engine and force clock the bus 9 times to recover most situations. OpenBMC-Staging-Count: 2 Signed-off-by: Edward A. James Signed-off-by: Joel Stanley

i2c: fsi: Add I2C master locking to FSI algorithm

2018-01-18T17:17:10+00:00

Since there are many ports per master, each with it's own adapter and chardev, we need some locking to prevent transfers from changing the master state while other transfers are in progress. OpenBMC-Staging-Count: 2 Signed-off-by: Edward A. James Signed-off-by: Joel Stanley

i2c: fsi: Add transfer implementation for FSI algorithm

2018-01-18T17:17:10+00:00

Execute I2C transfers from the FSI-attached I2C master. Use polling instead of interrupts as we have no hardware IRQ over FSI. OpenBMC-Staging-Count: 2 Signed-off-by: Edward A. James Signed-off-by: Joel Stanley

i2c: fsi: Add abort and hardware reset procedures

2018-01-18T17:17:09+00:00

Add abort procedure for failed transfers. Add engine and bus reset procedures to recover from as many faults as possible. OpenBMC-Staging-Count: 2 Signed-off-by: Edward A. James Signed-off-by: Joel Stanley

i2c: fsi: Add port structure to FSI algorithm

2018-01-18T17:17:09+00:00

Add and initialize I2C adapters for each port on the FSI-attached I2C master. Ports for each master are defined in the devicetree. OpenBMC-Staging-Count: 2 Signed-off-by: Edward A. James Signed-off-by: Joel Stanley

i2c: Add FSI-attached I2C master algorithm

2018-01-18T17:17:08+00:00

Add register definitions for FSI-attached I2C master and functions to access those registers over FSI. Add an FSI driver so that our I2C bus is probed up during an FSI scan. OpenBMC-Staging-Count: 2 Signed-off-by: Edward A. James Signed-off-by: Joel Stanley

Merge tag 'v4.13.16' into dev-4.13

2017-11-28T07:41:55+00:00

This is the 4.13.16 stable release

i2c: piix4: Fix SMBus port selection for AMD Family 17h chips

2017-10-27T08:39:13+00:00

commit 0fe16195f89173652cf111d7b384941b00c5aabd upstream. AMD Family 17h uses the KERNCZ SMBus controller. While its documentation is not publicly available, it is documented in the BIOS and Kernel Developer’s Guide for AMD Family 15h Models 60h-6Fh Processors. On this SMBus controller, the port select register is at PMx register 0x02, bit 4:3 (PMx00 register bit 20:19). Without this patch, the 4 SMBus channels on AMD Family 17h chips are mirrored and report the same chips on all channels. Signed-off-by: Guenter Roeck Reviewed-by: Jean Delvare Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman

i2c: ismt: Separate I2C block read from SMBus block read

2017-10-27T08:39:13+00:00

commit c6ebcedbab7ca78984959386012a17b21183e1a3 upstream. Commit b6c159a9cb69 ("i2c: ismt: Don't duplicate the receive length for block reads") broke I2C block reads. It aimed to fix normal SMBus block read, but changed the correct behavior of I2C block read in the process. According to Documentation/i2c/smbus-protocol, one vital difference between normal SMBus block read and I2C block read is that there is no byte count prefixed in the data sent on the wire: SMBus Block Read: i2c_smbus_read_block_data() S Addr Wr [A] Comm [A] S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P I2C Block Read: i2c_smbus_read_i2c_block_data() S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P Therefore the two transaction types need to be processed differently in the driver by copying of the dma_buffer as done previously for the I2C_SMBUS_I2C_BLOCK_DATA case. Fixes: b6c159a9cb69 ("i2c: ismt: Don't duplicate the receive length for block reads") Signed-off-by: Pontus Andersson Tested-by: Stephen Douthit Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman