talos-obmc-linux/drivers/gpu/ipu-v3, branch dev-4.13

Merge tag 'drm-for-v4.14' into dev-4.13

2018-04-19T02:00:20+00:00

This is the DRM tree that was merged into the mainline 4.14 kernel. The ASPEED GFX DRM driver requires functionaliy that was included in this tree, so we merge it back into the 4.13 OpenBMC tree. This should have no impact on other parts of the BMC. Signed-off-by: Joel Stanley

gpu: ipu-v3: add DRM dependency

2017-08-11T08:31:13+00:00

The new PRE/PRG driver code causes a link failure when IPUv3 is built-in, but DRM is built as a module: drivers/gpu/ipu-v3/ipu-pre.o: In function `ipu_pre_configure': ipu-pre.c:(.text.ipu_pre_configure+0x18): undefined reference to `drm_format_info' drivers/gpu/ipu-v3/ipu-prg.o: In function `ipu_prg_format_supported': ipu-prg.c:(.text.ipu_prg_format_supported+0x8): undefined reference to `drm_format_info' Adding a Kconfig dependency on DRM means we don't run into this problem any more. If DRM is disabled altogether, the IPUv3 driver is built without PRE/PRG support. Fixes: ea9c260514c1 ("gpu: ipu-v3: add driver for Prefetch Resolve Gasket") Link: https://patchwork.kernel.org/patch/9636665/ Signed-off-by: Arnd Bergmann [p.zabel@pengutronix.de: changed the dependency from DRM to DRM || !DRM, since the link failure only happens when DRM=m and IPUV3_CORE=y. Modified the commit message to reflect this.] Signed-off-by: Philipp Zabel

drm: Convert to using %pOF instead of full_name

2017-07-26T11:45:06+00:00

Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring Cc: Russell King Cc: David Airlie Cc: Daniel Vetter Cc: Jani Nikula Cc: Sean Paul Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: Javier Martinez Canillas Cc: Xinliang Liu Cc: Rongrong Zou Cc: Xinwei Kong Cc: Chen Feng Cc: CK Hu Cc: Philipp Zabel Cc: Matthias Brugger Cc: Neil Armstrong Cc: Carlo Caione Cc: Kevin Hilman Cc: Thierry Reding Cc: Laurent Pinchart Cc: Mark Yao Cc: Heiko Stuebner Cc: Maxime Ripard Cc: Chen-Yu Tsai Cc: Jyri Sarha Cc: Tomi Valkeinen Cc: dri-devel@lists.freedesktop.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Partially-Reviewed-by: Laurent Pinchart Reviewed-by: Philipp Zabel Acked-by: Maxime Ripard [seanpaul changed subject prefix and fixed conflict in stm/ltdc.c] Signed-off-by: Sean Paul Signed-off-by: Daniel Vetter

BackMerge tag 'v4.12-rc5' into drm-next

2017-06-16T03:58:27+00:00

Linux 4.12-rc5 for nouveau fixes

gpu: ipu-v3: vdic: include AUTO field order bit in ipu_vdi_set_field_order

2017-06-08T06:57:20+00:00

The field order selection in VDIC_C register uses different bits depending on whether the VDIC is receiving from a CSI ("AUTO") or from memory ("MAN"). Since the VDIC cannot receive from both CSI and memory at the same time, set or clear both field order bits to cover both cases. Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel

gpu: ipu-v3: remove interrupt busy waiting routine

2017-06-08T06:57:19+00:00

This is not used anymore since commit eb8c88808c83 ("drm/imx: add deferred plane disabling"), remove it. Signed-off-by: Philipp Zabel

gpu: ipu-v3: allocate ipuv3_channels as needed

2017-06-08T06:57:19+00:00

Most of the 64 IPUv3 DMA channels are never used, some of them (channels 16, 30, 32, 34-39, and 53-63) are even marked as reserved. Allocate the channel control structure only when a channel is actually requested, replace the fixed size array with a list, and remove the unused enabled and busy fields from the ipuv3_channel structure. Signed-off-by: Philipp Zabel

gpu: ipu-v3: Add support for double read/write reduction

2017-06-08T06:57:18+00:00

Allow to skip writing odd chroma rows by setting the RDRW bit for 4:2:0 chroma subsampled formats for any IDMAC write channel. This also allows to skip reading odd rows for the VDIC read channel. Signed-off-by: Philipp Zabel

gpu: ipu-v3: prg: remove counter load enable

2017-06-08T06:57:13+00:00

The counter load enable bit has no effect when the shadow register set is activated. As we always operate the PRG with shadow enabled it is safe to remove this. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: Fix CSI selection for VDIC

2017-06-06T08:21:34+00:00

The description of the CSI_SEL bit in the i.MX6 reference manual is incorrect. It states "This bit defines which CSI is the input to the IC. This bit is effective only if IC_INPUT is bit cleared". From experiment it was found this is in fact not correct. The CSI_SEL bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC receives from in that case. Signed-off-by: Marek Vasut Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel